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From: Jordan Crouse <jcrouse@codeaurora.org>
To: freedreno@lists.freedesktop.org
Cc: nm@ti.com, devicetree@vger.kernel.org, rnayak@codeaurora.org,
	linux-pm@vger.kernel.org, sboyd@kernel.org,
	linux-arm-msm@vger.kernel.org, dianders@chromium.org,
	dri-devel@lists.freedesktop.org, vireshk@kernel.org,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes
Date: Fri, 16 Mar 2018 12:51:52 -0600	[thread overview]
Message-ID: <20180316185152.32020-3-jcrouse@codeaurora.org> (raw)
In-Reply-To: <20180316185152.32020-1-jcrouse@codeaurora.org>

Add the nodes to describe the Adreno GPU and GMU devices.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 119 +++++++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 16b5f356ec96..854da6604417 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -312,4 +312,123 @@
 			};
 		};
 	};
+
+	adreno_smmu: arm,smmu-adreno@5040000 {
+		compatible = "qcom,msm8996-smmu-v2";
+		reg = <0x5040000 0x10000>;
+		#iommu-cells = <1>;
+		#global-interrupts = <2>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			 <&clock_gcc GCC_GPU_CFG_AHB_CLK>;
+		clock-names = "bus", "iface";
+
+		power-domains = <&clock_gpucc GPU_CX_GDSC>;
+	};
+
+	gpu_opp_table: adreno-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-710000000 {
+			opp-hz = /bits/ 64 <710000000>;
+			qcom,level = <416>;
+		};
+
+		opp-675000000 {
+			opp-hz = /bits/ 64 <675000000>;
+			qcom,level = <384>;
+		};
+
+		opp-596000000 {
+			opp-hz = /bits/ 64 <596000000>;
+			qcom,level = <320>;
+		};
+
+		opp-520000000 {
+			opp-hz = /bits/ 64 <520000000>;
+			qcom,level = <256>;
+		};
+
+		opp-414000000 {
+			opp-hz = /bits/ 64 <414000000>;
+			qcom,level = <192>;
+		};
+
+		opp-342000000 {
+			opp-hz = /bits/ 64 <342000000>;
+			qcom,level = <128>;
+		};
+
+		opp-257000000 {
+			opp-hz = /bits/ 64 <257000000>;
+			qcom,level = <64>;
+		};
+	};
+
+	gpu@5000000 {
+		compatible = "qcom,adreno-630.2", "qcom,adreno";
+		#stream-id-cells = <16>;
+
+		reg = <0x5000000 0x40000>;
+		reg-names = "kgsl_3d0_reg_memory";
+
+		/*
+		 * Look ma, no clocks! The GPU clocks and power are controlled
+		 * entirely by the GMU
+		 */
+
+		interrupts = <0 300 0>;
+		interrupt-names = "kgsl_3d0_irq";
+
+		iommus = <&adreno_smmu 0>;
+
+		operating-points-v2 = <&gpu_opp_table>;
+
+		gmu = <&gmu>;
+	};
+
+	gmu_opp_table: adreno-gmu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			qcom,level = <128>;
+		};
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			qcom,level = <48>;
+		};
+	};
+
+	gmu: gmu@506a000 {
+		compatible="qcom,adreno-gmu";
+
+		reg = <0x506a000 0x30000>, <0xb200000 0x300000>;
+		reg-names = "gmu", "gmu_pdc";
+
+		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hfi", "gmu";
+
+		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+			<&clock_gpucc GPU_CC_CXO_CLK>,
+			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
+		clock-names = "gmu", "cxo", "axi", "memnoc";
+
+		power-domains = <&clock_gpucc GPU_CX_GDSC>;
+		iommus = <&adreno_smmu 5>;
+
+		operating-points-v2 = <&gmu_opp_table>;
+	};
 };
-- 
2.16.1

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WARNING: multiple messages have this Message-ID (diff)
From: jcrouse@codeaurora.org (Jordan Crouse)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes
Date: Fri, 16 Mar 2018 12:51:52 -0600	[thread overview]
Message-ID: <20180316185152.32020-3-jcrouse@codeaurora.org> (raw)
In-Reply-To: <20180316185152.32020-1-jcrouse@codeaurora.org>

Add the nodes to describe the Adreno GPU and GMU devices.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 119 +++++++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 16b5f356ec96..854da6604417 100644
--- a/arch/arm64/boot/dts/qcom/sdm845.dtsi
+++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi
@@ -312,4 +312,123 @@
 			};
 		};
 	};
+
+	adreno_smmu: arm,smmu-adreno at 5040000 {
+		compatible = "qcom,msm8996-smmu-v2";
+		reg = <0x5040000 0x10000>;
+		#iommu-cells = <1>;
+		#global-interrupts = <2>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 364 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 365 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 366 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 367 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 368 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 369 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 370 IRQ_TYPE_EDGE_RISING>,
+			     <GIC_SPI 371 IRQ_TYPE_EDGE_RISING>;
+		clocks = <&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
+			 <&clock_gcc GCC_GPU_CFG_AHB_CLK>;
+		clock-names = "bus", "iface";
+
+		power-domains = <&clock_gpucc GPU_CX_GDSC>;
+	};
+
+	gpu_opp_table: adreno-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-710000000 {
+			opp-hz = /bits/ 64 <710000000>;
+			qcom,level = <416>;
+		};
+
+		opp-675000000 {
+			opp-hz = /bits/ 64 <675000000>;
+			qcom,level = <384>;
+		};
+
+		opp-596000000 {
+			opp-hz = /bits/ 64 <596000000>;
+			qcom,level = <320>;
+		};
+
+		opp-520000000 {
+			opp-hz = /bits/ 64 <520000000>;
+			qcom,level = <256>;
+		};
+
+		opp-414000000 {
+			opp-hz = /bits/ 64 <414000000>;
+			qcom,level = <192>;
+		};
+
+		opp-342000000 {
+			opp-hz = /bits/ 64 <342000000>;
+			qcom,level = <128>;
+		};
+
+		opp-257000000 {
+			opp-hz = /bits/ 64 <257000000>;
+			qcom,level = <64>;
+		};
+	};
+
+	gpu at 5000000 {
+		compatible = "qcom,adreno-630.2", "qcom,adreno";
+		#stream-id-cells = <16>;
+
+		reg = <0x5000000 0x40000>;
+		reg-names = "kgsl_3d0_reg_memory";
+
+		/*
+		 * Look ma, no clocks! The GPU clocks and power are controlled
+		 * entirely by the GMU
+		 */
+
+		interrupts = <0 300 0>;
+		interrupt-names = "kgsl_3d0_irq";
+
+		iommus = <&adreno_smmu 0>;
+
+		operating-points-v2 = <&gpu_opp_table>;
+
+		gmu = <&gmu>;
+	};
+
+	gmu_opp_table: adreno-gmu-opp-table {
+		compatible = "operating-points-v2";
+
+		opp-400000000 {
+			opp-hz = /bits/ 64 <400000000>;
+			qcom,level = <128>;
+		};
+
+		opp-200000000 {
+			opp-hz = /bits/ 64 <200000000>;
+			qcom,level = <48>;
+		};
+	};
+
+	gmu: gmu at 506a000 {
+		compatible="qcom,adreno-gmu";
+
+		reg = <0x506a000 0x30000>, <0xb200000 0x300000>;
+		reg-names = "gmu", "gmu_pdc";
+
+		interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>,
+			     <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>;
+		interrupt-names = "hfi", "gmu";
+
+		clocks = <&clock_gpucc GPU_CC_CX_GMU_CLK>,
+			<&clock_gpucc GPU_CC_CXO_CLK>,
+			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
+			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>;
+		clock-names = "gmu", "cxo", "axi", "memnoc";
+
+		power-domains = <&clock_gpucc GPU_CX_GDSC>;
+		iommus = <&adreno_smmu 5>;
+
+		operating-points-v2 = <&gmu_opp_table>;
+	};
 };
-- 
2.16.1

  parent reply	other threads:[~2018-03-16 18:51 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-16 18:51 [v2 PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse
2018-03-16 18:51 ` Jordan Crouse
     [not found] ` <20180316185152.32020-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-03-16 18:51   ` [PATCH 1/2] dt-bindings: Document qcom,adreno-gmu Jordan Crouse
2018-03-16 18:51     ` Jordan Crouse
     [not found]     ` <20180316185152.32020-2-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-03-26 22:23       ` Rob Herring
2018-03-26 22:23         ` Rob Herring
2018-03-20  3:44   ` [v2 PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Viresh Kumar
2018-03-20  3:44     ` Viresh Kumar
2018-03-16 18:51 ` Jordan Crouse [this message]
2018-03-16 18:51   ` [PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes Jordan Crouse
  -- strict thread matches above, loose matches on Subject: below --
2018-08-08 22:46 [v3 PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse
     [not found] ` <20180808224701.7527-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-08-08 22:47   ` [PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes Jordan Crouse
2018-08-08 22:47     ` Jordan Crouse
     [not found]     ` <20180808224701.7527-3-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-08-09  9:46       ` Robin Murphy
2018-08-09  9:46         ` Robin Murphy
2018-08-10 19:49       ` Stephen Boyd
2018-08-10 19:49         ` Stephen Boyd
2018-08-12  1:23       ` kbuild test robot
2018-08-12  1:23         ` kbuild test robot
2018-03-16 18:44 [v2 PATCH 0/2] arm64: dts: Add sdm845 GPU/GMU and SMMU Jordan Crouse
     [not found] ` <20180316184410.29863-1-jcrouse-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org>
2018-03-16 18:44   ` [PATCH 2/2] arm64: dts: sdm845: Add gpu and gmu device nodes Jordan Crouse

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