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* [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
@ 2018-04-05 11:49 Chris Wilson
  2018-04-05 12:25 ` ✗ Fi.CI.BAT: failure for " Patchwork
                   ` (3 more replies)
  0 siblings, 4 replies; 13+ messages in thread
From: Chris Wilson @ 2018-04-05 11:49 UTC (permalink / raw)
  To: intel-gfx; +Cc: Chris Wilson, Durgadoss R, Rodrigo Vivi, stable

Inside the psr work function, we want to wait for PSR to idle first and
wish to do so without blocking the normal modeset path, so we do so
without holding the PSR lock. However, we first have to find which pipe
PSR was enabled on, which requires chasing into the PSR struct and
requires locking to prevent intel_psr_disable() from concurrently
setting our pointer to NULL.

Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Durgadoss R <durgadoss.r@intel.com>
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Cc: <stable@vger.kernel.org> # v4.0+
---
 drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++-------------------
 1 file changed, 44 insertions(+), 38 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_psr.c b/drivers/gpu/drm/i915/intel_psr.c
index 2d53f7398a6d..69a5b276f4d8 100644
--- a/drivers/gpu/drm/i915/intel_psr.c
+++ b/drivers/gpu/drm/i915/intel_psr.c
@@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp *intel_dp,
 	cancel_delayed_work_sync(&dev_priv->psr.work);
 }
 
-static void intel_psr_work(struct work_struct *work)
+static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
 {
-	struct drm_i915_private *dev_priv =
-		container_of(work, typeof(*dev_priv), psr.work.work);
-	struct intel_dp *intel_dp = dev_priv->psr.enabled;
-	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
-	enum pipe pipe = to_intel_crtc(crtc)->pipe;
+	struct intel_dp *intel_dp;
+	i915_reg_t reg;
+	u32 mask;
+	int err;
+
+	intel_dp = dev_priv->psr.enabled;
+	if (!intel_dp)
+		return false;
 
-	/* We have to make sure PSR is ready for re-enable
-	 * otherwise it keeps disabled until next full enable/disable cycle.
-	 * PSR might take some time to get fully disabled
-	 * and be ready for re-enable.
-	 */
 	if (HAS_DDI(dev_priv)) {
 		if (dev_priv->psr.psr2_enabled) {
-			if (intel_wait_for_register(dev_priv,
-						    EDP_PSR2_STATUS,
-						    EDP_PSR2_STATUS_STATE_MASK,
-						    0,
-						    50)) {
-				DRM_ERROR("Timed out waiting for PSR2 Idle for re-enable\n");
-				return;
-			}
+			reg = EDP_PSR2_STATUS;
+			mask = EDP_PSR2_STATUS_STATE_MASK;
 		} else {
-			if (intel_wait_for_register(dev_priv,
-						    EDP_PSR_STATUS,
-						    EDP_PSR_STATUS_STATE_MASK,
-						    0,
-						    50)) {
-				DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
-				return;
-			}
+			reg = EDP_PSR_STATUS;
+			mask = EDP_PSR_STATUS_STATE_MASK;
 		}
 	} else {
-		if (intel_wait_for_register(dev_priv,
-					    VLV_PSRSTAT(pipe),
-					    VLV_EDP_PSR_IN_TRANS,
-					    0,
-					    1)) {
-			DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
-			return;
-		}
+		struct drm_crtc *crtc =
+			dp_to_dig_port(intel_dp)->base.base.crtc;
+		enum pipe pipe = to_intel_crtc(crtc)->pipe;
+
+		reg = VLV_PSRSTAT(pipe);
+		mask = VLV_EDP_PSR_IN_TRANS;
 	}
+
+	mutex_unlock(&dev_priv->psr.lock);
+
+	err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
+	if (err)
+		DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
+
+	/* After the unlocked wait, verify that PSR is still wanted! */
 	mutex_lock(&dev_priv->psr.lock);
-	intel_dp = dev_priv->psr.enabled;
+	return err == 0 && dev_priv->psr.enabled;
+}
 
-	if (!intel_dp)
+static void intel_psr_work(struct work_struct *work)
+{
+	struct drm_i915_private *dev_priv =
+		container_of(work, typeof(*dev_priv), psr.work.work);
+
+	mutex_lock(&dev_priv->psr.lock);
+
+	/*
+	 * We have to make sure PSR is ready for re-enable
+	 * otherwise it keeps disabled until next full enable/disable cycle.
+	 * PSR might take some time to get fully disabled
+	 * and be ready for re-enable.
+	 */
+	if (!psr_wait_for_idle(dev_priv))
 		goto unlock;
 
 	/*
@@ -832,7 +838,7 @@ static void intel_psr_work(struct work_struct *work)
 	if (dev_priv->psr.busy_frontbuffer_bits)
 		goto unlock;
 
-	intel_psr_activate(intel_dp);
+	intel_psr_activate(dev_priv->psr.enabled);
 unlock:
 	mutex_unlock(&dev_priv->psr.lock);
 }
-- 
2.16.3

^ permalink raw reply related	[flat|nested] 13+ messages in thread

* ✗ Fi.CI.BAT: failure for drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-05 11:49 [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock Chris Wilson
@ 2018-04-05 12:25 ` Patchwork
  2018-04-05 13:06 ` ✓ Fi.CI.BAT: success " Patchwork
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-04-05 12:25 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/psr: Chase psr.enabled only under the psr.lock
URL   : https://patchwork.freedesktop.org/series/41205/
State : failure

== Summary ==

Series 41205v1 drm/i915/psr: Chase psr.enabled only under the psr.lock
https://patchwork.freedesktop.org/api/1.0/series/41205/revisions/1/mbox/

---- Possible new issues:

Test gem_exec_flush:
        Subgroup basic-uc-pro-default:
                pass       -> INCOMPLETE (fi-cnl-y3)

---- Known issues:

Test kms_flip:
        Subgroup basic-flip-vs-wf_vblank:
                pass       -> FAIL       (fi-cfl-s3) fdo#100368
Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                dmesg-warn -> PASS       (fi-glk-j4005) fdo#105644
Test prime_vgem:
        Subgroup basic-fence-flip:
                fail       -> PASS       (fi-ilk-650) fdo#104008

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#105644 https://bugs.freedesktop.org/show_bug.cgi?id=105644
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:429s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:443s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:386s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:541s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:302s
fi-bxt-dsi       total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  time:516s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:513s
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:525s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:508s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:409s
fi-cfl-s3        total:285  pass:258  dwarn:0   dfail:0   fail:1   skip:26  time:557s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:512s
fi-cnl-y3        total:53   pass:45   dwarn:0   dfail:0   fail:0   skip:7  
fi-elk-e7500     total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  time:426s
fi-gdg-551       total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 time:318s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:540s
fi-glk-j4005     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:494s
fi-hsw-4770      total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:406s
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:425s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:462s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:432s
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:473s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:465s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:508s
fi-pnv-d510      total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:639s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:442s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:531s
fi-skl-6700k2    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:509s
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:516s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:430s
fi-skl-gvtdvm    total:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  time:447s
fi-snb-2600      total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:406s
Blacklisted hosts:
fi-cnl-psr       total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  time:520s

0eddede73765b01ec287cad00e23bee23c216a16 drm-tip: 2018y-04m-05d-09h-51m-03s UTC integration manifest
4cf1e254d4ff drm/i915/psr: Chase psr.enabled only under the psr.lock

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8592/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread

* ✓ Fi.CI.BAT: success for drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-05 11:49 [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock Chris Wilson
  2018-04-05 12:25 ` ✗ Fi.CI.BAT: failure for " Patchwork
@ 2018-04-05 13:06 ` Patchwork
  2018-04-05 14:54 ` ✓ Fi.CI.IGT: " Patchwork
  2018-04-06 18:12 ` [Intel-gfx] [PATCH] " Souza, Jose
  3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-04-05 13:06 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/psr: Chase psr.enabled only under the psr.lock
URL   : https://patchwork.freedesktop.org/series/41205/
State : success

== Summary ==

Series 41205v1 drm/i915/psr: Chase psr.enabled only under the psr.lock
https://patchwork.freedesktop.org/api/1.0/series/41205/revisions/1/mbox/

---- Known issues:

Test kms_pipe_crc_basic:
        Subgroup suspend-read-crc-pipe-c:
                dmesg-warn -> PASS       (fi-glk-j4005) fdo#105644
Test prime_vgem:
        Subgroup basic-fence-flip:
                fail       -> PASS       (fi-ilk-650) fdo#104008

fdo#105644 https://bugs.freedesktop.org/show_bug.cgi?id=105644
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008

fi-bdw-5557u     total:285  pass:264  dwarn:0   dfail:0   fail:0   skip:21  time:433s
fi-bdw-gvtdvm    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:441s
fi-blb-e6850     total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:381s
fi-bsw-n3050     total:285  pass:239  dwarn:0   dfail:0   fail:0   skip:46  time:540s
fi-bwr-2160      total:285  pass:180  dwarn:0   dfail:0   fail:0   skip:105 time:296s
fi-bxt-dsi       total:285  pass:255  dwarn:0   dfail:0   fail:0   skip:30  time:517s
fi-bxt-j4205     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:520s
fi-byt-j1900     total:285  pass:250  dwarn:0   dfail:0   fail:0   skip:35  time:521s
fi-byt-n2820     total:285  pass:246  dwarn:0   dfail:0   fail:0   skip:39  time:505s
fi-cfl-8700k     total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:412s
fi-cfl-s3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:559s
fi-cfl-u         total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:512s
fi-cnl-y3        total:285  pass:259  dwarn:0   dfail:0   fail:0   skip:26  time:582s
fi-elk-e7500     total:285  pass:226  dwarn:0   dfail:0   fail:0   skip:59  time:419s
fi-gdg-551       total:285  pass:176  dwarn:0   dfail:0   fail:1   skip:108 time:314s
fi-glk-1         total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:538s
fi-glk-j4005     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:488s
fi-hsw-4770      total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:406s
fi-ilk-650       total:285  pass:225  dwarn:0   dfail:0   fail:0   skip:60  time:421s
fi-ivb-3520m     total:285  pass:256  dwarn:0   dfail:0   fail:0   skip:29  time:478s
fi-ivb-3770      total:285  pass:252  dwarn:0   dfail:0   fail:0   skip:33  time:432s
fi-kbl-7500u     total:285  pass:260  dwarn:1   dfail:0   fail:0   skip:24  time:473s
fi-kbl-7567u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:463s
fi-kbl-r         total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:509s
fi-pnv-d510      total:285  pass:220  dwarn:1   dfail:0   fail:0   skip:64  time:673s
fi-skl-6260u     total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:447s
fi-skl-6600u     total:285  pass:258  dwarn:0   dfail:0   fail:0   skip:27  time:534s
fi-skl-6700k2    total:285  pass:261  dwarn:0   dfail:0   fail:0   skip:24  time:508s
fi-skl-6770hq    total:285  pass:265  dwarn:0   dfail:0   fail:0   skip:20  time:490s
fi-skl-guc       total:285  pass:257  dwarn:0   dfail:0   fail:0   skip:28  time:430s
fi-skl-gvtdvm    total:285  pass:262  dwarn:0   dfail:0   fail:0   skip:23  time:447s
fi-snb-2520m     total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:566s
fi-snb-2600      total:285  pass:245  dwarn:0   dfail:0   fail:0   skip:40  time:400s
Blacklisted hosts:
fi-cnl-psr       total:285  pass:256  dwarn:3   dfail:0   fail:0   skip:26  time:537s

0eddede73765b01ec287cad00e23bee23c216a16 drm-tip: 2018y-04m-05d-09h-51m-03s UTC integration manifest
f04a2e0277ad drm/i915/psr: Chase psr.enabled only under the psr.lock

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8594/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread

* ✓ Fi.CI.IGT: success for drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-05 11:49 [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock Chris Wilson
  2018-04-05 12:25 ` ✗ Fi.CI.BAT: failure for " Patchwork
  2018-04-05 13:06 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2018-04-05 14:54 ` Patchwork
  2018-04-06 18:12 ` [Intel-gfx] [PATCH] " Souza, Jose
  3 siblings, 0 replies; 13+ messages in thread
From: Patchwork @ 2018-04-05 14:54 UTC (permalink / raw)
  To: Chris Wilson; +Cc: intel-gfx

== Series Details ==

Series: drm/i915/psr: Chase psr.enabled only under the psr.lock
URL   : https://patchwork.freedesktop.org/series/41205/
State : success

== Summary ==

---- Possible new issues:

Test kms_cursor_legacy:
        Subgroup cursor-vs-flip-toggle:
                fail       -> PASS       (shard-hsw)

---- Known issues:

Test kms_flip:
        Subgroup plain-flip-fb-recreate:
                pass       -> FAIL       (shard-hsw) fdo#100368
Test kms_frontbuffer_tracking:
        Subgroup fbc-1p-primscrn-pri-indfb-draw-render:
                fail       -> PASS       (shard-snb) fdo#103167
Test perf:
        Subgroup polling:
                pass       -> FAIL       (shard-hsw) fdo#102252

fdo#100368 https://bugs.freedesktop.org/show_bug.cgi?id=100368
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#102252 https://bugs.freedesktop.org/show_bug.cgi?id=102252

shard-apl        total:2680 pass:1835 dwarn:1   dfail:0   fail:7   skip:836 time:12639s
shard-hsw        total:2680 pass:1784 dwarn:1   dfail:0   fail:3   skip:891 time:11365s
shard-snb        total:2680 pass:1376 dwarn:1   dfail:0   fail:4   skip:1299 time:6949s
Blacklisted hosts:
shard-kbl        total:2622 pass:1865 dwarn:1   dfail:0   fail:13  skip:742 time:8746s

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_8594/shards.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-05 11:49 [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock Chris Wilson
                   ` (2 preceding siblings ...)
  2018-04-05 14:54 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-04-06 18:12 ` Souza, Jose
  2018-04-06 22:18     ` [Intel-gfx] " Rodrigo Vivi
  2018-04-10 10:30   ` Chris Wilson
  3 siblings, 2 replies; 13+ messages in thread
From: Souza, Jose @ 2018-04-06 18:12 UTC (permalink / raw)
  To: intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk
  Cc: Vivi, Rodrigo, R, Durgadoss, stable@vger.kernel.org

On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> Inside the psr work function, we want to wait for PSR to idle first
> and
> wish to do so without blocking the normal modeset path, so we do so
> without holding the PSR lock. However, we first have to find which
> pipe
> PSR was enabled on, which requires chasing into the PSR struct and
> requires locking to prevent intel_psr_disable() from concurrently
> setting our pointer to NULL.
> 
> Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode")
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Durgadoss R <durgadoss.r@intel.com>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: <stable@vger.kernel.org> # v4.0+

Feel free to add:
Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>

> ---
>  drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++---------
> ----------
>  1 file changed, 44 insertions(+), 38 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/intel_psr.c
> b/drivers/gpu/drm/i915/intel_psr.c
> index 2d53f7398a6d..69a5b276f4d8 100644
> --- a/drivers/gpu/drm/i915/intel_psr.c
> +++ b/drivers/gpu/drm/i915/intel_psr.c
> @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp
> *intel_dp,
>  	cancel_delayed_work_sync(&dev_priv->psr.work);
>  }
>  
> -static void intel_psr_work(struct work_struct *work)
> +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
>  {
> -	struct drm_i915_private *dev_priv =
> -		container_of(work, typeof(*dev_priv),
> psr.work.work);
> -	struct intel_dp *intel_dp = dev_priv->psr.enabled;
> -	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)-
> >base.base.crtc;
> -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +	struct intel_dp *intel_dp;

nitpick: Why not already set it?
struct intel_dp *intel_dp = dev_priv->psr.enabled;


> +	i915_reg_t reg;
> +	u32 mask;
> +	int err;
> +
> +	intel_dp = dev_priv->psr.enabled;
> +	if (!intel_dp)
> +		return false;
>  
> -	/* We have to make sure PSR is ready for re-enable
> -	 * otherwise it keeps disabled until next full
> enable/disable cycle.
> -	 * PSR might take some time to get fully disabled
> -	 * and be ready for re-enable.
> -	 */
>  	if (HAS_DDI(dev_priv)) {


nitpick: While on that you could replace this for:

if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) {

>  		if (dev_priv->psr.psr2_enabled) {
> -			if (intel_wait_for_register(dev_priv,
> -						    EDP_PSR2_STATUS,
> -						    EDP_PSR2_STATUS_
> STATE_MASK,
> -						    0,
> -						    50)) {
> -				DRM_ERROR("Timed out waiting for
> PSR2 Idle for re-enable\n");
> -				return;
> -			}
> +			reg = EDP_PSR2_STATUS;
> +			mask = EDP_PSR2_STATUS_STATE_MASK;
>  		} else {
> -			if (intel_wait_for_register(dev_priv,
> -						    EDP_PSR_STATUS,
> -						    EDP_PSR_STATUS_S
> TATE_MASK,
> -						    0,
> -						    50)) {
> -				DRM_ERROR("Timed out waiting for PSR
> Idle for re-enable\n");
> -				return;
> -			}
> +			reg = EDP_PSR_STATUS;
> +			mask = EDP_PSR_STATUS_STATE_MASK;
>  		}
>  	} else {
> -		if (intel_wait_for_register(dev_priv,
> -					    VLV_PSRSTAT(pipe),
> -					    VLV_EDP_PSR_IN_TRANS,
> -					    0,
> -					    1)) {
> -			DRM_ERROR("Timed out waiting for PSR Idle
> for re-enable\n");
> -			return;
> -		}
> +		struct drm_crtc *crtc =
> +			dp_to_dig_port(intel_dp)->base.base.crtc;
> +		enum pipe pipe = to_intel_crtc(crtc)->pipe;
> +
> +		reg = VLV_PSRSTAT(pipe);
> +		mask = VLV_EDP_PSR_IN_TRANS;
>  	}
> +
> +	mutex_unlock(&dev_priv->psr.lock);
> +
> +	err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
> +	if (err)
> +		DRM_ERROR("Timed out waiting for PSR Idle for re-
> enable\n");
> +
> +	/* After the unlocked wait, verify that PSR is still wanted!
> */
>  	mutex_lock(&dev_priv->psr.lock);
> -	intel_dp = dev_priv->psr.enabled;
> +	return err == 0 && dev_priv->psr.enabled;
> +}
>  
> -	if (!intel_dp)
> +static void intel_psr_work(struct work_struct *work)
> +{
> +	struct drm_i915_private *dev_priv =
> +		container_of(work, typeof(*dev_priv),
> psr.work.work);
> +
> +	mutex_lock(&dev_priv->psr.lock);
> +
> +	/*
> +	 * We have to make sure PSR is ready for re-enable
> +	 * otherwise it keeps disabled until next full
> enable/disable cycle.
> +	 * PSR might take some time to get fully disabled
> +	 * and be ready for re-enable.
> +	 */
> +	if (!psr_wait_for_idle(dev_priv))
>  		goto unlock;
>  
>  	/*
> @@ -832,7 +838,7 @@ static void intel_psr_work(struct work_struct
> *work)
>  	if (dev_priv->psr.busy_frontbuffer_bits)
>  		goto unlock;
>  
> -	intel_psr_activate(intel_dp);
> +	intel_psr_activate(dev_priv->psr.enabled);
>  unlock:
>  	mutex_unlock(&dev_priv->psr.lock);
>  }

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-06 18:12 ` [Intel-gfx] [PATCH] " Souza, Jose
@ 2018-04-06 22:18     ` Rodrigo Vivi
  2018-04-10 10:30   ` Chris Wilson
  1 sibling, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2018-04-06 22:18 UTC (permalink / raw)
  To: Souza, Jose
  Cc: intel-gfx@lists.freedesktop.org, R, Durgadoss,
	stable@vger.kernel.org

On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > Inside the psr work function, we want to wait for PSR to idle first
> > and
> > wish to do so without blocking the normal modeset path, so we do so
> > without holding the PSR lock. However, we first have to find which
> > pipe
> > PSR was enabled on, which requires chasing into the PSR struct and
> > requires locking to prevent intel_psr_disable() from concurrently
> > setting our pointer to NULL.
> > 
> > Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Durgadoss R <durgadoss.r@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: <stable@vger.kernel.org> # v4.0+
> 
> Feel free to add:
> Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++---------
> > ----------
> >  1 file changed, 44 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 2d53f7398a6d..69a5b276f4d8 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> >  	cancel_delayed_work_sync(&dev_priv->psr.work);
> >  }
> >  
> > -static void intel_psr_work(struct work_struct *work)
> > +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
> >  {
> > -	struct drm_i915_private *dev_priv =
> > -		container_of(work, typeof(*dev_priv),
> > psr.work.work);
> > -	struct intel_dp *intel_dp = dev_priv->psr.enabled;
> > -	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)-
> > >base.base.crtc;
> > -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > +	struct intel_dp *intel_dp;
> 
> nitpick: Why not already set it?
> struct intel_dp *intel_dp = dev_priv->psr.enabled;
> 
> 
> > +	i915_reg_t reg;
> > +	u32 mask;
> > +	int err;
> > +
> > +	intel_dp = dev_priv->psr.enabled;
> > +	if (!intel_dp)
> > +		return false;
> >  
> > -	/* We have to make sure PSR is ready for re-enable
> > -	 * otherwise it keeps disabled until next full
> > enable/disable cycle.
> > -	 * PSR might take some time to get fully disabled
> > -	 * and be ready for re-enable.
> > -	 */
> >  	if (HAS_DDI(dev_priv)) {
> 
> 
> nitpick: While on that you could replace this for:
> 
> if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) {
> 
> >  		if (dev_priv->psr.psr2_enabled) {
> > -			if (intel_wait_for_register(dev_priv,
> > -						    EDP_PSR2_STATUS,
> > -						    EDP_PSR2_STATUS_
> > STATE_MASK,
> > -						    0,
> > -						    50)) {
> > -				DRM_ERROR("Timed out waiting for
> > PSR2 Idle for re-enable\n");
> > -				return;
> > -			}
> > +			reg = EDP_PSR2_STATUS;
> > +			mask = EDP_PSR2_STATUS_STATE_MASK;
> >  		} else {
> > -			if (intel_wait_for_register(dev_priv,
> > -						    EDP_PSR_STATUS,
> > -						    EDP_PSR_STATUS_S
> > TATE_MASK,
> > -						    0,
> > -						    50)) {
> > -				DRM_ERROR("Timed out waiting for PSR
> > Idle for re-enable\n");
> > -				return;
> > -			}
> > +			reg = EDP_PSR_STATUS;
> > +			mask = EDP_PSR_STATUS_STATE_MASK;
> >  		}
> >  	} else {
> > -		if (intel_wait_for_register(dev_priv,
> > -					    VLV_PSRSTAT(pipe),
> > -					    VLV_EDP_PSR_IN_TRANS,
> > -					    0,
> > -					    1)) {
> > -			DRM_ERROR("Timed out waiting for PSR Idle
> > for re-enable\n");
> > -			return;
> > -		}
> > +		struct drm_crtc *crtc =
> > +			dp_to_dig_port(intel_dp)->base.base.crtc;

I'm afraid that the issue is this pointer here. So this will only mask
the issue.

Should we maybe stash the pipe? :/

> > +		enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > +
> > +		reg = VLV_PSRSTAT(pipe);
> > +		mask = VLV_EDP_PSR_IN_TRANS;
> >  	}
> > +
> > +	mutex_unlock(&dev_priv->psr.lock);
> > +
> > +	err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
> > +	if (err)
> > +		DRM_ERROR("Timed out waiting for PSR Idle for re-
> > enable\n");
> > +
> > +	/* After the unlocked wait, verify that PSR is still wanted!
> > */
> >  	mutex_lock(&dev_priv->psr.lock);
> > -	intel_dp = dev_priv->psr.enabled;
> > +	return err == 0 && dev_priv->psr.enabled;
> > +}
> >  
> > -	if (!intel_dp)
> > +static void intel_psr_work(struct work_struct *work)
> > +{
> > +	struct drm_i915_private *dev_priv =
> > +		container_of(work, typeof(*dev_priv),
> > psr.work.work);
> > +
> > +	mutex_lock(&dev_priv->psr.lock);
> > +
> > +	/*
> > +	 * We have to make sure PSR is ready for re-enable
> > +	 * otherwise it keeps disabled until next full
> > enable/disable cycle.
> > +	 * PSR might take some time to get fully disabled
> > +	 * and be ready for re-enable.
> > +	 */
> > +	if (!psr_wait_for_idle(dev_priv))
> >  		goto unlock;
> >  
> >  	/*
> > @@ -832,7 +838,7 @@ static void intel_psr_work(struct work_struct
> > *work)
> >  	if (dev_priv->psr.busy_frontbuffer_bits)
> >  		goto unlock;
> >  
> > -	intel_psr_activate(intel_dp);
> > +	intel_psr_activate(dev_priv->psr.enabled);
> >  unlock:
> >  	mutex_unlock(&dev_priv->psr.lock);
> >  }
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
@ 2018-04-06 22:18     ` Rodrigo Vivi
  0 siblings, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2018-04-06 22:18 UTC (permalink / raw)
  To: Souza, Jose
  Cc: intel-gfx@lists.freedesktop.org, chris@chris-wilson.co.uk,
	R, Durgadoss, stable@vger.kernel.org

On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > Inside the psr work function, we want to wait for PSR to idle first
> > and
> > wish to do so without blocking the normal modeset path, so we do so
> > without holding the PSR lock. However, we first have to find which
> > pipe
> > PSR was enabled on, which requires chasing into the PSR struct and
> > requires locking to prevent intel_psr_disable() from concurrently
> > setting our pointer to NULL.
> > 
> > Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Durgadoss R <durgadoss.r@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: <stable@vger.kernel.org> # v4.0+
> 
> Feel free to add:
> Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++---------
> > ----------
> >  1 file changed, 44 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 2d53f7398a6d..69a5b276f4d8 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> >  	cancel_delayed_work_sync(&dev_priv->psr.work);
> >  }
> >  
> > -static void intel_psr_work(struct work_struct *work)
> > +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
> >  {
> > -	struct drm_i915_private *dev_priv =
> > -		container_of(work, typeof(*dev_priv),
> > psr.work.work);
> > -	struct intel_dp *intel_dp = dev_priv->psr.enabled;
> > -	struct drm_crtc *crtc = dp_to_dig_port(intel_dp)-
> > >base.base.crtc;
> > -	enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > +	struct intel_dp *intel_dp;
> 
> nitpick: Why not already set it?
> struct intel_dp *intel_dp = dev_priv->psr.enabled;
> 
> 
> > +	i915_reg_t reg;
> > +	u32 mask;
> > +	int err;
> > +
> > +	intel_dp = dev_priv->psr.enabled;
> > +	if (!intel_dp)
> > +		return false;
> >  
> > -	/* We have to make sure PSR is ready for re-enable
> > -	 * otherwise it keeps disabled until next full
> > enable/disable cycle.
> > -	 * PSR might take some time to get fully disabled
> > -	 * and be ready for re-enable.
> > -	 */
> >  	if (HAS_DDI(dev_priv)) {
> 
> 
> nitpick: While on that you could replace this for:
> 
> if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) {
> 
> >  		if (dev_priv->psr.psr2_enabled) {
> > -			if (intel_wait_for_register(dev_priv,
> > -						    EDP_PSR2_STATUS,
> > -						    EDP_PSR2_STATUS_
> > STATE_MASK,
> > -						    0,
> > -						    50)) {
> > -				DRM_ERROR("Timed out waiting for
> > PSR2 Idle for re-enable\n");
> > -				return;
> > -			}
> > +			reg = EDP_PSR2_STATUS;
> > +			mask = EDP_PSR2_STATUS_STATE_MASK;
> >  		} else {
> > -			if (intel_wait_for_register(dev_priv,
> > -						    EDP_PSR_STATUS,
> > -						    EDP_PSR_STATUS_S
> > TATE_MASK,
> > -						    0,
> > -						    50)) {
> > -				DRM_ERROR("Timed out waiting for PSR
> > Idle for re-enable\n");
> > -				return;
> > -			}
> > +			reg = EDP_PSR_STATUS;
> > +			mask = EDP_PSR_STATUS_STATE_MASK;
> >  		}
> >  	} else {
> > -		if (intel_wait_for_register(dev_priv,
> > -					    VLV_PSRSTAT(pipe),
> > -					    VLV_EDP_PSR_IN_TRANS,
> > -					    0,
> > -					    1)) {
> > -			DRM_ERROR("Timed out waiting for PSR Idle
> > for re-enable\n");
> > -			return;
> > -		}
> > +		struct drm_crtc *crtc =
> > +			dp_to_dig_port(intel_dp)->base.base.crtc;

I'm afraid that the issue is this pointer here. So this will only mask
the issue.

Should we maybe stash the pipe? :/

> > +		enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > +
> > +		reg = VLV_PSRSTAT(pipe);
> > +		mask = VLV_EDP_PSR_IN_TRANS;
> >  	}
> > +
> > +	mutex_unlock(&dev_priv->psr.lock);
> > +
> > +	err = intel_wait_for_register(dev_priv, reg, mask, 0, 50);
> > +	if (err)
> > +		DRM_ERROR("Timed out waiting for PSR Idle for re-
> > enable\n");
> > +
> > +	/* After the unlocked wait, verify that PSR is still wanted!
> > */
> >  	mutex_lock(&dev_priv->psr.lock);
> > -	intel_dp = dev_priv->psr.enabled;
> > +	return err == 0 && dev_priv->psr.enabled;
> > +}
> >  
> > -	if (!intel_dp)
> > +static void intel_psr_work(struct work_struct *work)
> > +{
> > +	struct drm_i915_private *dev_priv =
> > +		container_of(work, typeof(*dev_priv),
> > psr.work.work);
> > +
> > +	mutex_lock(&dev_priv->psr.lock);
> > +
> > +	/*
> > +	 * We have to make sure PSR is ready for re-enable
> > +	 * otherwise it keeps disabled until next full
> > enable/disable cycle.
> > +	 * PSR might take some time to get fully disabled
> > +	 * and be ready for re-enable.
> > +	 */
> > +	if (!psr_wait_for_idle(dev_priv))
> >  		goto unlock;
> >  
> >  	/*
> > @@ -832,7 +838,7 @@ static void intel_psr_work(struct work_struct
> > *work)
> >  	if (dev_priv->psr.busy_frontbuffer_bits)
> >  		goto unlock;
> >  
> > -	intel_psr_activate(intel_dp);
> > +	intel_psr_activate(dev_priv->psr.enabled);
> >  unlock:
> >  	mutex_unlock(&dev_priv->psr.lock);
> >  }

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-06 22:18     ` [Intel-gfx] " Rodrigo Vivi
  (?)
@ 2018-04-07  9:05     ` Chris Wilson
  2018-04-09 19:14         ` [Intel-gfx] " Rodrigo Vivi
  -1 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2018-04-07  9:05 UTC (permalink / raw)
  To: Rodrigo Vivi, Souza, Jose
  Cc: intel-gfx@lists.freedesktop.org, R, Durgadoss,
	stable@vger.kernel.org

Quoting Rodrigo Vivi (2018-04-06 23:18:16)
> On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > > +           struct drm_crtc *crtc =
> > > +                   dp_to_dig_port(intel_dp)->base.base.crtc;
> 
> I'm afraid that the issue is this pointer here. So this will only mask
> the issue.
> 
> Should we maybe stash the pipe? :/

It's not that bad. pipe cannot change until after psr_disable is called,
right? And psr_disable ensures that this worker is flushed. The current
problem is just the coordination of cancelling the worker, where we may
set psr.enabled to NULL right before the worker grabs it and
dereferences it.

So if we lock until we have the pipe, we know that dereference chain is
valid, and we know that psr_disable() cannot complete until we complete
the wait. So the pipe remains valid until we return (so long as the pipe
exists when we start).
-Chris

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-07  9:05     ` Chris Wilson
@ 2018-04-09 19:14         ` Rodrigo Vivi
  0 siblings, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2018-04-09 19:14 UTC (permalink / raw)
  To: Chris Wilson
  Cc: intel-gfx@lists.freedesktop.org, R, Durgadoss,
	stable@vger.kernel.org

On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-04-06 23:18:16)
> > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > > > +           struct drm_crtc *crtc =
> > > > +                   dp_to_dig_port(intel_dp)->base.base.crtc;
> > 
> > I'm afraid that the issue is this pointer here. So this will only mask
> > the issue.
> > 
> > Should we maybe stash the pipe? :/
> 
> It's not that bad. pipe cannot change until after psr_disable is called,
> right? And psr_disable ensures that this worker is flushed. The current
> problem is just the coordination of cancelling the worker, where we may
> set psr.enabled to NULL right before the worker grabs it and
> dereferences it.
> 
> So if we lock until we have the pipe, we know that dereference chain is
> valid, and we know that psr_disable() cannot complete until we complete
> the wait. So the pipe remains valid until we return (so long as the pipe
> exists when we start).

hmm... it makes sense and I have no better suggestion actually.
So, as long it really fixes the regression we introduced:

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
@ 2018-04-09 19:14         ` Rodrigo Vivi
  0 siblings, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2018-04-09 19:14 UTC (permalink / raw)
  To: Chris Wilson
  Cc: Souza, Jose, intel-gfx@lists.freedesktop.org, R, Durgadoss,
	stable@vger.kernel.org

On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-04-06 23:18:16)
> > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > > > +           struct drm_crtc *crtc =
> > > > +                   dp_to_dig_port(intel_dp)->base.base.crtc;
> > 
> > I'm afraid that the issue is this pointer here. So this will only mask
> > the issue.
> > 
> > Should we maybe stash the pipe? :/
> 
> It's not that bad. pipe cannot change until after psr_disable is called,
> right? And psr_disable ensures that this worker is flushed. The current
> problem is just the coordination of cancelling the worker, where we may
> set psr.enabled to NULL right before the worker grabs it and
> dereferences it.
> 
> So if we lock until we have the pipe, we know that dereference chain is
> valid, and we know that psr_disable() cannot complete until we complete
> the wait. So the pipe remains valid until we return (so long as the pipe
> exists when we start).

hmm... it makes sense and I have no better suggestion actually.
So, as long it really fixes the regression we introduced:

Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-06 18:12 ` [Intel-gfx] [PATCH] " Souza, Jose
  2018-04-06 22:18     ` [Intel-gfx] " Rodrigo Vivi
@ 2018-04-10 10:30   ` Chris Wilson
  1 sibling, 0 replies; 13+ messages in thread
From: Chris Wilson @ 2018-04-10 10:30 UTC (permalink / raw)
  To: Souza, Jose, intel-gfx@lists.freedesktop.org
  Cc: Vivi, Rodrigo, R, Durgadoss, stable@vger.kernel.org

Quoting Souza, Jose (2018-04-06 19:12:27)
> On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > Inside the psr work function, we want to wait for PSR to idle first
> > and
> > wish to do so without blocking the normal modeset path, so we do so
> > without holding the PSR lock. However, we first have to find which
> > pipe
> > PSR was enabled on, which requires chasing into the PSR struct and
> > requires locking to prevent intel_psr_disable() from concurrently
> > setting our pointer to NULL.
> > 
> > Fixes: 995d30477496 ("drm/i915: VLV/CHV PSR Software timer mode")
> > Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> > Cc: Durgadoss R <durgadoss.r@intel.com>
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Cc: <stable@vger.kernel.org> # v4.0+
> 
> Feel free to add:
> Reviewed-by: Jose Roberto de Souza <jose.souza@intel.com>
> 
> > ---
> >  drivers/gpu/drm/i915/intel_psr.c | 82 +++++++++++++++++++++---------
> > ----------
> >  1 file changed, 44 insertions(+), 38 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/intel_psr.c
> > b/drivers/gpu/drm/i915/intel_psr.c
> > index 2d53f7398a6d..69a5b276f4d8 100644
> > --- a/drivers/gpu/drm/i915/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/intel_psr.c
> > @@ -775,53 +775,59 @@ void intel_psr_disable(struct intel_dp
> > *intel_dp,
> >       cancel_delayed_work_sync(&dev_priv->psr.work);
> >  }
> >  
> > -static void intel_psr_work(struct work_struct *work)
> > +static bool psr_wait_for_idle(struct drm_i915_private *dev_priv)
> >  {
> > -     struct drm_i915_private *dev_priv =
> > -             container_of(work, typeof(*dev_priv),
> > psr.work.work);
> > -     struct intel_dp *intel_dp = dev_priv->psr.enabled;
> > -     struct drm_crtc *crtc = dp_to_dig_port(intel_dp)-
> > >base.base.crtc;
> > -     enum pipe pipe = to_intel_crtc(crtc)->pipe;
> > +     struct intel_dp *intel_dp;
> 
> nitpick: Why not already set it?
> struct intel_dp *intel_dp = dev_priv->psr.enabled;

I have a very strong personal preference for coupling logic together and
not splitting it up into an early init and later test. It certainly
helps against falling into the trap of using the variable inside the init
block before you test.

> > +     i915_reg_t reg;
> > +     u32 mask;
> > +     int err;
> > +
> > +     intel_dp = dev_priv->psr.enabled;
> > +     if (!intel_dp)
> > +             return false;
> >  
> > -     /* We have to make sure PSR is ready for re-enable
> > -      * otherwise it keeps disabled until next full
> > enable/disable cycle.
> > -      * PSR might take some time to get fully disabled
> > -      * and be ready for re-enable.
> > -      */
> >       if (HAS_DDI(dev_priv)) {
> 
> 
> nitpick: While on that you could replace this for:
> 
> if (!(IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))) {

That I leave to others ;) Though I would suggest making the branch
around the
	VLV_PSRSTAT(pipe)
explicit as that is only applicable to a subset, and easier to extend as
we typically end up with
	if (GEN >= 10) {
	} else if (bxt_special_case_1) {
	} else if (GEN >= 8) {
	} else if (vlv_or_chv_special_case_2) {
	} else if (GEN >= 6) {
	} else {
		MISSING_CASE();
	}
or whatever is required.
-Chris

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-09 19:14         ` [Intel-gfx] " Rodrigo Vivi
  (?)
@ 2018-04-10 11:00         ` Chris Wilson
  2018-04-10 18:02           ` [Intel-gfx] " Rodrigo Vivi
  -1 siblings, 1 reply; 13+ messages in thread
From: Chris Wilson @ 2018-04-10 11:00 UTC (permalink / raw)
  To: Rodrigo Vivi
  Cc: intel-gfx@lists.freedesktop.org, R, Durgadoss,
	stable@vger.kernel.org

Quoting Rodrigo Vivi (2018-04-09 20:14:32)
> On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote:
> > Quoting Rodrigo Vivi (2018-04-06 23:18:16)
> > > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> > > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > > > > +           struct drm_crtc *crtc =
> > > > > +                   dp_to_dig_port(intel_dp)->base.base.crtc;
> > > 
> > > I'm afraid that the issue is this pointer here. So this will only mask
> > > the issue.
> > > 
> > > Should we maybe stash the pipe? :/
> > 
> > It's not that bad. pipe cannot change until after psr_disable is called,
> > right? And psr_disable ensures that this worker is flushed. The current
> > problem is just the coordination of cancelling the worker, where we may
> > set psr.enabled to NULL right before the worker grabs it and
> > dereferences it.
> > 
> > So if we lock until we have the pipe, we know that dereference chain is
> > valid, and we know that psr_disable() cannot complete until we complete
> > the wait. So the pipe remains valid until we return (so long as the pipe
> > exists when we start).
> 
> hmm... it makes sense and I have no better suggestion actually.
> So, as long it really fixes the regression we introduced:
> 
> Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>

It does fix the abstract race, but I have no evidence of this being hit
in practice. Pushed, but up to you if you care about this being
backported.

Note this race is different from the GPF CI reported. Hmm, I think
https://bugs.freedesktop.org/show_bug.cgi?id=105959 is the same one as
hit on the kasan run earlier.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread

* Re: [Intel-gfx] [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock
  2018-04-10 11:00         ` Chris Wilson
@ 2018-04-10 18:02           ` Rodrigo Vivi
  0 siblings, 0 replies; 13+ messages in thread
From: Rodrigo Vivi @ 2018-04-10 18:02 UTC (permalink / raw)
  To: Chris Wilson
  Cc: intel-gfx@lists.freedesktop.org, R, Durgadoss,
	stable@vger.kernel.org

On Tue, Apr 10, 2018 at 12:00:26PM +0100, Chris Wilson wrote:
> Quoting Rodrigo Vivi (2018-04-09 20:14:32)
> > On Sat, Apr 07, 2018 at 10:05:25AM +0100, Chris Wilson wrote:
> > > Quoting Rodrigo Vivi (2018-04-06 23:18:16)
> > > > On Fri, Apr 06, 2018 at 11:12:27AM -0700, Souza, Jose wrote:
> > > > > On Thu, 2018-04-05 at 12:49 +0100, Chris Wilson wrote:
> > > > > > +           struct drm_crtc *crtc =
> > > > > > +                   dp_to_dig_port(intel_dp)->base.base.crtc;
> > > > 
> > > > I'm afraid that the issue is this pointer here. So this will only mask
> > > > the issue.
> > > > 
> > > > Should we maybe stash the pipe? :/
> > > 
> > > It's not that bad. pipe cannot change until after psr_disable is called,
> > > right? And psr_disable ensures that this worker is flushed. The current
> > > problem is just the coordination of cancelling the worker, where we may
> > > set psr.enabled to NULL right before the worker grabs it and
> > > dereferences it.
> > > 
> > > So if we lock until we have the pipe, we know that dereference chain is
> > > valid, and we know that psr_disable() cannot complete until we complete
> > > the wait. So the pipe remains valid until we return (so long as the pipe
> > > exists when we start).
> > 
> > hmm... it makes sense and I have no better suggestion actually.
> > So, as long it really fixes the regression we introduced:
> > 
> > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> 
> It does fix the abstract race, but I have no evidence of this being hit
> in practice. Pushed, but up to you if you care about this being
> backported.
> 
> Note this race is different from the GPF CI reported. Hmm, I think
> https://bugs.freedesktop.org/show_bug.cgi?id=105959 is the same one as
> hit on the kasan run earlier.

Ouch, thanks for the clarification... I was really considering that this
was the case... but I should have noticed that there was no bugzilla
referenced here...

> -Chris
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 13+ messages in thread

end of thread, other threads:[~2018-04-10 18:02 UTC | newest]

Thread overview: 13+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-04-05 11:49 [PATCH] drm/i915/psr: Chase psr.enabled only under the psr.lock Chris Wilson
2018-04-05 12:25 ` ✗ Fi.CI.BAT: failure for " Patchwork
2018-04-05 13:06 ` ✓ Fi.CI.BAT: success " Patchwork
2018-04-05 14:54 ` ✓ Fi.CI.IGT: " Patchwork
2018-04-06 18:12 ` [Intel-gfx] [PATCH] " Souza, Jose
2018-04-06 22:18   ` Rodrigo Vivi
2018-04-06 22:18     ` [Intel-gfx] " Rodrigo Vivi
2018-04-07  9:05     ` Chris Wilson
2018-04-09 19:14       ` Rodrigo Vivi
2018-04-09 19:14         ` [Intel-gfx] " Rodrigo Vivi
2018-04-10 11:00         ` Chris Wilson
2018-04-10 18:02           ` [Intel-gfx] " Rodrigo Vivi
2018-04-10 10:30   ` Chris Wilson

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