From: joro@8bytes.org (joro at 8bytes.org)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 2/2] x86/mm: implement free pmd/pte page interfaces
Date: Thu, 26 Apr 2018 22:07:37 +0200 [thread overview]
Message-ID: <20180426200737.GS15462@8bytes.org> (raw)
In-Reply-To: <1524764948.2693.478.camel@hpe.com>
On Thu, Apr 26, 2018 at 05:49:58PM +0000, Kani, Toshi wrote:
> On Thu, 2018-04-26 at 19:23 +0200, joro at 8bytes.org wrote:
> > So the PMD entry you clear can still be in a page-walk cache and this
> > needs to be flushed too before you can free the PTE page. Otherwise
> > page-walks might still go to the page you just freed. That is especially
> > bad when the page is already reallocated and filled with other data.
>
> I do not understand why we need to flush processor caches here. x86
> processor caches are coherent with MESI. So, clearing an PMD entry
> modifies a cache entry on the processor associated with the address,
> which in turn invalidates all stale cache entries on other processors.
A page walk cache is not about the processors data cache, its a cache
similar to the TLB to speed up page-walks by caching intermediate
results of previous page walks.
Thanks,
Joerg
WARNING: multiple messages have this Message-ID (diff)
From: "joro@8bytes.org" <joro@8bytes.org>
To: "Kani, Toshi" <toshi.kani@hpe.com>
Cc: "linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"bp@suse.de" <bp@suse.de>,
"tglx@linutronix.de" <tglx@linutronix.de>,
"linux-mm@kvack.org" <linux-mm@kvack.org>,
"guohanjun@huawei.com" <guohanjun@huawei.com>,
"wxf.wang@hisilicon.com" <wxf.wang@hisilicon.com>,
"stable@vger.kernel.org" <stable@vger.kernel.org>,
"x86@kernel.org" <x86@kernel.org>,
"akpm@linux-foundation.org" <akpm@linux-foundation.org>,
"willy@infradead.org" <willy@infradead.org>,
"hpa@zytor.com" <hpa@zytor.com>,
"catalin.marinas@arm.com" <catalin.marinas@arm.com>,
"mingo@redhat.com" <mingo@redhat.com>,
"will.deacon@arm.com" <will.deacon@arm.com>,
"Hocko, Michal" <MHocko@suse.com>,
"cpandya@codeaurora.org" <cpandya@codeaurora.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH v2 2/2] x86/mm: implement free pmd/pte page interfaces
Date: Thu, 26 Apr 2018 22:07:37 +0200 [thread overview]
Message-ID: <20180426200737.GS15462@8bytes.org> (raw)
In-Reply-To: <1524764948.2693.478.camel@hpe.com>
On Thu, Apr 26, 2018 at 05:49:58PM +0000, Kani, Toshi wrote:
> On Thu, 2018-04-26 at 19:23 +0200, joro@8bytes.org wrote:
> > So the PMD entry you clear can still be in a page-walk cache and this
> > needs to be flushed too before you can free the PTE page. Otherwise
> > page-walks might still go to the page you just freed. That is especially
> > bad when the page is already reallocated and filled with other data.
>
> I do not understand why we need to flush processor caches here. x86
> processor caches are coherent with MESI. So, clearing an PMD entry
> modifies a cache entry on the processor associated with the address,
> which in turn invalidates all stale cache entries on other processors.
A page walk cache is not about the processors data cache, its a cache
similar to the TLB to speed up page-walks by caching intermediate
results of previous page walks.
Thanks,
Joerg
next prev parent reply other threads:[~2018-04-26 20:07 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-03-14 18:01 [PATCH v2 0/2] fix memory leak / panic in ioremap huge pages Toshi Kani
2018-03-14 18:01 ` Toshi Kani
2018-03-14 18:01 ` [PATCH v2 1/2] mm/vmalloc: Add interfaces to free unmapped page table Toshi Kani
2018-03-14 18:01 ` Toshi Kani
2018-03-14 22:38 ` Andrew Morton
2018-03-14 22:38 ` Andrew Morton
2018-03-15 14:27 ` Kani, Toshi
2018-03-15 14:27 ` Kani, Toshi
2018-03-14 18:01 ` [PATCH v2 2/2] x86/mm: implement free pmd/pte page interfaces Toshi Kani
2018-03-14 18:01 ` Toshi Kani
2018-03-15 7:39 ` Chintan Pandya
2018-03-15 7:39 ` Chintan Pandya
2018-03-15 14:51 ` Kani, Toshi
2018-03-15 14:51 ` Kani, Toshi
2018-04-26 14:19 ` Joerg Roedel
2018-04-26 14:19 ` Joerg Roedel
2018-04-26 16:21 ` Kani, Toshi
2018-04-26 16:21 ` Kani, Toshi
2018-04-26 17:23 ` joro at 8bytes.org
2018-04-26 17:23 ` joro
2018-04-26 17:49 ` Kani, Toshi
2018-04-26 17:49 ` Kani, Toshi
2018-04-26 20:07 ` joro at 8bytes.org [this message]
2018-04-26 20:07 ` joro
2018-04-26 22:30 ` Kani, Toshi
2018-04-26 22:30 ` Kani, Toshi
2018-04-27 7:37 ` joro at 8bytes.org
2018-04-27 7:37 ` joro
2018-04-27 11:39 ` Michal Hocko
2018-04-27 11:39 ` Michal Hocko
2018-04-27 11:46 ` joro at 8bytes.org
2018-04-27 11:46 ` joro
2018-04-27 11:52 ` Chintan Pandya
2018-04-27 11:52 ` Chintan Pandya
2018-04-27 12:48 ` joro at 8bytes.org
2018-04-27 12:48 ` joro
2018-04-27 13:42 ` Chintan Pandya
2018-04-27 13:42 ` Chintan Pandya
2018-04-27 14:31 ` Kani, Toshi
2018-04-27 14:31 ` Kani, Toshi
2018-04-28 9:02 ` joro at 8bytes.org
2018-04-28 9:02 ` joro
2018-04-28 20:54 ` Kani, Toshi
2018-04-28 20:54 ` Kani, Toshi
2018-04-30 7:30 ` Chintan Pandya
2018-04-30 7:30 ` Chintan Pandya
2018-04-30 13:43 ` Kani, Toshi
2018-04-30 13:43 ` Kani, Toshi
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