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From: Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [patch V7 13/15] SBB 13
Date: Sun, 29 Apr 2018 22:36:27 -0400	[thread overview]
Message-ID: <20180430023627.GD30984@char.us.oracle.com> (raw)
In-Reply-To: <20180429193938.557096663@linutronix.de>

[-- Attachment #1: Type: text/plain, Size: 469 bytes --]

> PR_SET_SPECULATION_CTRL has these additional return values:
> 
> -ERANGE: arg3 is incorrect, i.e. it's not either PR_SPEC_ENABLE or PR_SPEC_DISABLE

s/not either/neither/

? Feel free to ignore it of course but it read more obvious to me that way.

And also attaching the testing program I spoke off. My previous testing (which
I alluded to in previous emails) missed the obvious case of 'r < 0' meaning
0xfffffff.. which would report that all bits are set (duh).




[-- Attachment #2: test-prctl.c --]
[-- Type: text/plain, Size: 2145 bytes --]

#include <stdio.h>
       #include <sys/prctl.h>

#define SPEC_CTRL_RDS_SHIFT            2          /* Reduced Data Speculation bit */
/* Per task speculation control */
#define PR_SET_SPECULATION_CTRL                52
#define PR_GET_SPECULATION_CTRL                53
/* Speculation control variants */
# define PR_SPEC_STORE_BYPASS          0
/* Return and control values for PR_SET/GET_SPECULATION_CTRL */
# define PR_SPEC_NOT_AFFECTED          0
# define PR_SPEC_PRCTL                 (1UL << 0)
# define PR_SPEC_ENABLE                        (1UL << 1)
# define PR_SPEC_DISABLE               (1UL << 2)

void print_bitfields(int r)
{
 if ( r >= 0 )
 	fprintf(stderr, "	r=%s %s %s\n", r & PR_SPEC_PRCTL ? "PR_SPEC_PRCTL" : "",
		r & PR_SPEC_ENABLE ? "PR_SPEC_ENABLE" : "",
		r & PR_SPEC_DISABLE ? "PR_SPEC_DISABLE" : "");

}
void get_v(void)
{
 int r;
 r = prctl(PR_GET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS);
 fprintf(stderr, "   PR_GET_SPECULATION_CTRL PR_SPEC_STORE_BYPASS r=%d\n", r);
 print_bitfields(r);

}

int main(void)
{
 int r;

 fprintf(stderr,"Initial state\n"); 
 get_v();

 r = prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_DISABLE);
 fprintf(stderr, "PR_SET_SPECULATION_CTRL PR_SPEC_DISABLE r=%d\n", r);
 print_bitfields(r);
 get_v();

 /* Two DISALBE in a row*/
 r = prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_DISABLE);
 fprintf(stderr, "PR_SET_SPECULATION_CTRL PR_SPEC_DISABLE r=%d\n", r);
 print_bitfields(r);
 get_v();

 /* Two enable in a row. */
 r = prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_ENABLE);
 fprintf(stderr, "PR_SET_SPECULATION_CTRL PR_SPEC_ENABLE r=%d\n", r);
 print_bitfields(r);
 get_v();

 r = prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_ENABLE);
 fprintf(stderr, "PR_SET_SPECULATION_CTRL PR_SPEC_ENABLE r=%d\n", r);
 print_bitfields(r);
 get_v();
 fprintf(stderr,"\nReal test-case\n");
 /* The real normal test-case */
 r = prctl(PR_SET_SPECULATION_CTRL, PR_SPEC_STORE_BYPASS, PR_SPEC_DISABLE);
 fprintf(stderr, "PR_SET_SPECULATION_CTRL PR_SPEC_DISABLE r=%d\n", r);
 print_bitfields(r);
 get_v();

 do { } while (1);
 
	return 0;
}

  parent reply	other threads:[~2018-04-30  2:36 UTC|newest]

Thread overview: 50+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-04-29 19:30 [patch V7 00/15] SBB 0 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 01/15] SBB 1 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 02/15] SBB 2 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 03/15] SBB 3 Thomas Gleixner
2018-04-29 23:31   ` [MODERATED] " Linus Torvalds
2018-04-30  2:50     ` Konrad Rzeszutek Wilk
2018-04-30  7:09     ` David Woodhouse
2018-04-29 19:30 ` [patch V7 04/15] SBB 4 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 05/15] SBB 5 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 06/15] SBB 6 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 07/15] SBB 7 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 08/15] SBB 8 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 09/15] SBB 9 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 10/15] SBB 10 Thomas Gleixner
2018-04-30  0:16   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30  7:49     ` Thomas Gleixner
2018-04-29 19:30 ` [patch V7 11/15] SBB 11 Thomas Gleixner
2018-04-29 19:30 ` [patch V7 12/15] SBB 12 Thomas Gleixner
2018-04-30  1:33   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-29 19:30 ` [patch V7 13/15] SBB 13 Thomas Gleixner
2018-04-30  1:48   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30  2:39     ` Konrad Rzeszutek Wilk
2018-04-30  3:17     ` Jon Masters
2018-04-30  8:35       ` Thomas Gleixner
2018-04-30  2:20   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30  2:36   ` Konrad Rzeszutek Wilk [this message]
2018-04-30 17:28   ` Konrad Rzeszutek Wilk
2018-04-29 19:30 ` [patch V7 14/15] SBB 14 Thomas Gleixner
2018-04-30  2:14   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30  5:57     ` Thomas Gleixner
2018-04-30 15:49       ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-29 19:31 ` [patch V7 15/15] SBB 15 Thomas Gleixner
2018-04-30  2:32   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-30 15:56   ` Konrad Rzeszutek Wilk
2018-04-30 16:07     ` Thomas Gleixner
2018-04-30 19:30   ` [MODERATED] " Tim Chen
2018-04-30 19:36     ` Thomas Gleixner
2018-04-30 20:12       ` [MODERATED] " Tim Chen
2018-04-30 20:20         ` Konrad Rzeszutek Wilk
2018-04-30 20:44           ` Tim Chen
2018-04-30 20:28         ` Thomas Gleixner
2018-04-30 20:09     ` [MODERATED] " Konrad Rzeszutek Wilk
2018-04-29 20:14 ` [patch V7 00/15] SBB 0 Thomas Gleixner
2018-04-29 20:35 ` [MODERATED] " Borislav Petkov
2018-04-29 20:46   ` Konrad Rzeszutek Wilk
2018-04-29 20:57     ` Thomas Gleixner
2018-04-29 21:40     ` [MODERATED] " Borislav Petkov
2018-04-29 20:55   ` Thomas Gleixner
2018-04-29 22:05     ` Thomas Gleixner
2018-04-30  0:06       ` [MODERATED] " Jon Masters

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