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From: Andi Kleen <ak@linux.intel.com>
To: speck@linutronix.de
Subject: [MODERATED] Re: [patch V11 05/16] SSB 5
Date: Fri, 11 May 2018 09:11:35 -0700	[thread overview]
Message-ID: <20180511161135.GM13616@tassilo.jf.intel.com> (raw)
In-Reply-To: <20180510235056.GA27882@char.us.oracle.com>

On Thu, May 10, 2018 at 07:50:56PM -0400, speck for Konrad Rzeszutek Wilk wrote:
> On Thu, May 10, 2018 at 03:25:33PM -0700, speck for Andi Kleen wrote:
> > > It is actually slower. I tried doing it last time with the spectre/meltdown
> > > and the performance was way slower than doing it this way. I can dig up the patches
> > >  - as I think we did the tests on Broadwell but hadn't tried Skylake or such
> > > (or maybe it was the other way around).
> > 
> > Was this with MSR lists unconditionally, or with MSR list combined with 
> > the "wait for the first write" approach?
> 
> It was the unconditional. The patch went through a bunch of iterations and this

My suspicion is that a combination of the two would be best:

first wait for the first intercept
	so no overhead for the case of the guest not using IBRS at all
then use the msr save/restore list
	this is the most efficient way to do save/restore

With the new "rare MSR use" we may end up with SSB on Linux it may also be worth
to time out the save/restore and go back to intercept, so if SSB is only used temporarily
for a short time the exits wouldn't be slower forever just because
someone used it temporarily.

> It won't apply to 'master' as this was against our heavily backported 4.1 kernel
> but you get the idea. Also ignore some of the commit description as we did
> eventually figure out the 'very fragile' case.

Right that's unconditional.

So the "never use MSR" case is definitely slower, which is likely what you saw.

-Andi

  reply	other threads:[~2018-05-11 16:11 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-05-02 21:51 [patch V11 00/16] SSB 0 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 01/16] SSB 1 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 02/16] SSB 2 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 03/16] SSB 3 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 04/16] SSB 4 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 05/16] SSB 5 Thomas Gleixner
2018-05-10 17:52   ` [MODERATED] " Andi Kleen
2018-05-10 18:30     ` Konrad Rzeszutek Wilk
2018-05-10 19:08       ` Andi Kleen
2018-05-10 21:22         ` Konrad Rzeszutek Wilk
2018-05-10 22:25           ` Andi Kleen
2018-05-10 23:50             ` Konrad Rzeszutek Wilk
2018-05-11 16:11               ` Andi Kleen [this message]
2018-05-16  7:55               ` Paolo Bonzini
2018-05-16 13:52                 ` Konrad Rzeszutek Wilk
2018-05-02 21:51 ` [patch V11 06/16] SSB 6 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 07/16] SSB 7 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 08/16] SSB 8 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 09/16] SSB 9 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 10/16] SSB 10 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 11/16] SSB 11 Thomas Gleixner
2018-05-04 20:58   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-02 21:51 ` [patch V11 12/16] SSB 12 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 13/16] SSB 13 Thomas Gleixner
2018-05-02 21:51 ` [patch V11 14/16] SSB 14 Thomas Gleixner
2018-05-03  7:19   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-03  7:31     ` Thomas Gleixner
2018-05-03  7:22   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-02 21:51 ` [patch V11 15/16] SSB 15 Thomas Gleixner
2018-05-03  7:21   ` [MODERATED] " Konrad Rzeszutek Wilk
2018-05-02 21:51 ` [patch V11 16/16] SSB 16 Thomas Gleixner
2018-05-02 23:21 ` [patch V11 00/16] SSB 0 Thomas Gleixner
2018-05-03  4:27 ` [MODERATED] Encrypted Message Tim Chen
2018-05-03  6:10   ` [MODERATED] Re: [patch V11 00/16] SSB 0 Ingo Molnar
2018-05-03  6:30   ` Thomas Gleixner

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