From: Eduardo Habkost <ehabkost@redhat.com>
To: "Moger, Babu" <Babu.Moger@amd.com>
Cc: "geoff@hostfission.com" <geoff@hostfission.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"mst@redhat.com" <mst@redhat.com>,
"kash@tripleback.net" <kash@tripleback.net>,
"mtosatti@redhat.com" <mtosatti@redhat.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"rth@twiddle.net" <rth@twiddle.net>
Subject: Re: [PATCH v8 3/8] i386: Add new property to control cache info
Date: Fri, 11 May 2018 17:47:59 -0300 [thread overview]
Message-ID: <20180511204759.GP13350@localhost.localdomain> (raw)
In-Reply-To: <BL0PR12MB24682473432EF64021381FAB959F0@BL0PR12MB2468.namprd12.prod.outlook.com>
On Fri, May 11, 2018 at 08:21:50PM +0000, Moger, Babu wrote:
>
> > -----Original Message-----
> > From: Eduardo Habkost [mailto:ehabkost@redhat.com]
> > Sent: Friday, May 11, 2018 2:22 PM
> > To: Moger, Babu <Babu.Moger@amd.com>
> > Cc: mst@redhat.com; marcel.apfelbaum@gmail.com; pbonzini@redhat.com;
> > rth@twiddle.net; mtosatti@redhat.com; qemu-devel@nongnu.org;
> > kvm@vger.kernel.org; geoff@hostfission.com; kash@tripleback.net
> > Subject: Re: [PATCH v8 3/8] i386: Add new property to control cache info
> >
> > On Thu, May 10, 2018 at 03:41:43PM -0500, Babu Moger wrote:
> > > The property legacy-cache will be used to control the cache information.
> > > If user passes "-cpu legacy-cache" then older information will
> > > be displayed even if the hardware supports new information. Otherwise
> > > use the statically loaded cache definitions if available.
> > >
> > > Signed-off-by: Babu Moger <babu.moger@amd.com>
> > > Tested-by: Geoffrey McRae <geoff@hostfission.com>
> > > ---
> > > include/hw/i386/pc.h | 8 ++++
> > > target/i386/cpu.c | 97 ++++++++++++++++++++++++++++++++-----------
> > -
> > > target/i386/cpu.h | 5 +++
> > > 3 files changed, 84 insertions(+), 26 deletions(-)
> > >
> > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> > > index 2e834e6ded..df15deefca 100644
> > > --- a/include/hw/i386/pc.h
> > > +++ b/include/hw/i386/pc.h
> > > @@ -304,6 +304,14 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
> > > int e820_get_num_entries(void);
> > > bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
> > >
> > > +#define PC_COMPAT_2_12 \
> > > + HW_COMPAT_2_12 \
> > > + {\
> > > + .driver = TYPE_X86_CPU,\
> > > + .property = "legacy-cache",\
> > > + .value = "on",\
> > > + },
> >
> > This isn't enough if the pc-*-2.12 machine-type isn't using the
> > macro.
> >
> > Before we do this, we need a commit similar to commit
> > df47ce8af4a5, but adding pc-*-2.13 machine-types.
>
> Ok. Sure. I think I got it. Will add pc-*-2.13 machine-types in v9 series.
Thanks. If you submit v9, please use the x86-next tree as base
so you don't need to resubmit the patches that I have already
queued. See MAINTAINERS for the git URL.
--
Eduardo
WARNING: multiple messages have this Message-ID (diff)
From: Eduardo Habkost <ehabkost@redhat.com>
To: "Moger, Babu" <Babu.Moger@amd.com>
Cc: "geoff@hostfission.com" <geoff@hostfission.com>,
"kvm@vger.kernel.org" <kvm@vger.kernel.org>,
"mst@redhat.com" <mst@redhat.com>,
"kash@tripleback.net" <kash@tripleback.net>,
"mtosatti@redhat.com" <mtosatti@redhat.com>,
"qemu-devel@nongnu.org" <qemu-devel@nongnu.org>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"rth@twiddle.net" <rth@twiddle.net>
Subject: Re: [Qemu-devel] [PATCH v8 3/8] i386: Add new property to control cache info
Date: Fri, 11 May 2018 17:47:59 -0300 [thread overview]
Message-ID: <20180511204759.GP13350@localhost.localdomain> (raw)
In-Reply-To: <BL0PR12MB24682473432EF64021381FAB959F0@BL0PR12MB2468.namprd12.prod.outlook.com>
On Fri, May 11, 2018 at 08:21:50PM +0000, Moger, Babu wrote:
>
> > -----Original Message-----
> > From: Eduardo Habkost [mailto:ehabkost@redhat.com]
> > Sent: Friday, May 11, 2018 2:22 PM
> > To: Moger, Babu <Babu.Moger@amd.com>
> > Cc: mst@redhat.com; marcel.apfelbaum@gmail.com; pbonzini@redhat.com;
> > rth@twiddle.net; mtosatti@redhat.com; qemu-devel@nongnu.org;
> > kvm@vger.kernel.org; geoff@hostfission.com; kash@tripleback.net
> > Subject: Re: [PATCH v8 3/8] i386: Add new property to control cache info
> >
> > On Thu, May 10, 2018 at 03:41:43PM -0500, Babu Moger wrote:
> > > The property legacy-cache will be used to control the cache information.
> > > If user passes "-cpu legacy-cache" then older information will
> > > be displayed even if the hardware supports new information. Otherwise
> > > use the statically loaded cache definitions if available.
> > >
> > > Signed-off-by: Babu Moger <babu.moger@amd.com>
> > > Tested-by: Geoffrey McRae <geoff@hostfission.com>
> > > ---
> > > include/hw/i386/pc.h | 8 ++++
> > > target/i386/cpu.c | 97 ++++++++++++++++++++++++++++++++-----------
> > -
> > > target/i386/cpu.h | 5 +++
> > > 3 files changed, 84 insertions(+), 26 deletions(-)
> > >
> > > diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h
> > > index 2e834e6ded..df15deefca 100644
> > > --- a/include/hw/i386/pc.h
> > > +++ b/include/hw/i386/pc.h
> > > @@ -304,6 +304,14 @@ int e820_add_entry(uint64_t, uint64_t, uint32_t);
> > > int e820_get_num_entries(void);
> > > bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
> > >
> > > +#define PC_COMPAT_2_12 \
> > > + HW_COMPAT_2_12 \
> > > + {\
> > > + .driver = TYPE_X86_CPU,\
> > > + .property = "legacy-cache",\
> > > + .value = "on",\
> > > + },
> >
> > This isn't enough if the pc-*-2.12 machine-type isn't using the
> > macro.
> >
> > Before we do this, we need a commit similar to commit
> > df47ce8af4a5, but adding pc-*-2.13 machine-types.
>
> Ok. Sure. I think I got it. Will add pc-*-2.13 machine-types in v9 series.
Thanks. If you submit v9, please use the x86-next tree as base
so you don't need to resubmit the patches that I have already
queued. See MAINTAINERS for the git URL.
--
Eduardo
next prev parent reply other threads:[~2018-05-11 20:47 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-10 20:41 [PATCH v8 0/8] i386: Enable TOPOEXT to support hyperthreading on AMD CPU Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
2018-05-10 20:41 ` [PATCH v8 1/8] i386: Helpers to encode cache information consistently Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
2018-05-11 19:12 ` Eduardo Habkost
2018-05-11 19:12 ` [Qemu-devel] " Eduardo Habkost
2018-07-16 13:20 ` Philippe Mathieu-Daudé
2018-07-16 19:52 ` Eduardo Habkost
2018-07-17 15:42 ` Philippe Mathieu-Daudé
2018-05-10 20:41 ` [PATCH v8 2/8] i386: Add cache information in X86CPUDefinition Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
2018-05-10 20:41 ` [PATCH v8 3/8] i386: Add new property to control cache info Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
2018-05-11 19:21 ` Eduardo Habkost
2018-05-11 19:21 ` [Qemu-devel] " Eduardo Habkost
2018-05-11 20:21 ` Moger, Babu
2018-05-11 20:21 ` [Qemu-devel] " Moger, Babu
2018-05-11 20:40 ` Eduardo Habkost
2018-05-11 20:40 ` [Qemu-devel] " Eduardo Habkost
2018-05-11 20:47 ` Eduardo Habkost [this message]
2018-05-11 20:47 ` Eduardo Habkost
2018-05-14 16:44 ` Moger, Babu
2018-05-14 16:44 ` [Qemu-devel] " Moger, Babu
2018-05-10 20:41 ` [PATCH v8 4/8] i386: Initialize cache information for EPYC family processors Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
2018-05-10 20:41 ` [PATCH v8 5/8] i386: Populate AMD Processor Cache Information for cpuid 0x8000001D Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
2018-05-10 20:41 ` [PATCH v8 6/8] i386: Add support for CPUID_8000_001E for AMD Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
2018-05-10 20:41 ` [PATCH v8 7/8] i386: Enable TOPOEXT feature on AMD EPYC CPU Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
2018-05-11 20:46 ` Eduardo Habkost
2018-05-11 20:46 ` [Qemu-devel] " Eduardo Habkost
2018-05-11 22:16 ` Moger, Babu
2018-05-11 22:16 ` [Qemu-devel] " Moger, Babu
2018-05-10 20:41 ` [PATCH v8 8/8] i386: Remove generic SMT thread check Babu Moger
2018-05-10 20:41 ` [Qemu-devel] " Babu Moger
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