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From: Boris Brezillon <boris.brezillon@bootlin.com>
To: Tudor Ambarus <tudor.ambarus@microchip.com>
Cc: Peter Rosin <peda@axentia.se>,
	Nicolas Ferre <nicolas.ferre@microchip.com>,
	Ludovic Desroches <ludovic.desroches@microchip.com>,
	Alexandre Belloni <alexandre.belloni@bootlin.com>,
	Marek Vasut <marek.vasut@gmail.com>,
	Josh Wu <rainyfeeling@outlook.com>,
	Cyrille Pitchen <cyrille.pitchen@wedev4u.fr>,
	<linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
	Richard Weinberger <richard@nod.at>,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>,
	<linux-arm-kernel@lists.infradead.org>
Subject: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma
Date: Mon, 4 Jun 2018 18:03:31 +0200	[thread overview]
Message-ID: <20180604180331.67299cc3@bbrezillon> (raw)
In-Reply-To: <28c58ca3-d8ca-7195-3aa2-10d7c703dd65@microchip.com>

On Mon, 4 Jun 2018 18:46:56 +0300
Tudor Ambarus <tudor.ambarus@microchip.com> wrote:

> Hi, Peter,
> 
> On 05/28/2018 01:10 PM, Peter Rosin wrote:
> 
> [cut]
> 
> > So, I think I want either
> > 
> > A) the NAND controller to use master 1 DMAC0/IF0 (i.e. slave 8 DDR2 port 2) and
> >     the LCDC to use master 9 (i.e. slave 9 DDR2 Port 3)
> > 
> > or
> > 
> > B) the NAND controller to use master 2 DMAC0/IF1 (i.e. slave 7 DDR2 port 1, and
> >     possibly slave 9 DDR2 port 3 (if my previous findings are relevant) and the
> >     LCDC to use master 8 (i.e. slave 8 DDR2 Port 2)  
> 
> My understanding is that "Table 14-3. Master to Slave Access" describes
> what connections are allowed between the masters and slaves, while the
> PRxSy registers just set the priorities. What happens when you assign
> the highest priority to a master to slave connection that is not
> allowed? Probably it is ignored, but I'll check with the hardware team.
> So I expect that the NAND controller can not use DDR2 port 3 regardless
> of the priority set.
> 
> [cut]
> 
> > So, output is as expected and I believe that the patch makes the NAND DMA
> > accesses use master 2 DMAC0/IF1 and are thus forced to use slave 7 DDR2 Port 1
> > (and possibly 9). The LCDC is using slave 8 DDR2 Port 2. So there should be no
> > slave conflict?
> > 
> > But the on-screen crap remains during NAND accesses.  
> 
> No conflict, but you missed to dispatch the load on the LCDC DMA
> masters, if I understood correctly.
> 
> So, I think we want to test the following:
> - NAND controller to use DMAC0/IF1 (slave 7 DDR2 port 1)

As I explained in one of my previous email, it's not that easy to set
up, because the SRAM is connected to IF0, and we're using DMA memcpy
here. Also, I don't see how it could solve Peter's problem if, even
when he switches to LCDC master 9 for the primary overlay, he still
keeps experiencing FIFO underruns.

> - LCDC to use master 8 (slave 8 DDR2 Port 2) and master 9 (slave 9 DDR2
> Port 3).

Except that only works if you have several overlays activated, which
AFAIR, is not the case in Peter's setup.

WARNING: multiple messages have this Message-ID (diff)
From: boris.brezillon@bootlin.com (Boris Brezillon)
To: linux-arm-kernel@lists.infradead.org
Subject: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma
Date: Mon, 4 Jun 2018 18:03:31 +0200	[thread overview]
Message-ID: <20180604180331.67299cc3@bbrezillon> (raw)
In-Reply-To: <28c58ca3-d8ca-7195-3aa2-10d7c703dd65@microchip.com>

On Mon, 4 Jun 2018 18:46:56 +0300
Tudor Ambarus <tudor.ambarus@microchip.com> wrote:

> Hi, Peter,
> 
> On 05/28/2018 01:10 PM, Peter Rosin wrote:
> 
> [cut]
> 
> > So, I think I want either
> > 
> > A) the NAND controller to use master 1 DMAC0/IF0 (i.e. slave 8 DDR2 port 2) and
> >     the LCDC to use master 9 (i.e. slave 9 DDR2 Port 3)
> > 
> > or
> > 
> > B) the NAND controller to use master 2 DMAC0/IF1 (i.e. slave 7 DDR2 port 1, and
> >     possibly slave 9 DDR2 port 3 (if my previous findings are relevant) and the
> >     LCDC to use master 8 (i.e. slave 8 DDR2 Port 2)  
> 
> My understanding is that "Table 14-3. Master to Slave Access" describes
> what connections are allowed between the masters and slaves, while the
> PRxSy registers just set the priorities. What happens when you assign
> the highest priority to a master to slave connection that is not
> allowed? Probably it is ignored, but I'll check with the hardware team.
> So I expect that the NAND controller can not use DDR2 port 3 regardless
> of the priority set.
> 
> [cut]
> 
> > So, output is as expected and I believe that the patch makes the NAND DMA
> > accesses use master 2 DMAC0/IF1 and are thus forced to use slave 7 DDR2 Port 1
> > (and possibly 9). The LCDC is using slave 8 DDR2 Port 2. So there should be no
> > slave conflict?
> > 
> > But the on-screen crap remains during NAND accesses.  
> 
> No conflict, but you missed to dispatch the load on the LCDC DMA
> masters, if I understood correctly.
> 
> So, I think we want to test the following:
> - NAND controller to use DMAC0/IF1 (slave 7 DDR2 port 1)

As I explained in one of my previous email, it's not that easy to set
up, because the SRAM is connected to IF0, and we're using DMA memcpy
here. Also, I don't see how it could solve Peter's problem if, even
when he switches to LCDC master 9 for the primary overlay, he still
keeps experiencing FIFO underruns.

> - LCDC to use master 8 (slave 8 DDR2 Port 2) and master 9 (slave 9 DDR2
> Port 3).

Except that only works if you have several overlays activated, which
AFAIR, is not the case in Peter's setup.

  reply	other threads:[~2018-06-04 16:03 UTC|newest]

Thread overview: 117+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-03-29 13:10 [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Peter Rosin
2018-03-29 13:10 ` Peter Rosin
2018-03-29 13:33 ` Boris Brezillon
2018-03-29 13:33   ` Boris Brezillon
2018-03-29 13:37   ` Peter Rosin
2018-03-29 13:37     ` Peter Rosin
2018-03-29 13:44     ` Boris Brezillon
2018-03-29 13:44       ` Boris Brezillon
2018-03-29 14:27       ` Peter Rosin
2018-03-29 14:27         ` Peter Rosin
2018-03-30 21:43         ` Peter Rosin
2018-03-30 21:43           ` Peter Rosin
2018-04-02 12:22         ` Boris Brezillon
2018-04-02 12:22           ` Boris Brezillon
2018-04-02 17:59           ` Peter Rosin
2018-04-02 17:59             ` Peter Rosin
2018-04-02 19:28             ` Boris Brezillon
2018-04-02 19:28               ` Boris Brezillon
2018-04-02 20:20               ` Boris Brezillon
2018-04-02 20:20                 ` Boris Brezillon
2018-04-02 20:32                 ` Boris Brezillon
2018-04-02 20:32                   ` Boris Brezillon
2018-04-03  6:11                 ` Peter Rosin
2018-04-03  6:11                   ` Peter Rosin
2018-04-03  7:18                   ` Boris Brezillon
2018-04-03  7:18                     ` Boris Brezillon
2018-04-11 14:44                     ` Peter Rosin
2018-04-11 14:44                       ` Peter Rosin
2018-04-11 14:59                       ` Boris Brezillon
2018-04-11 14:59                         ` Boris Brezillon
2018-04-11 15:10                         ` Peter Rosin
2018-04-11 15:10                           ` Peter Rosin
2018-04-11 15:34                           ` Boris Brezillon
2018-04-11 15:34                             ` Boris Brezillon
2018-04-11 15:34                       ` Nicolas Ferre
2018-04-11 15:34                         ` Nicolas Ferre
2018-04-12  7:18                         ` Peter Rosin
2018-04-12  7:18                           ` Peter Rosin
2018-05-22 18:03                         ` Peter Rosin
2018-05-22 18:03                           ` Peter Rosin
2018-05-23 10:42                           ` Boris Brezillon
2018-05-23 10:42                             ` Boris Brezillon
2018-05-25 14:51                         ` Tudor Ambarus
2018-05-25 14:51                           ` Tudor Ambarus
2018-05-26 17:40                           ` Peter Rosin
2018-05-26 17:40                             ` Peter Rosin
2018-05-27  9:18                           ` Peter Rosin
2018-05-27  9:18                             ` Peter Rosin
2018-05-27 22:11                             ` Peter Rosin
2018-05-27 22:11                               ` Peter Rosin
2018-05-28 10:10                               ` Peter Rosin
2018-05-28 10:10                                 ` Peter Rosin
2018-05-28 14:27                                 ` Boris Brezillon
2018-05-28 14:27                                   ` Boris Brezillon
2018-05-28 15:52                                   ` Peter Rosin
2018-05-28 15:52                                     ` Peter Rosin
2018-05-28 16:09                                     ` Boris Brezillon
2018-05-28 16:09                                       ` Boris Brezillon
2018-05-28 16:09                                     ` Nicolas Ferre
2018-05-28 16:09                                       ` Nicolas Ferre
2018-05-29  6:30                                 ` Eugen Hristev
2018-05-29  6:30                                   ` Eugen Hristev
2018-05-29  7:10                                   ` Peter Rosin
2018-05-29  7:10                                     ` Peter Rosin
2018-05-29  7:25                                     ` Eugen Hristev
2018-05-29  7:25                                       ` Eugen Hristev
2018-05-29 14:49                                   ` Boris Brezillon
2018-05-29 14:49                                     ` Boris Brezillon
2018-05-29 15:01                                     ` Eugen Hristev
2018-05-29 15:01                                       ` Eugen Hristev
2018-05-29 15:15                                       ` Boris Brezillon
2018-05-29 15:15                                         ` Boris Brezillon
2018-05-29 15:21                                         ` Eugen Hristev
2018-05-29 15:21                                           ` Eugen Hristev
2018-05-29 15:46                                           ` Boris Brezillon
2018-05-29 15:46                                             ` Boris Brezillon
2018-05-29 17:57                                             ` Boris Brezillon
2018-05-29 17:57                                               ` Boris Brezillon
2018-05-29 21:37                                               ` Peter Rosin
2018-05-29 21:37                                                 ` Peter Rosin
2018-06-04 15:46                                 ` Tudor Ambarus
2018-06-04 15:46                                   ` Tudor Ambarus
2018-06-04 16:03                                   ` Boris Brezillon [this message]
2018-06-04 16:03                                     ` Boris Brezillon
2022-06-16 15:54                           ` SAMA5D3 Display FIFO underflow (Was: Re: [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma) Ahmad Fatoum
2022-07-25 14:17                             ` Ahmad Fatoum
2022-07-28  8:03                               ` Tudor.Ambarus
2018-04-03  6:51                 ` [PATCH] mtd: nand: raw: atmel: add module param to avoid using dma Peter Rosin
2018-04-03  6:51                   ` Peter Rosin
2018-04-03  7:15                   ` Boris Brezillon
2018-04-03  7:15                     ` Boris Brezillon
2018-04-03  7:32                     ` Boris Brezillon
2018-04-03  7:32                       ` Boris Brezillon
2018-04-03  8:14                     ` Peter Rosin
2018-04-03  8:14                       ` Peter Rosin
2018-04-03  8:30                       ` Boris Brezillon
2018-04-03  8:30                         ` Boris Brezillon
2018-04-02 20:23               ` Peter Rosin
2018-04-02 20:23                 ` Peter Rosin
2018-04-02 20:35                 ` Boris Brezillon
2018-04-02 20:35                   ` Boris Brezillon
2018-04-03  7:18                 ` Alexandre Belloni
2018-04-03  7:18                   ` Alexandre Belloni
2018-04-03  8:37                   ` Peter Rosin
2018-04-03  8:37                     ` Peter Rosin
2018-03-29 14:20 ` Nicolas Ferre
2018-03-29 14:20   ` Nicolas Ferre
2018-03-29 14:23   ` Peter Rosin
2018-03-29 14:23     ` Peter Rosin
2018-03-29 14:29   ` Boris Brezillon
2018-03-29 14:29     ` Boris Brezillon
2018-06-18  8:39 ` Boris Brezillon
2018-06-18  8:39   ` Boris Brezillon
2018-06-18 14:00   ` Miquel Raynal
2018-06-18 14:00     ` Miquel Raynal
2018-06-25 12:31   ` Miquel Raynal
2018-06-25 12:31     ` Miquel Raynal

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