From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Stefan Agner <stefan@agner.ch>
Cc: boris.brezillon@bootlin.com, dwmw2@infradead.org,
computersforpeace@gmail.com, marek.vasut@gmail.com,
robh+dt@kernel.org, mark.rutland@arm.com,
thierry.reding@gmail.com, mturquette@baylibre.com,
sboyd@kernel.org, dev@lynxeye.de, richard@nod.at,
marcel@ziswiler.com, krzk@kernel.org, digetx@gmail.com,
benjamin.lindqvist@endian.se, jonathanh@nvidia.com,
pdeschrijver@nvidia.com, pgaikwad@nvidia.com,
mirza.krak@gmail.com, linux-mtd@lists.infradead.org,
linux-tegra@vger.kernel.org
Subject: Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
Date: Thu, 7 Jun 2018 11:58:48 +0200 [thread overview]
Message-ID: <20180607115848.5ef08680@xps13> (raw)
In-Reply-To: <80eb6a514e96cdbd460c6a0937a9dff9@agner.ch>
Hi Stefan,
On Thu, 31 May 2018 11:37:41 +0200, Stefan Agner <stefan@agner.ch>
wrote:
> On 27.05.2018 23:54, Stefan Agner wrote:
> > Add support for the NAND flash controller found on NVIDIA
> > Tegra 2 SoCs. This implementation does not make use of the
> > command queue feature. Regular operations/data transfers are
> > done in PIO mode. Page read/writes with hardware ECC make
> > use of the DMA for data transfer.
> >
> > Signed-off-by: Lucas Stach <dev@lynxeye.de>
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > ---
> > MAINTAINERS | 7 +
> > drivers/mtd/nand/raw/Kconfig | 6 +
> > drivers/mtd/nand/raw/Makefile | 1 +
> > drivers/mtd/nand/raw/tegra_nand.c | 999 ++++++++++++++++++++++++++++++
> > 4 files changed, 1013 insertions(+)
> > create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
> >
> [...]
> > +
> > + chip->ecc.read_page = tegra_nand_read_page_hwecc;
> > + chip->ecc.write_page = tegra_nand_write_page_hwecc;
> > + /* Not functional for unknown reason...
> > + chip->ecc.read_page_raw = tegra_nand_read_page;
> > + chip->ecc.write_page_raw = tegra_nand_write_page;
> > + */
>
> I am giving up on these raw read/write_page functions. Using DMA without
> HW ECC just seems not to work.
[...]
> Note that the default implementations nand_(read|write)_page_raw which
> use exec_op do work fine! Unfortunately, the PIO mode only allows 4
> bytes in a read cycle, hence raw read/write is slow...
>
Well, if raw accessors work in PIO mode, I suppose it's not a big deal.
Thanks for trying anyway!
Miquèl
WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Stefan Agner <stefan@agner.ch>
Cc: mark.rutland@arm.com, pgaikwad@nvidia.com, dev@lynxeye.de,
marek.vasut@gmail.com, sboyd@kernel.org, richard@nod.at,
mturquette@baylibre.com, mirza.krak@gmail.com, krzk@kernel.org,
jonathanh@nvidia.com, boris.brezillon@bootlin.com,
robh+dt@kernel.org, thierry.reding@gmail.com,
marcel@ziswiler.com, benjamin.lindqvist@endian.se,
linux-tegra@vger.kernel.org, linux-mtd@lists.infradead.org,
digetx@gmail.com, computersforpeace@gmail.com,
dwmw2@infradead.org, pdeschrijver@nvidia.com
Subject: Re: [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver
Date: Thu, 7 Jun 2018 11:58:48 +0200 [thread overview]
Message-ID: <20180607115848.5ef08680@xps13> (raw)
In-Reply-To: <80eb6a514e96cdbd460c6a0937a9dff9@agner.ch>
Hi Stefan,
On Thu, 31 May 2018 11:37:41 +0200, Stefan Agner <stefan@agner.ch>
wrote:
> On 27.05.2018 23:54, Stefan Agner wrote:
> > Add support for the NAND flash controller found on NVIDIA
> > Tegra 2 SoCs. This implementation does not make use of the
> > command queue feature. Regular operations/data transfers are
> > done in PIO mode. Page read/writes with hardware ECC make
> > use of the DMA for data transfer.
> >
> > Signed-off-by: Lucas Stach <dev@lynxeye.de>
> > Signed-off-by: Stefan Agner <stefan@agner.ch>
> > ---
> > MAINTAINERS | 7 +
> > drivers/mtd/nand/raw/Kconfig | 6 +
> > drivers/mtd/nand/raw/Makefile | 1 +
> > drivers/mtd/nand/raw/tegra_nand.c | 999 ++++++++++++++++++++++++++++++
> > 4 files changed, 1013 insertions(+)
> > create mode 100644 drivers/mtd/nand/raw/tegra_nand.c
> >
> [...]
> > +
> > + chip->ecc.read_page = tegra_nand_read_page_hwecc;
> > + chip->ecc.write_page = tegra_nand_write_page_hwecc;
> > + /* Not functional for unknown reason...
> > + chip->ecc.read_page_raw = tegra_nand_read_page;
> > + chip->ecc.write_page_raw = tegra_nand_write_page;
> > + */
>
> I am giving up on these raw read/write_page functions. Using DMA without
> HW ECC just seems not to work.
[...]
> Note that the default implementations nand_(read|write)_page_raw which
> use exec_op do work fine! Unfortunately, the PIO mode only allows 4
> bytes in a read cycle, hence raw read/write is slow...
>
Well, if raw accessors work in PIO mode, I suppose it's not a big deal.
Thanks for trying anyway!
Miquèl
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Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
next prev parent reply other threads:[~2018-06-07 9:59 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-05-27 21:54 [PATCH v2 3/6] mtd: rawnand: add NVIDIA Tegra NAND Flash controller driver Stefan Agner
2018-05-27 22:19 ` Miquel Raynal
2018-05-28 12:41 ` Stefan Agner
2018-05-28 11:57 ` Dmitry Osipenko
2018-05-28 11:57 ` Dmitry Osipenko
2018-05-28 12:43 ` Stefan Agner
2018-05-28 16:41 ` Benjamin Lindqvist
2018-05-28 16:41 ` Benjamin Lindqvist
2018-05-28 16:57 ` Boris Brezillon
2018-05-31 9:37 ` Stefan Agner
2018-05-31 9:55 ` Stefan Agner
2018-06-07 9:58 ` Miquel Raynal [this message]
2018-06-07 9:58 ` Miquel Raynal
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