[MODERATED] Re: [PATCH 2/2] L1TF KVM v2 2

[Konrad Rzeszutek Wilk <konrad.wilk@oracle.com>]

On Wed, Jun 20, 2018 at 10:25:45PM +0200, speck for Jiri Kosina wrote:
> On Wed, 20 Jun 2018, speck for Paolo Bonzini wrote:
> 
> > diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
> > index 578793e97431..aebf89c4175d 100644
> > --- a/arch/x86/include/asm/cpufeatures.h
> > +++ b/arch/x86/include/asm/cpufeatures.h
> > @@ -333,6 +333,7 @@
> >  #define X86_FEATURE_PCONFIG		(18*32+18) /* Intel PCONFIG */
> >  #define X86_FEATURE_SPEC_CTRL		(18*32+26) /* "" Speculation Control (IBRS + IBPB) */
> >  #define X86_FEATURE_INTEL_STIBP		(18*32+27) /* "" Single Thread Indirect Branch Predictors */
> > +#define X86_FEATURE_FLUSH_L1D		(18*32+28) /* IA32_FLUSH_L1D MSR */
> >  #define X86_FEATURE_ARCH_CAPABILITIES	(18*32+29) /* IA32_ARCH_CAPABILITIES MSR (Intel) */
> >  
> >  /*
> > diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
> > index 53d5b1b9255e..f43bd9f23053 100644
> > --- a/arch/x86/include/asm/msr-index.h
> > +++ b/arch/x86/include/asm/msr-index.h
> > @@ -65,6 +65,9 @@
> >  
> >  #define MSR_MTRRcap			0x000000fe
> >  
> > +#define MSR_IA32_FLUSH_L1D             0x10b
> > +#define MSR_IA32_FLUSH_L1D_VALUE       0x00000001
> > +
> >  #define MSR_IA32_ARCH_CAPABILITIES	0x0000010a
> >  #define ARCH_CAP_RDCL_NO		(1 << 0)   /* Not susceptible to Meltdown */
> >  #define ARCH_CAP_IBRS_ALL		(1 << 1)   /* Enhanced IBRS support */
> > diff --git a/arch/x86/kvm/x86.c b/arch/x86/kvm/x86.c
> > index 8bf8f672cece..c88ed554bb66 100644
> > --- a/arch/x86/kvm/x86.c
> > +++ b/arch/x86/kvm/x86.c
> > @@ -6551,8 +6551,15 @@ static int pvclock_gtod_notify(struct notifier_block *nb, unsigned long unused,
> >  
> >  void kvm_l1d_flush(void)
> >  {
> > +	int size;
> > +
> > +	if (static_cpu_has(X86_FEATURE_FLUSH_L1D)) {
> 
> Umm, where exactly do you set this feature bit?

CPUID.7 array ends up being set  automatically in cpu/common.c.

> 
> Thanks,
> 
> -- 
> Jiri Kosina
> SUSE Labs