* [PATCH libdrm 1/2] intel: Introducing Whiskey Lake platform
@ 2018-06-19 23:45 José Roberto de Souza
2018-06-19 23:45 ` [PATCH libdrm 2/2] intel: Introducing Amber " José Roberto de Souza
2018-06-20 23:29 ` [PATCH libdrm 1/2] intel: Introducing Whiskey " Rodrigo Vivi
0 siblings, 2 replies; 5+ messages in thread
From: José Roberto de Souza @ 2018-06-19 23:45 UTC (permalink / raw)
To: dri-devel; +Cc: José Roberto de Souza, Rodrigo Vivi
Whiskey Lake uses the same gen graphics as Coffe Lake, including some
ids that were previously marked as reserved on Coffe Lake, but that
now are moved to WHL page.
So, let's just move them to WHL macros that will feed into CFL macro
just to keep it better organized to make easier future code review
but it will be handled as a CFL.
This is a copy of merged i915's
commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
intel/intel_chipset.h | 33 +++++++++++++++++----------------
1 file changed, 17 insertions(+), 16 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 32b2c48f..44e65f9e 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -231,16 +231,17 @@
#define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
#define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
#define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
-#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1
-#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4
-#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0
-#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3
-#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9
-#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2
-#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5
-#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6
-#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
-#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
+#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9
+#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
+#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
+#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
+#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
+
+#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1
+#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0
+#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2
+#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3
+#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4
#define PCI_CHIP_CANNONLAKE_0 0x5A51
#define PCI_CHIP_CANNONLAKE_1 0x5A59
@@ -510,16 +511,16 @@
#define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
(devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
-#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \
+#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
(devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
(devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
(devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
(devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
- (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5)
+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \
+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \
+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \
+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \
+ (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3)
#define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
IS_CFL_H(devid) || \
--
2.17.1
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^ permalink raw reply related [flat|nested] 5+ messages in thread* [PATCH libdrm 2/2] intel: Introducing Amber Lake platform
2018-06-19 23:45 [PATCH libdrm 1/2] intel: Introducing Whiskey Lake platform José Roberto de Souza
@ 2018-06-19 23:45 ` José Roberto de Souza
2018-06-20 23:31 ` Rodrigo Vivi
2018-06-20 23:29 ` [PATCH libdrm 1/2] intel: Introducing Whiskey " Rodrigo Vivi
1 sibling, 1 reply; 5+ messages in thread
From: José Roberto de Souza @ 2018-06-19 23:45 UTC (permalink / raw)
To: dri-devel; +Cc: José Roberto de Souza, Rodrigo Vivi
Amber Lake uses the same gen graphics as Kaby Lake, including a id
that were previously marked as reserved on Kaby Lake, but that now is
moved to AML page.
So, let's just move it to AML macro that will feed into KBL macro
just to keep it better organized to make easier future code review
but it will be handled as a KBL.
This is a copy of merged i915's
commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")
Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
---
intel/intel_chipset.h | 9 ++++++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
index 44e65f9e..583d6447 100644
--- a/intel/intel_chipset.h
+++ b/intel/intel_chipset.h
@@ -201,7 +201,6 @@
#define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
#define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
#define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E
-#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C
#define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
#define PCI_CHIP_KABYLAKE_M_GT2 0x5917
#define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
@@ -213,6 +212,9 @@
#define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
#define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
+#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C
+#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0
+
#define PCI_CHIP_BROXTON_0 0x0A84
#define PCI_CHIP_BROXTON_1 0x1A84
#define PCI_CHIP_BROXTON_2 0x5A84
@@ -468,12 +470,13 @@
#define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
(devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
(devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \
- (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \
(devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
(devid) == PCI_CHIP_KABYLAKE_M_GT2 || \
(devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
(devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \
- (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
+ (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \
+ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \
+ (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2)
#define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \
(devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \
--
2.17.1
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply related [flat|nested] 5+ messages in thread* Re: [PATCH libdrm 2/2] intel: Introducing Amber Lake platform
2018-06-19 23:45 ` [PATCH libdrm 2/2] intel: Introducing Amber " José Roberto de Souza
@ 2018-06-20 23:31 ` Rodrigo Vivi
2018-06-20 23:42 ` Rodrigo Vivi
0 siblings, 1 reply; 5+ messages in thread
From: Rodrigo Vivi @ 2018-06-20 23:31 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: dri-devel
On Tue, Jun 19, 2018 at 04:45:21PM -0700, José Roberto de Souza wrote:
> Amber Lake uses the same gen graphics as Kaby Lake, including a id
> that were previously marked as reserved on Kaby Lake, but that now is
> moved to AML page.
>
> So, let's just move it to AML macro that will feed into KBL macro
> just to keep it better organized to make easier future code review
> but it will be handled as a KBL.
>
> This is a copy of merged i915's
> commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
I just didn't push yet because I haven't migrated my system to
new gitlab yet. And I wasn't able to login.
I hope that someone else can push these 2 patches for now.
I will try to get my gitlab account working later anyways...
Thanks,
Rodrigo.
> ---
> intel/intel_chipset.h | 9 ++++++---
> 1 file changed, 6 insertions(+), 3 deletions(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 44e65f9e..583d6447 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -201,7 +201,6 @@
> #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
> #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
> #define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E
> -#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C
> #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
> #define PCI_CHIP_KABYLAKE_M_GT2 0x5917
> #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
> @@ -213,6 +212,9 @@
> #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
> #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
>
> +#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C
> +#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0
> +
> #define PCI_CHIP_BROXTON_0 0x0A84
> #define PCI_CHIP_BROXTON_1 0x1A84
> #define PCI_CHIP_BROXTON_2 0x5A84
> @@ -468,12 +470,13 @@
> #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
> (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
> (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \
> - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \
> (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
> (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \
> (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
> (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \
> - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
> + (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \
> + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \
> + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2)
>
> #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \
> (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \
> --
> 2.17.1
>
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH libdrm 2/2] intel: Introducing Amber Lake platform
2018-06-20 23:31 ` Rodrigo Vivi
@ 2018-06-20 23:42 ` Rodrigo Vivi
0 siblings, 0 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2018-06-20 23:42 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: dri-devel
On Wed, Jun 20, 2018 at 04:31:15PM -0700, Rodrigo Vivi wrote:
> On Tue, Jun 19, 2018 at 04:45:21PM -0700, José Roberto de Souza wrote:
> > Amber Lake uses the same gen graphics as Kaby Lake, including a id
> > that were previously marked as reserved on Kaby Lake, but that now is
> > moved to AML page.
> >
> > So, let's just move it to AML macro that will feed into KBL macro
> > just to keep it better organized to make easier future code review
> > but it will be handled as a KBL.
> >
> > This is a copy of merged i915's
> > commit e364672477a1 ("drm/i915/aml: Introducing Amber Lake platform")
> >
> > Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> > Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
>
> Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
>
> I just didn't push yet because I haven't migrated my system to
> new gitlab yet. And I wasn't able to login.
> I hope that someone else can push these 2 patches for now.
> I will try to get my gitlab account working later anyways...
nevermind. the reset pswd email finally arrived on my inbox
so gitlab up and running
patches pushed, thanks.
>
> Thanks,
> Rodrigo.
>
> > ---
> > intel/intel_chipset.h | 9 ++++++---
> > 1 file changed, 6 insertions(+), 3 deletions(-)
> >
> > diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> > index 44e65f9e..583d6447 100644
> > --- a/intel/intel_chipset.h
> > +++ b/intel/intel_chipset.h
> > @@ -201,7 +201,6 @@
> > #define PCI_CHIP_KABYLAKE_ULX_GT1_5 0x5915
> > #define PCI_CHIP_KABYLAKE_ULX_GT1 0x590E
> > #define PCI_CHIP_KABYLAKE_ULX_GT2_0 0x591E
> > -#define PCI_CHIP_KABYLAKE_ULX_GT2_1 0x591C
> > #define PCI_CHIP_KABYLAKE_DT_GT2 0x5912
> > #define PCI_CHIP_KABYLAKE_M_GT2 0x5917
> > #define PCI_CHIP_KABYLAKE_DT_GT1 0x5902
> > @@ -213,6 +212,9 @@
> > #define PCI_CHIP_KABYLAKE_SRV_GT1 0x590A
> > #define PCI_CHIP_KABYLAKE_WKS_GT2 0x591D
> >
> > +#define PCI_CHIP_AMBERLAKE_ULX_GT2_1 0x591C
> > +#define PCI_CHIP_AMBERLAKE_ULX_GT2_2 0x87C0
> > +
> > #define PCI_CHIP_BROXTON_0 0x0A84
> > #define PCI_CHIP_BROXTON_1 0x1A84
> > #define PCI_CHIP_BROXTON_2 0x5A84
> > @@ -468,12 +470,13 @@
> > #define IS_KBL_GT2(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT2 || \
> > (devid) == PCI_CHIP_KABYLAKE_ULT_GT2F || \
> > (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_0 || \
> > - (devid) == PCI_CHIP_KABYLAKE_ULX_GT2_1 || \
> > (devid) == PCI_CHIP_KABYLAKE_DT_GT2 || \
> > (devid) == PCI_CHIP_KABYLAKE_M_GT2 || \
> > (devid) == PCI_CHIP_KABYLAKE_HALO_GT2 || \
> > (devid) == PCI_CHIP_KABYLAKE_SRV_GT2 || \
> > - (devid) == PCI_CHIP_KABYLAKE_WKS_GT2)
> > + (devid) == PCI_CHIP_KABYLAKE_WKS_GT2 || \
> > + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_1 || \
> > + (devid) == PCI_CHIP_AMBERLAKE_ULX_GT2_2)
> >
> > #define IS_KBL_GT3(devid) ((devid) == PCI_CHIP_KABYLAKE_ULT_GT3_0 || \
> > (devid) == PCI_CHIP_KABYLAKE_ULT_GT3_1 || \
> > --
> > 2.17.1
> >
_______________________________________________
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dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH libdrm 1/2] intel: Introducing Whiskey Lake platform
2018-06-19 23:45 [PATCH libdrm 1/2] intel: Introducing Whiskey Lake platform José Roberto de Souza
2018-06-19 23:45 ` [PATCH libdrm 2/2] intel: Introducing Amber " José Roberto de Souza
@ 2018-06-20 23:29 ` Rodrigo Vivi
1 sibling, 0 replies; 5+ messages in thread
From: Rodrigo Vivi @ 2018-06-20 23:29 UTC (permalink / raw)
To: José Roberto de Souza; +Cc: dri-devel
On Tue, Jun 19, 2018 at 04:45:20PM -0700, José Roberto de Souza wrote:
> Whiskey Lake uses the same gen graphics as Coffe Lake, including some
> ids that were previously marked as reserved on Coffe Lake, but that
> now are moved to WHL page.
>
> So, let's just move them to WHL macros that will feed into CFL macro
> just to keep it better organized to make easier future code review
> but it will be handled as a CFL.
>
> This is a copy of merged i915's
> commit b9be78531d27 ("drm/i915/whl: Introducing Whiskey Lake platform")
>
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> ---
> intel/intel_chipset.h | 33 +++++++++++++++++----------------
> 1 file changed, 17 insertions(+), 16 deletions(-)
>
> diff --git a/intel/intel_chipset.h b/intel/intel_chipset.h
> index 32b2c48f..44e65f9e 100644
> --- a/intel/intel_chipset.h
> +++ b/intel/intel_chipset.h
> @@ -231,16 +231,17 @@
> #define PCI_CHIP_COFFEELAKE_S_GT2_4 0x3E9A
> #define PCI_CHIP_COFFEELAKE_H_GT2_1 0x3E9B
> #define PCI_CHIP_COFFEELAKE_H_GT2_2 0x3E94
> -#define PCI_CHIP_COFFEELAKE_U_GT1_1 0x3EA1
> -#define PCI_CHIP_COFFEELAKE_U_GT1_2 0x3EA4
> -#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA0
> -#define PCI_CHIP_COFFEELAKE_U_GT2_2 0x3EA3
> -#define PCI_CHIP_COFFEELAKE_U_GT2_3 0x3EA9
> -#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA2
> -#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA5
> -#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA6
> -#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA7
> -#define PCI_CHIP_COFFEELAKE_U_GT3_5 0x3EA8
> +#define PCI_CHIP_COFFEELAKE_U_GT2_1 0x3EA9
> +#define PCI_CHIP_COFFEELAKE_U_GT3_1 0x3EA5
> +#define PCI_CHIP_COFFEELAKE_U_GT3_2 0x3EA6
> +#define PCI_CHIP_COFFEELAKE_U_GT3_3 0x3EA7
> +#define PCI_CHIP_COFFEELAKE_U_GT3_4 0x3EA8
> +
> +#define PCI_CHIP_WHISKEYLAKE_U_GT1_1 0x3EA1
> +#define PCI_CHIP_WHISKEYLAKE_U_GT2_1 0x3EA0
> +#define PCI_CHIP_WHISKEYLAKE_U_GT3_1 0x3EA2
> +#define PCI_CHIP_WHISKEYLAKE_U_GT3_2 0x3EA3
> +#define PCI_CHIP_WHISKEYLAKE_U_GT3_3 0x3EA4
>
> #define PCI_CHIP_CANNONLAKE_0 0x5A51
> #define PCI_CHIP_CANNONLAKE_1 0x5A59
> @@ -510,16 +511,16 @@
> #define IS_CFL_H(devid) ((devid) == PCI_CHIP_COFFEELAKE_H_GT2_1 || \
> (devid) == PCI_CHIP_COFFEELAKE_H_GT2_2)
>
> -#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT1_1 || \
> - (devid) == PCI_CHIP_COFFEELAKE_U_GT1_2 || \
> - (devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
> - (devid) == PCI_CHIP_COFFEELAKE_U_GT2_2 || \
> - (devid) == PCI_CHIP_COFFEELAKE_U_GT2_3 || \
> +#define IS_CFL_U(devid) ((devid) == PCI_CHIP_COFFEELAKE_U_GT2_1 || \
> (devid) == PCI_CHIP_COFFEELAKE_U_GT3_1 || \
> (devid) == PCI_CHIP_COFFEELAKE_U_GT3_2 || \
> (devid) == PCI_CHIP_COFFEELAKE_U_GT3_3 || \
> (devid) == PCI_CHIP_COFFEELAKE_U_GT3_4 || \
> - (devid) == PCI_CHIP_COFFEELAKE_U_GT3_5)
> + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT1_1 || \
> + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT2_1 || \
> + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_1 || \
> + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_2 || \
> + (devid) == PCI_CHIP_WHISKEYLAKE_U_GT3_3)
>
> #define IS_COFFEELAKE(devid) (IS_CFL_S(devid) || \
> IS_CFL_H(devid) || \
> --
> 2.17.1
>
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^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2018-06-20 23:42 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-06-19 23:45 [PATCH libdrm 1/2] intel: Introducing Whiskey Lake platform José Roberto de Souza
2018-06-19 23:45 ` [PATCH libdrm 2/2] intel: Introducing Amber " José Roberto de Souza
2018-06-20 23:31 ` Rodrigo Vivi
2018-06-20 23:42 ` Rodrigo Vivi
2018-06-20 23:29 ` [PATCH libdrm 1/2] intel: Introducing Whiskey " Rodrigo Vivi
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