From: "Emilio G. Cota" <cota@braap.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: patches@linaro.org, qemu-devel@nongnu.org,
"KONRAD Frederic" <frederic.konrad@adacore.com>,
qemu-arm@nongnu.org, "Cédric Le Goater" <clg@kaod.org>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Richard Henderson" <rth@twiddle.net>
Subject: Re: [Qemu-arm] [PATCH 4/6] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM
Date: Fri, 13 Jul 2018 12:41:21 -0400 [thread overview]
Message-ID: <20180713164121.GA22074@flamenco> (raw)
In-Reply-To: <20180710160013.26559-5-peter.maydell@linaro.org>
On Tue, Jul 10, 2018 at 17:00:11 +0100, Peter Maydell wrote:
> If get_page_addr_code() returns -1, this indicates that there is no RAM
> page we can read a full TB from. Instead we must create a TB which
> contains a single instruction and which we do not cache, so it is
> executed only once.
>
> Since this means we can now have TBs which are not in any page list,
> we also need to make tb_phys_invalidate() handle them (by not trying
> to remove them from a nonexistent page list).
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Emilio
WARNING: multiple messages have this Message-ID (diff)
From: "Emilio G. Cota" <cota@braap.org>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, patches@linaro.org,
"Richard Henderson" <rth@twiddle.net>,
"Paolo Bonzini" <pbonzini@redhat.com>,
"Cédric Le Goater" <clg@kaod.org>,
"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
"KONRAD Frederic" <frederic.konrad@adacore.com>
Subject: Re: [Qemu-devel] [PATCH 4/6] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM
Date: Fri, 13 Jul 2018 12:41:21 -0400 [thread overview]
Message-ID: <20180713164121.GA22074@flamenco> (raw)
In-Reply-To: <20180710160013.26559-5-peter.maydell@linaro.org>
On Tue, Jul 10, 2018 at 17:00:11 +0100, Peter Maydell wrote:
> If get_page_addr_code() returns -1, this indicates that there is no RAM
> page we can read a full TB from. Instead we must create a TB which
> contains a single instruction and which we do not cache, so it is
> executed only once.
>
> Since this means we can now have TBs which are not in any page list,
> we also need to make tb_phys_invalidate() handle them (by not trying
> to remove them from a nonexistent page list).
>
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Emilio G. Cota <cota@braap.org>
Emilio
next prev parent reply other threads:[~2018-07-13 16:41 UTC|newest]
Thread overview: 63+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-10 16:00 [Qemu-arm] [PATCH 0/6] accel/tcg: Support execution from MMIO and small MMU regions Peter Maydell
2018-07-10 16:00 ` [Qemu-devel] " Peter Maydell
2018-07-10 16:00 ` [Qemu-arm] [PATCH 1/6] accel/tcg: Pass read access type through to io_readx() Peter Maydell
2018-07-10 16:00 ` [Qemu-devel] " Peter Maydell
2018-07-10 18:19 ` Richard Henderson
2018-07-10 18:19 ` Richard Henderson
2018-07-11 14:06 ` [Qemu-arm] " Philippe Mathieu-Daudé
2018-07-11 14:06 ` [Qemu-devel] " Philippe Mathieu-Daudé
2018-07-10 16:00 ` [Qemu-devel] [PATCH 2/6] accel/tcg: Handle get_page_addr_code() returning -1 in hashtable lookups Peter Maydell
2018-07-10 16:00 ` Peter Maydell
2018-07-10 18:23 ` [Qemu-arm] " Richard Henderson
2018-07-10 18:23 ` [Qemu-devel] " Richard Henderson
2018-07-13 16:44 ` [Qemu-arm] " Emilio G. Cota
2018-07-13 16:44 ` [Qemu-devel] " Emilio G. Cota
2018-07-10 16:00 ` [Qemu-arm] [PATCH 3/6] accel/tcg: Handle get_page_addr_code() returning -1 in tb_check_watchpoint() Peter Maydell
2018-07-10 16:00 ` [Qemu-devel] " Peter Maydell
2018-07-10 18:27 ` [Qemu-arm] " Richard Henderson
2018-07-10 18:27 ` [Qemu-devel] " Richard Henderson
2018-07-10 16:00 ` [Qemu-arm] [PATCH 4/6] accel/tcg: tb_gen_code(): Create single-insn TB for execution from non-RAM Peter Maydell
2018-07-10 16:00 ` [Qemu-devel] " Peter Maydell
2018-07-10 18:30 ` [Qemu-arm] " Richard Henderson
2018-07-10 18:30 ` [Qemu-devel] " Richard Henderson
2018-07-13 16:41 ` Emilio G. Cota [this message]
2018-07-13 16:41 ` Emilio G. Cota
2018-07-10 16:00 ` [Qemu-arm] [PATCH 5/6] accel/tcg: Return -1 for execution from MMIO regions in get_page_addr_code() Peter Maydell
2018-07-10 16:00 ` [Qemu-devel] " Peter Maydell
2018-07-10 18:33 ` [Qemu-arm] " Richard Henderson
2018-07-10 18:33 ` [Qemu-devel] " Richard Henderson
2018-07-11 14:36 ` [Qemu-devel] [Qemu-arm] " Philippe Mathieu-Daudé
2018-11-14 17:19 ` [Qemu-arm] [Qemu-devel] " Thomas Huth
2018-11-14 17:19 ` Thomas Huth
2018-11-15 7:32 ` [Qemu-arm] " Richard Henderson
2018-11-15 7:32 ` Richard Henderson
2018-11-15 13:53 ` Peter Maydell
2018-11-15 13:53 ` Peter Maydell
2018-11-15 16:00 ` Richard Henderson
2018-11-15 16:00 ` Richard Henderson
2018-07-10 16:00 ` [Qemu-arm] [PATCH 6/6] target/arm: Allow execution from small regions Peter Maydell
2018-07-10 16:00 ` [Qemu-devel] " Peter Maydell
2018-07-10 18:34 ` [Qemu-arm] " Richard Henderson
2018-07-10 18:34 ` [Qemu-devel] " Richard Henderson
2018-07-11 15:09 ` [Qemu-arm] " Philippe Mathieu-Daudé
2018-07-11 15:09 ` [Qemu-devel] " Philippe Mathieu-Daudé
2018-07-11 4:21 ` [Qemu-arm] [PATCH 0/6] accel/tcg: Support execution from MMIO and small MMU regions Philippe Mathieu-Daudé
2018-07-11 4:21 ` [Qemu-devel] " Philippe Mathieu-Daudé
2018-07-12 16:37 ` Peter Maydell
2018-07-12 16:37 ` Peter Maydell
2018-07-13 15:13 ` Peter Maydell
2018-07-13 15:13 ` [Qemu-devel] " Peter Maydell
2018-07-16 12:30 ` KONRAD Frederic
2018-07-16 12:30 ` [Qemu-devel] " KONRAD Frederic
2018-07-16 13:02 ` Peter Maydell
2018-07-16 13:02 ` Peter Maydell
2018-07-23 14:57 ` [Qemu-arm] " Cédric Le Goater
2018-07-23 14:57 ` [Qemu-devel] " Cédric Le Goater
2018-07-23 15:17 ` Peter Maydell
2018-07-23 15:17 ` Peter Maydell
2018-07-23 15:51 ` [Qemu-arm] " Cédric Le Goater
2018-07-23 15:51 ` [Qemu-devel] " Cédric Le Goater
2018-07-23 15:11 ` [Qemu-arm] " Cédric Le Goater
2018-07-23 15:11 ` [Qemu-devel] " Cédric Le Goater
2018-07-24 12:23 ` [Qemu-arm] " Peter Maydell
2018-07-24 12:23 ` [Qemu-devel] " Peter Maydell
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