* [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
@ 2018-07-13 15:42 Lucas De Marchi
2018-07-13 15:42 ` [PATCH v3 2/2] drm/i915: remove PCH_GMBUS defines Lucas De Marchi
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Lucas De Marchi @ 2018-07-13 15:42 UTC (permalink / raw)
To: intel-gfx; +Cc: daniel.vetter, JaniNikulajani.nikula, Rodrigo Vivi
Instead of defining all registers twice, define just a PCH_GPIO_BASE
that has the same address as PCH_GPIO_A and use that to calculate all
the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
the same thing.
v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
macro to return a particular gpio address and move the enum out of
i915_reg.h (suggested by Jani)
v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
actually need to be changed (suggested by Daniel/Ville)
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
drivers/gpu/drm/i915/i915_drv.h | 3 ++-
drivers/gpu/drm/i915/i915_reg.h | 24 +++++-------------------
drivers/gpu/drm/i915/intel_drv.h | 16 ++++++++++++++++
drivers/gpu/drm/i915/intel_i2c.c | 12 ++++--------
5 files changed, 28 insertions(+), 29 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index 7a58ca555197..ecff866bbbf1 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
gmbus_mmio_write);
- MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
+ MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index b31d48cf7a69..596e734a874f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1611,7 +1611,8 @@ struct drm_i915_private {
struct mutex gmbus_mutex;
/**
- * Base address of the gmbus and gpio block.
+ * Base address of where the gmbus and gpio blocks are located (either
+ * on PCH or on SoC for platforms without PCH).
*/
uint32_t gpio_mmio_base;
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 1f222af0324d..5e3ba9898f4e 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -3089,18 +3089,9 @@ enum i915_power_well_id {
/*
* GPIO regs
*/
-#define GPIOA _MMIO(0x5010)
-#define GPIOB _MMIO(0x5014)
-#define GPIOC _MMIO(0x5018)
-#define GPIOD _MMIO(0x501c)
-#define GPIOE _MMIO(0x5020)
-#define GPIOF _MMIO(0x5024)
-#define GPIOG _MMIO(0x5028)
-#define GPIOH _MMIO(0x502c)
-#define GPIOJ _MMIO(0x5034)
-#define GPIOK _MMIO(0x5038)
-#define GPIOL _MMIO(0x503C)
-#define GPIOM _MMIO(0x5040)
+#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
+ 4 * (gpio))
+
# define GPIO_CLOCK_DIR_MASK (1 << 0)
# define GPIO_CLOCK_DIR_IN (0 << 1)
# define GPIO_CLOCK_DIR_OUT (1 << 1)
@@ -7483,6 +7474,8 @@ enum {
/* PCH */
+#define PCH_DISPLAY_BASE 0xc0000u
+
/* south display engine interrupt: IBX */
#define SDE_AUDIO_POWER_D (1 << 27)
#define SDE_AUDIO_POWER_C (1 << 26)
@@ -7671,13 +7664,6 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define PCH_GPIOA _MMIO(0xc5010)
-#define PCH_GPIOB _MMIO(0xc5014)
-#define PCH_GPIOC _MMIO(0xc5018)
-#define PCH_GPIOD _MMIO(0xc501c)
-#define PCH_GPIOE _MMIO(0xc5020)
-#define PCH_GPIOF _MMIO(0xc5024)
-
#define PCH_GMBUS0 _MMIO(0xc5100)
#define PCH_GMBUS1 _MMIO(0xc5104)
#define PCH_GMBUS2 _MMIO(0xc5108)
diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
index b09b6389a734..2d102f95b38e 100644
--- a/drivers/gpu/drm/i915/intel_drv.h
+++ b/drivers/gpu/drm/i915/intel_drv.h
@@ -152,6 +152,22 @@
* Display related stuff
*/
+enum i915_gpio {
+ GPIOA = 0,
+ GPIOB,
+ GPIOC,
+ GPIOD,
+ GPIOE,
+ GPIOF,
+ GPIOG,
+ GPIOH,
+ __GPIOI_UNUSED,
+ GPIOJ,
+ GPIOK,
+ GPIOL,
+ GPIOM,
+};
+
/* store information about an Ixxx DVO */
/* The i830->i865 use multiple DVOs with multiple i2cs */
/* the i915, i945 have a single sDVO i2c bus - which is different */
diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
index bef32b7c248e..f03c7ca718b5 100644
--- a/drivers/gpu/drm/i915/intel_i2c.c
+++ b/drivers/gpu/drm/i915/intel_i2c.c
@@ -37,7 +37,7 @@
struct gmbus_pin {
const char *name;
- i915_reg_t reg;
+ enum i915_gpio gpio;
};
/* Map gmbus pin pairs to names and registers. */
@@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
else
size = ARRAY_SIZE(gmbus_pins);
- return pin < size &&
- i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
+ return pin < size && get_gmbus_pin(dev_priv, pin)->name;
}
/* Intel GPIO access functions */
@@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
algo = &bus->bit_algo;
- bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
- i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
+ bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
bus->adapter.algo_data = algo;
algo->setsda = set_data;
algo->setscl = set_clock;
@@ -825,9 +823,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
else if (!HAS_GMCH_DISPLAY(dev_priv))
- dev_priv->gpio_mmio_base =
- i915_mmio_reg_offset(PCH_GPIOA) -
- i915_mmio_reg_offset(GPIOA);
+ dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
mutex_init(&dev_priv->gmbus_mutex);
init_waitqueue_head(&dev_priv->gmbus_wait_queue);
--
2.17.1
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v3 2/2] drm/i915: remove PCH_GMBUS defines
2018-07-13 15:42 [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
@ 2018-07-13 15:42 ` Lucas De Marchi
2018-07-13 16:00 ` ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Patchwork
` (2 subsequent siblings)
3 siblings, 0 replies; 9+ messages in thread
From: Lucas De Marchi @ 2018-07-13 15:42 UTC (permalink / raw)
To: intel-gfx; +Cc: daniel.vetter, JaniNikulajani.nikula, Rodrigo Vivi
Use GMBUS* macros which computes the address using the gpio_mmio_base.
For that we just need access to dev_priv in a few places so this has
been added.
Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
---
drivers/gpu/drm/i915/gvt/edid.c | 42 +++++++++++++++++------------
drivers/gpu/drm/i915/gvt/handlers.c | 8 +++---
drivers/gpu/drm/i915/i915_reg.h | 7 -----
3 files changed, 29 insertions(+), 28 deletions(-)
diff --git a/drivers/gpu/drm/i915/gvt/edid.c b/drivers/gpu/drm/i915/gvt/edid.c
index 4b98539025c5..3ffa814a634e 100644
--- a/drivers/gpu/drm/i915/gvt/edid.c
+++ b/drivers/gpu/drm/i915/gvt/edid.c
@@ -109,9 +109,11 @@ static inline int get_port_from_gmbus0(u32 gmbus0)
static void reset_gmbus_controller(struct intel_vgpu *vgpu)
{
- vgpu_vreg_t(vgpu, PCH_GMBUS2) = GMBUS_HW_RDY;
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
+ vgpu_vreg_t(vgpu, GMBUS2) = GMBUS_HW_RDY;
if (!vgpu->display.i2c_edid.edid_available)
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_SATOER;
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
}
@@ -141,22 +143,23 @@ static int gmbus0_mmio_write(struct intel_vgpu *vgpu,
vgpu->display.i2c_edid.state = I2C_GMBUS;
vgpu->display.i2c_edid.gmbus.phase = GMBUS_IDLE_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_HW_RDY | GMBUS_HW_WAIT_PHASE;
if (intel_vgpu_has_monitor_on_port(vgpu, port) &&
!intel_vgpu_port_is_dp(vgpu, port)) {
vgpu->display.i2c_edid.port = port;
vgpu->display.i2c_edid.edid_available = true;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_SATOER;
} else
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_SATOER;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_SATOER;
return 0;
}
static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
u32 slave_addr;
u32 wvalue = *(u32 *)p_data;
@@ -177,8 +180,8 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* 2) HW_RDY bit asserted
*/
if (wvalue & GMBUS_SW_CLR_INT) {
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_INT;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_HW_RDY;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_INT;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_HW_RDY;
}
/* For virtualization, we suppose that HW is always ready,
@@ -226,7 +229,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* visible in gmbus interface)
*/
i2c_edid->gmbus.phase = GMBUS_IDLE_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) &= ~GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) &= ~GMBUS_ACTIVE;
}
break;
case NIDX_NS_W:
@@ -238,7 +241,7 @@ static int gmbus1_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
* START (-->INDEX) -->DATA
*/
i2c_edid->gmbus.phase = GMBUS_DATA_PHASE;
- vgpu_vreg_t(vgpu, PCH_GMBUS2) |= GMBUS_ACTIVE;
+ vgpu_vreg_t(vgpu, GMBUS2) |= GMBUS_ACTIVE;
break;
default:
gvt_vgpu_err("Unknown/reserved GMBUS cycle detected!\n");
@@ -265,6 +268,7 @@ static int gmbus3_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
int i;
unsigned char byte_data;
struct intel_vgpu_i2c_edid *i2c_edid = &vgpu->display.i2c_edid;
@@ -274,7 +278,7 @@ static int gmbus3_mmio_read(struct intel_vgpu *vgpu, unsigned int offset,
u32 reg_data = 0;
/* Data can only be recevied if previous settings correct */
- if (vgpu_vreg_t(vgpu, PCH_GMBUS1) & GMBUS_SLAVE_READ) {
+ if (vgpu_vreg_t(vgpu, GMBUS1) & GMBUS_SLAVE_READ) {
if (byte_left <= 0) {
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
return 0;
@@ -350,12 +354,14 @@ static int gmbus2_mmio_write(struct intel_vgpu *vgpu, unsigned int offset,
int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
- if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
+ if (offset == i915_mmio_reg_offset(GMBUS2))
return gmbus2_mmio_read(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
+ else if (offset == i915_mmio_reg_offset(GMBUS3))
return gmbus3_mmio_read(vgpu, offset, p_data, bytes);
memcpy(p_data, &vgpu_vreg(vgpu, offset), bytes);
@@ -375,16 +381,18 @@ int intel_gvt_i2c_handle_gmbus_read(struct intel_vgpu *vgpu,
int intel_gvt_i2c_handle_gmbus_write(struct intel_vgpu *vgpu,
unsigned int offset, void *p_data, unsigned int bytes)
{
+ struct drm_i915_private *dev_priv = vgpu->gvt->dev_priv;
+
if (WARN_ON(bytes > 8 && (offset & (bytes - 1))))
return -EINVAL;
- if (offset == i915_mmio_reg_offset(PCH_GMBUS0))
+ if (offset == i915_mmio_reg_offset(GMBUS0))
return gmbus0_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS1))
+ else if (offset == i915_mmio_reg_offset(GMBUS1))
return gmbus1_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS2))
+ else if (offset == i915_mmio_reg_offset(GMBUS2))
return gmbus2_mmio_write(vgpu, offset, p_data, bytes);
- else if (offset == i915_mmio_reg_offset(PCH_GMBUS3))
+ else if (offset == i915_mmio_reg_offset(GMBUS3))
return gmbus3_mmio_write(vgpu, offset, p_data, bytes);
memcpy(&vgpu_vreg(vgpu, offset), p_data, bytes);
diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
index ecff866bbbf1..185e6c3002e5 100644
--- a/drivers/gpu/drm/i915/gvt/handlers.c
+++ b/drivers/gpu/drm/i915/gvt/handlers.c
@@ -2116,8 +2116,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(0x48268), D_ALL);
- MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
- gmbus_mmio_write);
+ MMIO_F(GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
+ gmbus_mmio_write);
MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
@@ -2507,8 +2507,8 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
MMIO_D(_MMIO(0xe6704), D_ALL);
MMIO_D(_MMIO(0xe6800), D_ALL);
MMIO_D(_MMIO(0xe6804), D_ALL);
- MMIO_D(PCH_GMBUS4, D_ALL);
- MMIO_D(PCH_GMBUS5, D_ALL);
+ MMIO_D(GMBUS4, D_ALL);
+ MMIO_D(GMBUS5, D_ALL);
MMIO_D(_MMIO(0x902c), D_ALL);
MMIO_D(_MMIO(0xec008), D_ALL);
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 5e3ba9898f4e..e01e98ff8c30 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7664,13 +7664,6 @@ enum {
#define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
#define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
-#define PCH_GMBUS0 _MMIO(0xc5100)
-#define PCH_GMBUS1 _MMIO(0xc5104)
-#define PCH_GMBUS2 _MMIO(0xc5108)
-#define PCH_GMBUS3 _MMIO(0xc510c)
-#define PCH_GMBUS4 _MMIO(0xc5110)
-#define PCH_GMBUS5 _MMIO(0xc5120)
-
#define _PCH_DPLL_A 0xc6014
#define _PCH_DPLL_B 0xc6018
#define PCH_DPLL(pll) _MMIO((pll) == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
--
2.17.1
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 9+ messages in thread
* ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-13 15:42 [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
2018-07-13 15:42 ` [PATCH v3 2/2] drm/i915: remove PCH_GMBUS defines Lucas De Marchi
@ 2018-07-13 16:00 ` Patchwork
2018-07-13 16:07 ` [PATCH v3 1/2] " Ville Syrjälä
2018-07-13 16:16 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-07-13 16:00 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
URL : https://patchwork.freedesktop.org/series/46493/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Commit: drm/i915: remove confusing GPIO vs PCH_GPIO
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3653:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3654:16: warning: expression using sizeof(void)
Commit: drm/i915: remove PCH_GMBUS defines
Okay!
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-13 15:42 [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
2018-07-13 15:42 ` [PATCH v3 2/2] drm/i915: remove PCH_GMBUS defines Lucas De Marchi
2018-07-13 16:00 ` ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Patchwork
@ 2018-07-13 16:07 ` Ville Syrjälä
2018-07-17 22:16 ` Lucas De Marchi
2018-07-13 16:16 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] " Patchwork
3 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2018-07-13 16:07 UTC (permalink / raw)
To: Lucas De Marchi
Cc: daniel.vetter, intel-gfx, JaniNikulajani.nikula, Rodrigo Vivi
On Fri, Jul 13, 2018 at 08:42:11AM -0700, Lucas De Marchi wrote:
> Instead of defining all registers twice, define just a PCH_GPIO_BASE
> that has the same address as PCH_GPIO_A and use that to calculate all
> the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> the same thing.
>
> v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> macro to return a particular gpio address and move the enum out of
> i915_reg.h (suggested by Jani)
>
> v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
> actually need to be changed (suggested by Daniel/Ville)
>
> Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> ---
> drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> drivers/gpu/drm/i915/i915_reg.h | 24 +++++-------------------
> drivers/gpu/drm/i915/intel_drv.h | 16 ++++++++++++++++
> drivers/gpu/drm/i915/intel_i2c.c | 12 ++++--------
> 5 files changed, 28 insertions(+), 29 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> index 7a58ca555197..ecff866bbbf1 100644
> --- a/drivers/gpu/drm/i915/gvt/handlers.c
> +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> @@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
>
> MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> gmbus_mmio_write);
> - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> + MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
I have no idea of gpio_mmio_base is populated correctly at this point
for gvt, and I'm too lazy to find out.
> MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
>
> MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index b31d48cf7a69..596e734a874f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1611,7 +1611,8 @@ struct drm_i915_private {
> struct mutex gmbus_mutex;
>
> /**
> - * Base address of the gmbus and gpio block.
> + * Base address of where the gmbus and gpio blocks are located (either
> + * on PCH or on SoC for platforms without PCH).
> */
> uint32_t gpio_mmio_base;
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 1f222af0324d..5e3ba9898f4e 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -3089,18 +3089,9 @@ enum i915_power_well_id {
> /*
> * GPIO regs
> */
> -#define GPIOA _MMIO(0x5010)
> -#define GPIOB _MMIO(0x5014)
> -#define GPIOC _MMIO(0x5018)
> -#define GPIOD _MMIO(0x501c)
> -#define GPIOE _MMIO(0x5020)
> -#define GPIOF _MMIO(0x5024)
> -#define GPIOG _MMIO(0x5028)
> -#define GPIOH _MMIO(0x502c)
> -#define GPIOJ _MMIO(0x5034)
> -#define GPIOK _MMIO(0x5038)
> -#define GPIOL _MMIO(0x503C)
> -#define GPIOM _MMIO(0x5040)
> +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
> + 4 * (gpio))
> +
> # define GPIO_CLOCK_DIR_MASK (1 << 0)
> # define GPIO_CLOCK_DIR_IN (0 << 1)
> # define GPIO_CLOCK_DIR_OUT (1 << 1)
> @@ -7483,6 +7474,8 @@ enum {
>
> /* PCH */
>
> +#define PCH_DISPLAY_BASE 0xc0000u
> +
> /* south display engine interrupt: IBX */
> #define SDE_AUDIO_POWER_D (1 << 27)
> #define SDE_AUDIO_POWER_C (1 << 26)
> @@ -7671,13 +7664,6 @@ enum {
> #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
>
> -#define PCH_GPIOA _MMIO(0xc5010)
> -#define PCH_GPIOB _MMIO(0xc5014)
> -#define PCH_GPIOC _MMIO(0xc5018)
> -#define PCH_GPIOD _MMIO(0xc501c)
> -#define PCH_GPIOE _MMIO(0xc5020)
> -#define PCH_GPIOF _MMIO(0xc5024)
> -
> #define PCH_GMBUS0 _MMIO(0xc5100)
> #define PCH_GMBUS1 _MMIO(0xc5104)
> #define PCH_GMBUS2 _MMIO(0xc5108)
> diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> index b09b6389a734..2d102f95b38e 100644
> --- a/drivers/gpu/drm/i915/intel_drv.h
> +++ b/drivers/gpu/drm/i915/intel_drv.h
> @@ -152,6 +152,22 @@
> * Display related stuff
> */
>
> +enum i915_gpio {
> + GPIOA = 0,
=0 not really needed
> + GPIOB,
> + GPIOC,
> + GPIOD,
> + GPIOE,
> + GPIOF,
> + GPIOG,
> + GPIOH,
> + __GPIOI_UNUSED,
> + GPIOJ,
> + GPIOK,
> + GPIOL,
> + GPIOM,
> +};
Weren't most things like this moved into intel_display.h a while back?
> +
> /* store information about an Ixxx DVO */
> /* The i830->i865 use multiple DVOs with multiple i2cs */
> /* the i915, i945 have a single sDVO i2c bus - which is different */
> diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> index bef32b7c248e..f03c7ca718b5 100644
> --- a/drivers/gpu/drm/i915/intel_i2c.c
> +++ b/drivers/gpu/drm/i915/intel_i2c.c
> @@ -37,7 +37,7 @@
>
> struct gmbus_pin {
> const char *name;
> - i915_reg_t reg;
> + enum i915_gpio gpio;
> };
>
> /* Map gmbus pin pairs to names and registers. */
> @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> else
> size = ARRAY_SIZE(gmbus_pins);
>
> - return pin < size &&
> - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> + return pin < size && get_gmbus_pin(dev_priv, pin)->name;
> }
>
> /* Intel GPIO access functions */
> @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
>
> algo = &bus->bit_algo;
>
> - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
> bus->adapter.algo_data = algo;
> algo->setsda = set_data;
> algo->setscl = set_clock;
> @@ -825,9 +823,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> else if (!HAS_GMCH_DISPLAY(dev_priv))
I was slightly confused by this until I remeber that BXT uses the PCH
offsets for the south stuff even though it doesn't have a PCH. Might
want to add a comment here to unconfuse matter.
> - dev_priv->gpio_mmio_base =
> - i915_mmio_reg_offset(PCH_GPIOA) -
> - i915_mmio_reg_offset(GPIOA);
> + dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
>
> mutex_init(&dev_priv->gmbus_mutex);
> init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> --
> 2.17.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v3,1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-13 15:42 [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
` (2 preceding siblings ...)
2018-07-13 16:07 ` [PATCH v3 1/2] " Ville Syrjälä
@ 2018-07-13 16:16 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-07-13 16:16 UTC (permalink / raw)
To: Lucas De Marchi; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v3,1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
URL : https://patchwork.freedesktop.org/series/46493/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_4486 -> Patchwork_9648 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/46493/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_9648 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_flip@basic-flip-vs-dpms:
fi-skl-6700hq: PASS -> DMESG-WARN (fdo#105998)
fdo#105998 https://bugs.freedesktop.org/show_bug.cgi?id=105998
== Participating hosts (45 -> 41) ==
Additional (1): fi-bxt-dsi
Missing (5): fi-byt-j1900 fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-hsw-4200u
== Build changes ==
* Linux: CI_DRM_4486 -> Patchwork_9648
CI_DRM_4486: 9c869b6ff78481dd5789d007bbee989129b67af4 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4556: caea9c5b3aa1191c0152d7c0f22a94efca4fd048 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_9648: d17d341a645e4cc229be1df83ddce13ee08c6af3 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
d17d341a645e drm/i915: remove PCH_GMBUS defines
8cf4c4171468 drm/i915: remove confusing GPIO vs PCH_GPIO
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_9648/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-13 16:07 ` [PATCH v3 1/2] " Ville Syrjälä
@ 2018-07-17 22:16 ` Lucas De Marchi
2018-07-18 10:01 ` Ville Syrjälä
0 siblings, 1 reply; 9+ messages in thread
From: Lucas De Marchi @ 2018-07-17 22:16 UTC (permalink / raw)
To: Ville Syrjälä
Cc: Daniel Vetter, intel-gfx, Lucas De Marchi, JaniNikulajani.nikula,
Rodrigo Vivi
On Fri, Jul 13, 2018 at 9:10 AM Ville Syrjälä
<ville.syrjala@linux.intel.com> wrote:
>
> On Fri, Jul 13, 2018 at 08:42:11AM -0700, Lucas De Marchi wrote:
> > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> > that has the same address as PCH_GPIO_A and use that to calculate all
> > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> > the same thing.
> >
> > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> > macro to return a particular gpio address and move the enum out of
> > i915_reg.h (suggested by Jani)
> >
> > v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
> > actually need to be changed (suggested by Daniel/Ville)
> >
> > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > ---
> > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> > drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> > drivers/gpu/drm/i915/i915_reg.h | 24 +++++-------------------
> > drivers/gpu/drm/i915/intel_drv.h | 16 ++++++++++++++++
> > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++--------
> > 5 files changed, 28 insertions(+), 29 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> > index 7a58ca555197..ecff866bbbf1 100644
> > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > @@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> >
> > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> > gmbus_mmio_write);
> > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > + MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
>
> I have no idea of gpio_mmio_base is populated correctly at this point
> for gvt, and I'm too lazy to find out.
humn, unfortunately it is not
i915_driver_load() -> i915_load_modeset_init() -> intel_setup_gmbus()
-> dev_priv->gpio_mmio_base = ...
i915_driver_load() -> i915_driver_init_hw() -> intel_gvt_init() ->
intel_gvt_init_device() -> intel_gvt_setup_mmio_info() ->
init_generic_mmio_info()
Is adding a single PCH_GPIO_BASE that doesn't depend on dev_priv being
populated for use on gvt an option?
Lucas De Marchi
>
> > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> >
> > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > index b31d48cf7a69..596e734a874f 100644
> > --- a/drivers/gpu/drm/i915/i915_drv.h
> > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > @@ -1611,7 +1611,8 @@ struct drm_i915_private {
> > struct mutex gmbus_mutex;
> >
> > /**
> > - * Base address of the gmbus and gpio block.
> > + * Base address of where the gmbus and gpio blocks are located (either
> > + * on PCH or on SoC for platforms without PCH).
> > */
> > uint32_t gpio_mmio_base;
> >
> > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > index 1f222af0324d..5e3ba9898f4e 100644
> > --- a/drivers/gpu/drm/i915/i915_reg.h
> > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > @@ -3089,18 +3089,9 @@ enum i915_power_well_id {
> > /*
> > * GPIO regs
> > */
> > -#define GPIOA _MMIO(0x5010)
> > -#define GPIOB _MMIO(0x5014)
> > -#define GPIOC _MMIO(0x5018)
> > -#define GPIOD _MMIO(0x501c)
> > -#define GPIOE _MMIO(0x5020)
> > -#define GPIOF _MMIO(0x5024)
> > -#define GPIOG _MMIO(0x5028)
> > -#define GPIOH _MMIO(0x502c)
> > -#define GPIOJ _MMIO(0x5034)
> > -#define GPIOK _MMIO(0x5038)
> > -#define GPIOL _MMIO(0x503C)
> > -#define GPIOM _MMIO(0x5040)
> > +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
> > + 4 * (gpio))
> > +
> > # define GPIO_CLOCK_DIR_MASK (1 << 0)
> > # define GPIO_CLOCK_DIR_IN (0 << 1)
> > # define GPIO_CLOCK_DIR_OUT (1 << 1)
> > @@ -7483,6 +7474,8 @@ enum {
> >
> > /* PCH */
> >
> > +#define PCH_DISPLAY_BASE 0xc0000u
> > +
> > /* south display engine interrupt: IBX */
> > #define SDE_AUDIO_POWER_D (1 << 27)
> > #define SDE_AUDIO_POWER_C (1 << 26)
> > @@ -7671,13 +7664,6 @@ enum {
> > #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> > #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
> >
> > -#define PCH_GPIOA _MMIO(0xc5010)
> > -#define PCH_GPIOB _MMIO(0xc5014)
> > -#define PCH_GPIOC _MMIO(0xc5018)
> > -#define PCH_GPIOD _MMIO(0xc501c)
> > -#define PCH_GPIOE _MMIO(0xc5020)
> > -#define PCH_GPIOF _MMIO(0xc5024)
> > -
> > #define PCH_GMBUS0 _MMIO(0xc5100)
> > #define PCH_GMBUS1 _MMIO(0xc5104)
> > #define PCH_GMBUS2 _MMIO(0xc5108)
> > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > index b09b6389a734..2d102f95b38e 100644
> > --- a/drivers/gpu/drm/i915/intel_drv.h
> > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > @@ -152,6 +152,22 @@
> > * Display related stuff
> > */
> >
> > +enum i915_gpio {
> > + GPIOA = 0,
>
> =0 not really needed
>
> > + GPIOB,
> > + GPIOC,
> > + GPIOD,
> > + GPIOE,
> > + GPIOF,
> > + GPIOG,
> > + GPIOH,
> > + __GPIOI_UNUSED,
> > + GPIOJ,
> > + GPIOK,
> > + GPIOL,
> > + GPIOM,
> > +};
>
> Weren't most things like this moved into intel_display.h a while back?
>
> > +
> > /* store information about an Ixxx DVO */
> > /* The i830->i865 use multiple DVOs with multiple i2cs */
> > /* the i915, i945 have a single sDVO i2c bus - which is different */
> > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> > index bef32b7c248e..f03c7ca718b5 100644
> > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > @@ -37,7 +37,7 @@
> >
> > struct gmbus_pin {
> > const char *name;
> > - i915_reg_t reg;
> > + enum i915_gpio gpio;
> > };
> >
> > /* Map gmbus pin pairs to names and registers. */
> > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> > else
> > size = ARRAY_SIZE(gmbus_pins);
> >
> > - return pin < size &&
> > - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> > + return pin < size && get_gmbus_pin(dev_priv, pin)->name;
> > }
> >
> > /* Intel GPIO access functions */
> > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
> >
> > algo = &bus->bit_algo;
> >
> > - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> > - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> > + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
> > bus->adapter.algo_data = algo;
> > algo->setsda = set_data;
> > algo->setscl = set_clock;
> > @@ -825,9 +823,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
> > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> > else if (!HAS_GMCH_DISPLAY(dev_priv))
>
> I was slightly confused by this until I remeber that BXT uses the PCH
> offsets for the south stuff even though it doesn't have a PCH. Might
> want to add a comment here to unconfuse matter.
>
> > - dev_priv->gpio_mmio_base =
> > - i915_mmio_reg_offset(PCH_GPIOA) -
> > - i915_mmio_reg_offset(GPIOA);
> > + dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
> >
> > mutex_init(&dev_priv->gmbus_mutex);
> > init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> > --
> > 2.17.1
>
> --
> Ville Syrjälä
> Intel
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Lucas De Marchi
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-17 22:16 ` Lucas De Marchi
@ 2018-07-18 10:01 ` Ville Syrjälä
2018-07-19 17:20 ` De Marchi, Lucas
0 siblings, 1 reply; 9+ messages in thread
From: Ville Syrjälä @ 2018-07-18 10:01 UTC (permalink / raw)
To: Lucas De Marchi
Cc: Daniel Vetter, intel-gfx, Lucas De Marchi, JaniNikulajani.nikula,
Rodrigo Vivi
On Tue, Jul 17, 2018 at 03:16:53PM -0700, Lucas De Marchi wrote:
> On Fri, Jul 13, 2018 at 9:10 AM Ville Syrjälä
> <ville.syrjala@linux.intel.com> wrote:
> >
> > On Fri, Jul 13, 2018 at 08:42:11AM -0700, Lucas De Marchi wrote:
> > > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> > > that has the same address as PCH_GPIO_A and use that to calculate all
> > > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> > > the same thing.
> > >
> > > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> > > macro to return a particular gpio address and move the enum out of
> > > i915_reg.h (suggested by Jani)
> > >
> > > v3: Move base offset inside the GPIO() macro so the GMBUS defines don't
> > > actually need to be changed (suggested by Daniel/Ville)
> > >
> > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> > > drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> > > drivers/gpu/drm/i915/i915_reg.h | 24 +++++-------------------
> > > drivers/gpu/drm/i915/intel_drv.h | 16 ++++++++++++++++
> > > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++--------
> > > 5 files changed, 28 insertions(+), 29 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c b/drivers/gpu/drm/i915/gvt/handlers.c
> > > index 7a58ca555197..ecff866bbbf1 100644
> > > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > > @@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct intel_gvt *gvt)
> > >
> > > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> > > gmbus_mmio_write);
> > > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > > + MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> >
> > I have no idea of gpio_mmio_base is populated correctly at this point
> > for gvt, and I'm too lazy to find out.
>
> humn, unfortunately it is not
>
> i915_driver_load() -> i915_load_modeset_init() -> intel_setup_gmbus()
> -> dev_priv->gpio_mmio_base = ...
> i915_driver_load() -> i915_driver_init_hw() -> intel_gvt_init() ->
> intel_gvt_init_device() -> intel_gvt_setup_mmio_info() ->
> init_generic_mmio_info()
>
> Is adding a single PCH_GPIO_BASE that doesn't depend on dev_priv being
> populated for use on gvt an option?
IIRC gvt already has some local register defines (possibly due to this
same reason?). Could add a few more I suppose. +cc the gvt folks to get
their input.
>
> Lucas De Marchi
>
> >
> > > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> > >
> > > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL, NULL,
> > > diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> > > index b31d48cf7a69..596e734a874f 100644
> > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > @@ -1611,7 +1611,8 @@ struct drm_i915_private {
> > > struct mutex gmbus_mutex;
> > >
> > > /**
> > > - * Base address of the gmbus and gpio block.
> > > + * Base address of where the gmbus and gpio blocks are located (either
> > > + * on PCH or on SoC for platforms without PCH).
> > > */
> > > uint32_t gpio_mmio_base;
> > >
> > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> > > index 1f222af0324d..5e3ba9898f4e 100644
> > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > @@ -3089,18 +3089,9 @@ enum i915_power_well_id {
> > > /*
> > > * GPIO regs
> > > */
> > > -#define GPIOA _MMIO(0x5010)
> > > -#define GPIOB _MMIO(0x5014)
> > > -#define GPIOC _MMIO(0x5018)
> > > -#define GPIOD _MMIO(0x501c)
> > > -#define GPIOE _MMIO(0x5020)
> > > -#define GPIOF _MMIO(0x5024)
> > > -#define GPIOG _MMIO(0x5028)
> > > -#define GPIOH _MMIO(0x502c)
> > > -#define GPIOJ _MMIO(0x5034)
> > > -#define GPIOK _MMIO(0x5038)
> > > -#define GPIOL _MMIO(0x503C)
> > > -#define GPIOM _MMIO(0x5040)
> > > +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010 + \
> > > + 4 * (gpio))
> > > +
> > > # define GPIO_CLOCK_DIR_MASK (1 << 0)
> > > # define GPIO_CLOCK_DIR_IN (0 << 1)
> > > # define GPIO_CLOCK_DIR_OUT (1 << 1)
> > > @@ -7483,6 +7474,8 @@ enum {
> > >
> > > /* PCH */
> > >
> > > +#define PCH_DISPLAY_BASE 0xc0000u
> > > +
> > > /* south display engine interrupt: IBX */
> > > #define SDE_AUDIO_POWER_D (1 << 27)
> > > #define SDE_AUDIO_POWER_C (1 << 26)
> > > @@ -7671,13 +7664,6 @@ enum {
> > > #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> > > #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
> > >
> > > -#define PCH_GPIOA _MMIO(0xc5010)
> > > -#define PCH_GPIOB _MMIO(0xc5014)
> > > -#define PCH_GPIOC _MMIO(0xc5018)
> > > -#define PCH_GPIOD _MMIO(0xc501c)
> > > -#define PCH_GPIOE _MMIO(0xc5020)
> > > -#define PCH_GPIOF _MMIO(0xc5024)
> > > -
> > > #define PCH_GMBUS0 _MMIO(0xc5100)
> > > #define PCH_GMBUS1 _MMIO(0xc5104)
> > > #define PCH_GMBUS2 _MMIO(0xc5108)
> > > diff --git a/drivers/gpu/drm/i915/intel_drv.h b/drivers/gpu/drm/i915/intel_drv.h
> > > index b09b6389a734..2d102f95b38e 100644
> > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > @@ -152,6 +152,22 @@
> > > * Display related stuff
> > > */
> > >
> > > +enum i915_gpio {
> > > + GPIOA = 0,
> >
> > =0 not really needed
> >
> > > + GPIOB,
> > > + GPIOC,
> > > + GPIOD,
> > > + GPIOE,
> > > + GPIOF,
> > > + GPIOG,
> > > + GPIOH,
> > > + __GPIOI_UNUSED,
> > > + GPIOJ,
> > > + GPIOK,
> > > + GPIOL,
> > > + GPIOM,
> > > +};
> >
> > Weren't most things like this moved into intel_display.h a while back?
> >
> > > +
> > > /* store information about an Ixxx DVO */
> > > /* The i830->i865 use multiple DVOs with multiple i2cs */
> > > /* the i915, i945 have a single sDVO i2c bus - which is different */
> > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c b/drivers/gpu/drm/i915/intel_i2c.c
> > > index bef32b7c248e..f03c7ca718b5 100644
> > > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > > @@ -37,7 +37,7 @@
> > >
> > > struct gmbus_pin {
> > > const char *name;
> > > - i915_reg_t reg;
> > > + enum i915_gpio gpio;
> > > };
> > >
> > > /* Map gmbus pin pairs to names and registers. */
> > > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
> > > else
> > > size = ARRAY_SIZE(gmbus_pins);
> > >
> > > - return pin < size &&
> > > - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> > > + return pin < size && get_gmbus_pin(dev_priv, pin)->name;
> > > }
> > >
> > > /* Intel GPIO access functions */
> > > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
> > >
> > > algo = &bus->bit_algo;
> > >
> > > - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> > > - i915_mmio_reg_offset(get_gmbus_pin(dev_priv, pin)->reg));
> > > + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
> > > bus->adapter.algo_data = algo;
> > > algo->setsda = set_data;
> > > algo->setscl = set_clock;
> > > @@ -825,9 +823,7 @@ int intel_setup_gmbus(struct drm_i915_private *dev_priv)
> > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> > > else if (!HAS_GMCH_DISPLAY(dev_priv))
> >
> > I was slightly confused by this until I remeber that BXT uses the PCH
> > offsets for the south stuff even though it doesn't have a PCH. Might
> > want to add a comment here to unconfuse matter.
> >
> > > - dev_priv->gpio_mmio_base =
> > > - i915_mmio_reg_offset(PCH_GPIOA) -
> > > - i915_mmio_reg_offset(GPIOA);
> > > + dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
> > >
> > > mutex_init(&dev_priv->gmbus_mutex);
> > > init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> > > --
> > > 2.17.1
> >
> > --
> > Ville Syrjälä
> > Intel
> > _______________________________________________
> > Intel-gfx mailing list
> > Intel-gfx@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
>
>
> --
> Lucas De Marchi
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-18 10:01 ` Ville Syrjälä
@ 2018-07-19 17:20 ` De Marchi, Lucas
2018-07-23 2:58 ` Zhenyu Wang
0 siblings, 1 reply; 9+ messages in thread
From: De Marchi, Lucas @ 2018-07-19 17:20 UTC (permalink / raw)
To: ville.syrjala@linux.intel.com, lucas.de.marchi@gmail.com
Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org,
Vivi, Rodrigo, intel-gvt-dev@lists.freedesktop.org
CC'ing gvt maintainers (and fixing Jani's address in CC).
See below
On Wed, 2018-07-18 at 13:01 +0300, Ville Syrjälä wrote:
> On Tue, Jul 17, 2018 at 03:16:53PM -0700, Lucas De Marchi wrote:
> > On Fri, Jul 13, 2018 at 9:10 AM Ville Syrjälä
> > <ville.syrjala@linux.intel.com> wrote:
> > >
> > > On Fri, Jul 13, 2018 at 08:42:11AM -0700, Lucas De Marchi wrote:
> > > > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> > > > that has the same address as PCH_GPIO_A and use that to calculate all
> > > > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> > > > the same thing.
> > > >
> > > > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> > > > macro to return a particular gpio address and move the enum out of
> > > > i915_reg.h (suggested by Jani)
> > > >
> > > > v3: Move base offset inside the GPIO() macro so the GMBUS defines
> > > > don't
> > > > actually need to be changed (suggested by Daniel/Ville)
> > > >
> > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > ---
> > > > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> > > > drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> > > > drivers/gpu/drm/i915/i915_reg.h | 24 +++++-------------------
> > > > drivers/gpu/drm/i915/intel_drv.h | 16 ++++++++++++++++
> > > > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++--------
> > > > 5 files changed, 28 insertions(+), 29 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
> > > > b/drivers/gpu/drm/i915/gvt/handlers.c
> > > > index 7a58ca555197..ecff866bbbf1 100644
> > > > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > > > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > > > @@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct
> > > > intel_gvt *gvt)
> > > >
> > > > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> > > > gmbus_mmio_write);
> > > > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > > > + MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > >
> > > I have no idea of gpio_mmio_base is populated correctly at this point
> > > for gvt, and I'm too lazy to find out.
> >
> > humn, unfortunately it is not
> >
> > i915_driver_load() -> i915_load_modeset_init() -> intel_setup_gmbus()
> > -> dev_priv->gpio_mmio_base = ...
> > i915_driver_load() -> i915_driver_init_hw() -> intel_gvt_init() ->
> > intel_gvt_init_device() -> intel_gvt_setup_mmio_info() ->
> > init_generic_mmio_info()
> >
> > Is adding a single PCH_GPIO_BASE that doesn't depend on dev_priv being
> > populated for use on gvt an option?
>
> IIRC gvt already has some local register defines (possibly due to this
> same reason?). Could add a few more I suppose. +cc the gvt folks to get
> their input.
Summary to gvt maintainers: I want to get rid of the multiple GPIO vs PCH_GPIO
defines we have today. For that I created the GPIO() macro, but it depends on
dev_priv being populated with the gpio's block offset already which is not
true while initializing gvt.
I can define a PCH_GPIO_BASE as above in i915_reg.h that is the same as
PCH_GPIOA today. Or define it in a private gvt header. Do you have another
option/suggestion?
thanks
Lucas De Marchi
>
> >
> > Lucas De Marchi
> >
> > >
> > > > MMIO_F(_MMIO(0xe4f00), 0x28, 0, 0, 0, D_ALL, NULL, NULL);
> > > >
> > > > MMIO_F(_MMIO(_PCH_DPB_AUX_CH_CTL), 6 * 4, 0, 0, 0, D_PRE_SKL,
> > > > NULL,
> > > > diff --git a/drivers/gpu/drm/i915/i915_drv.h
> > > > b/drivers/gpu/drm/i915/i915_drv.h
> > > > index b31d48cf7a69..596e734a874f 100644
> > > > --- a/drivers/gpu/drm/i915/i915_drv.h
> > > > +++ b/drivers/gpu/drm/i915/i915_drv.h
> > > > @@ -1611,7 +1611,8 @@ struct drm_i915_private {
> > > > struct mutex gmbus_mutex;
> > > >
> > > > /**
> > > > - * Base address of the gmbus and gpio block.
> > > > + * Base address of where the gmbus and gpio blocks are located
> > > > (either
> > > > + * on PCH or on SoC for platforms without PCH).
> > > > */
> > > > uint32_t gpio_mmio_base;
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/i915_reg.h
> > > > b/drivers/gpu/drm/i915/i915_reg.h
> > > > index 1f222af0324d..5e3ba9898f4e 100644
> > > > --- a/drivers/gpu/drm/i915/i915_reg.h
> > > > +++ b/drivers/gpu/drm/i915/i915_reg.h
> > > > @@ -3089,18 +3089,9 @@ enum i915_power_well_id {
> > > > /*
> > > > * GPIO regs
> > > > */
> > > > -#define GPIOA _MMIO(0x5010)
> > > > -#define GPIOB _MMIO(0x5014)
> > > > -#define GPIOC _MMIO(0x5018)
> > > > -#define GPIOD _MMIO(0x501c)
> > > > -#define GPIOE _MMIO(0x5020)
> > > > -#define GPIOF _MMIO(0x5024)
> > > > -#define GPIOG _MMIO(0x5028)
> > > > -#define GPIOH _MMIO(0x502c)
> > > > -#define GPIOJ _MMIO(0x5034)
> > > > -#define GPIOK _MMIO(0x5038)
> > > > -#define GPIOL _MMIO(0x503C)
> > > > -#define GPIOM _MMIO(0x5040)
> > > > +#define GPIO(gpio) _MMIO(dev_priv->gpio_mmio_base + 0x5010
> > > > + \
> > > > + 4 * (gpio))
> > > > +
> > > > # define GPIO_CLOCK_DIR_MASK (1 << 0)
> > > > # define GPIO_CLOCK_DIR_IN (0 << 1)
> > > > # define GPIO_CLOCK_DIR_OUT (1 << 1)
> > > > @@ -7483,6 +7474,8 @@ enum {
> > > >
> > > > /* PCH */
> > > >
> > > > +#define PCH_DISPLAY_BASE 0xc0000u
> > > > +
> > > > /* south display engine interrupt: IBX */
> > > > #define SDE_AUDIO_POWER_D (1 << 27)
> > > > #define SDE_AUDIO_POWER_C (1 << 26)
> > > > @@ -7671,13 +7664,6 @@ enum {
> > > > #define ICP_TC_HPD_LONG_DETECT(tc_port) (2 << (tc_port) * 4)
> > > > #define ICP_TC_HPD_SHORT_DETECT(tc_port) (1 << (tc_port) * 4)
> > > >
> > > > -#define PCH_GPIOA _MMIO(0xc5010)
> > > > -#define PCH_GPIOB _MMIO(0xc5014)
> > > > -#define PCH_GPIOC _MMIO(0xc5018)
> > > > -#define PCH_GPIOD _MMIO(0xc501c)
> > > > -#define PCH_GPIOE _MMIO(0xc5020)
> > > > -#define PCH_GPIOF _MMIO(0xc5024)
> > > > -
> > > > #define PCH_GMBUS0 _MMIO(0xc5100)
> > > > #define PCH_GMBUS1 _MMIO(0xc5104)
> > > > #define PCH_GMBUS2 _MMIO(0xc5108)
> > > > diff --git a/drivers/gpu/drm/i915/intel_drv.h
> > > > b/drivers/gpu/drm/i915/intel_drv.h
> > > > index b09b6389a734..2d102f95b38e 100644
> > > > --- a/drivers/gpu/drm/i915/intel_drv.h
> > > > +++ b/drivers/gpu/drm/i915/intel_drv.h
> > > > @@ -152,6 +152,22 @@
> > > > * Display related stuff
> > > > */
> > > >
> > > > +enum i915_gpio {
> > > > + GPIOA = 0,
> > >
> > > =0 not really needed
> > >
> > > > + GPIOB,
> > > > + GPIOC,
> > > > + GPIOD,
> > > > + GPIOE,
> > > > + GPIOF,
> > > > + GPIOG,
> > > > + GPIOH,
> > > > + __GPIOI_UNUSED,
> > > > + GPIOJ,
> > > > + GPIOK,
> > > > + GPIOL,
> > > > + GPIOM,
> > > > +};
> > >
> > > Weren't most things like this moved into intel_display.h a while back?
> > >
> > > > +
> > > > /* store information about an Ixxx DVO */
> > > > /* The i830->i865 use multiple DVOs with multiple i2cs */
> > > > /* the i915, i945 have a single sDVO i2c bus - which is different */
> > > > diff --git a/drivers/gpu/drm/i915/intel_i2c.c
> > > > b/drivers/gpu/drm/i915/intel_i2c.c
> > > > index bef32b7c248e..f03c7ca718b5 100644
> > > > --- a/drivers/gpu/drm/i915/intel_i2c.c
> > > > +++ b/drivers/gpu/drm/i915/intel_i2c.c
> > > > @@ -37,7 +37,7 @@
> > > >
> > > > struct gmbus_pin {
> > > > const char *name;
> > > > - i915_reg_t reg;
> > > > + enum i915_gpio gpio;
> > > > };
> > > >
> > > > /* Map gmbus pin pairs to names and registers. */
> > > > @@ -121,8 +121,7 @@ bool intel_gmbus_is_valid_pin(struct
> > > > drm_i915_private *dev_priv,
> > > > else
> > > > size = ARRAY_SIZE(gmbus_pins);
> > > >
> > > > - return pin < size &&
> > > > - i915_mmio_reg_valid(get_gmbus_pin(dev_priv, pin)->reg);
> > > > + return pin < size && get_gmbus_pin(dev_priv, pin)->name;
> > > > }
> > > >
> > > > /* Intel GPIO access functions */
> > > > @@ -292,8 +291,7 @@ intel_gpio_setup(struct intel_gmbus *bus, unsigned
> > > > int pin)
> > > >
> > > > algo = &bus->bit_algo;
> > > >
> > > > - bus->gpio_reg = _MMIO(dev_priv->gpio_mmio_base +
> > > > - i915_mmio_reg_offset(get_gmbus_pin(dev_pri
> > > > v, pin)->reg));
> > > > + bus->gpio_reg = GPIO(get_gmbus_pin(dev_priv, pin)->gpio);
> > > > bus->adapter.algo_data = algo;
> > > > algo->setsda = set_data;
> > > > algo->setscl = set_clock;
> > > > @@ -825,9 +823,7 @@ int intel_setup_gmbus(struct drm_i915_private
> > > > *dev_priv)
> > > > if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
> > > > dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
> > > > else if (!HAS_GMCH_DISPLAY(dev_priv))
> > >
> > > I was slightly confused by this until I remeber that BXT uses the PCH
> > > offsets for the south stuff even though it doesn't have a PCH. Might
> > > want to add a comment here to unconfuse matter.
> > >
> > > > - dev_priv->gpio_mmio_base =
> > > > - i915_mmio_reg_offset(PCH_GPIOA) -
> > > > - i915_mmio_reg_offset(GPIOA);
> > > > + dev_priv->gpio_mmio_base = PCH_DISPLAY_BASE;
> > > >
> > > > mutex_init(&dev_priv->gmbus_mutex);
> > > > init_waitqueue_head(&dev_priv->gmbus_wait_queue);
> > > > --
> > > > 2.17.1
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
> > > _______________________________________________
> > > Intel-gfx mailing list
> > > Intel-gfx@lists.freedesktop.org
> > > https://lists.freedesktop.org/mailman/listinfo/intel-gfx
> >
> >
> >
> > --
> > Lucas De Marchi
>
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO
2018-07-19 17:20 ` De Marchi, Lucas
@ 2018-07-23 2:58 ` Zhenyu Wang
0 siblings, 0 replies; 9+ messages in thread
From: Zhenyu Wang @ 2018-07-23 2:58 UTC (permalink / raw)
To: De Marchi, Lucas
Cc: daniel.vetter@ffwll.ch, intel-gfx@lists.freedesktop.org,
Vivi, Rodrigo, intel-gvt-dev@lists.freedesktop.org
[-- Attachment #1.1: Type: text/plain, Size: 3808 bytes --]
On 2018.07.19 17:20:15 +0000, De Marchi, Lucas wrote:
> CC'ing gvt maintainers (and fixing Jani's address in CC).
>
> See below
>
> On Wed, 2018-07-18 at 13:01 +0300, Ville Syrjälä wrote:
> > On Tue, Jul 17, 2018 at 03:16:53PM -0700, Lucas De Marchi wrote:
> > > On Fri, Jul 13, 2018 at 9:10 AM Ville Syrjälä
> > > <ville.syrjala@linux.intel.com> wrote:
> > > >
> > > > On Fri, Jul 13, 2018 at 08:42:11AM -0700, Lucas De Marchi wrote:
> > > > > Instead of defining all registers twice, define just a PCH_GPIO_BASE
> > > > > that has the same address as PCH_GPIO_A and use that to calculate all
> > > > > the others. This also brings VLV and !HAS_GMCH_DISPLAY in line, doing
> > > > > the same thing.
> > > > >
> > > > > v2: Fix GMBUS registers to be relative to gpio base; create GPIO()
> > > > > macro to return a particular gpio address and move the enum out of
> > > > > i915_reg.h (suggested by Jani)
> > > > >
> > > > > v3: Move base offset inside the GPIO() macro so the GMBUS defines
> > > > > don't
> > > > > actually need to be changed (suggested by Daniel/Ville)
> > > > >
> > > > > Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/gvt/handlers.c | 2 +-
> > > > > drivers/gpu/drm/i915/i915_drv.h | 3 ++-
> > > > > drivers/gpu/drm/i915/i915_reg.h | 24 +++++-------------------
> > > > > drivers/gpu/drm/i915/intel_drv.h | 16 ++++++++++++++++
> > > > > drivers/gpu/drm/i915/intel_i2c.c | 12 ++++--------
> > > > > 5 files changed, 28 insertions(+), 29 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gvt/handlers.c
> > > > > b/drivers/gpu/drm/i915/gvt/handlers.c
> > > > > index 7a58ca555197..ecff866bbbf1 100644
> > > > > --- a/drivers/gpu/drm/i915/gvt/handlers.c
> > > > > +++ b/drivers/gpu/drm/i915/gvt/handlers.c
> > > > > @@ -2118,7 +2118,7 @@ static int init_generic_mmio_info(struct
> > > > > intel_gvt *gvt)
> > > > >
> > > > > MMIO_F(PCH_GMBUS0, 4 * 4, 0, 0, 0, D_ALL, gmbus_mmio_read,
> > > > > gmbus_mmio_write);
> > > > > - MMIO_F(PCH_GPIOA, 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > > > > + MMIO_F(GPIO(GPIOA), 6 * 4, F_UNALIGN, 0, 0, D_ALL, NULL, NULL);
> > > >
> > > > I have no idea of gpio_mmio_base is populated correctly at this point
> > > > for gvt, and I'm too lazy to find out.
> > >
> > > humn, unfortunately it is not
> > >
> > > i915_driver_load() -> i915_load_modeset_init() -> intel_setup_gmbus()
> > > -> dev_priv->gpio_mmio_base = ...
> > > i915_driver_load() -> i915_driver_init_hw() -> intel_gvt_init() ->
> > > intel_gvt_init_device() -> intel_gvt_setup_mmio_info() ->
> > > init_generic_mmio_info()
> > >
> > > Is adding a single PCH_GPIO_BASE that doesn't depend on dev_priv being
> > > populated for use on gvt an option?
> >
> > IIRC gvt already has some local register defines (possibly due to this
> > same reason?). Could add a few more I suppose. +cc the gvt folks to get
> > their input.
>
> Summary to gvt maintainers: I want to get rid of the multiple GPIO vs PCH_GPIO
> defines we have today. For that I created the GPIO() macro, but it depends on
> dev_priv being populated with the gpio's block offset already which is not
> true while initializing gvt.
>
This also applys to GMBUS change, right?
> I can define a PCH_GPIO_BASE as above in i915_reg.h that is the same as
> PCH_GPIOA today. Or define it in a private gvt header. Do you have another
> option/suggestion?
>
yeah, adding a base define for gvt private seems good to me, as gvt handles
MMIO trap so may need to use them in different way.
thanks
--
Open Source Technology Center, Intel ltd.
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^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2018-07-23 2:58 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2018-07-13 15:42 [PATCH v3 1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Lucas De Marchi
2018-07-13 15:42 ` [PATCH v3 2/2] drm/i915: remove PCH_GMBUS defines Lucas De Marchi
2018-07-13 16:00 ` ✗ Fi.CI.SPARSE: warning for series starting with [v3,1/2] drm/i915: remove confusing GPIO vs PCH_GPIO Patchwork
2018-07-13 16:07 ` [PATCH v3 1/2] " Ville Syrjälä
2018-07-17 22:16 ` Lucas De Marchi
2018-07-18 10:01 ` Ville Syrjälä
2018-07-19 17:20 ` De Marchi, Lucas
2018-07-23 2:58 ` Zhenyu Wang
2018-07-13 16:16 ` ✓ Fi.CI.BAT: success for series starting with [v3,1/2] " Patchwork
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