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From: hch@lst.de (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: RFC: simplified RISC-V interrupt and clocksource handling
Date: Fri, 27 Jul 2018 16:44:05 +0200	[thread overview]
Message-ID: <20180727144405.GB29626@lst.de> (raw)
In-Reply-To: <dc346650-0b48-3c2b-9190-b87ea6987e37@wdc.com>

On Thu, Jul 26, 2018 at 04:38:43PM -0700, Atish Patra wrote:
> 1. As per my understanding, timer interrupt now can't be registered as a 
> Linux IRQ now. Thus, /proc/interrupts will not be automatically populated 
> for timer interrupt stats. Am I wrong in my assumption?

Yes, with this code the timer interrupt does not show up in
/proc/interrupts.  I wonder if that is an issue and if there is any
precedence for it?

> 2. The future version of local interrupt controller known as Core Level 
> Interrupt Controller aka CLIC. Do we have to change the current design
> again for CLIC in future?
>
> Here are the docs:
> https://github.com/sifive/clic-spec/blob/master/clic.adoc

This doesn't really look like 'the future' version but a proposal for
something more like low end realtime microcontrollers ala ARM Cortex M*.
At least the priorities don't really make much sense for a general
purpose SOC.

Either way the existing architectural scause/sie interrupt handling will
remain but can be opted out, but if we really want to support the CLIC
it would have to grow a new irqchip driver, and the PLIC driver would
require a few dozend new lines of glue code to chain underneath it.

WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Atish Patra <atish.patra@wdc.com>
Cc: Christoph Hellwig <hch@lst.de>,
	"tglx@linutronix.de" <tglx@linutronix.de>,
	"palmer@sifive.com" <palmer@sifive.com>,
	"jason@lakedaemon.net" <jason@lakedaemon.net>,
	"marc.zyngier@arm.com" <marc.zyngier@arm.com>,
	"robh+dt@kernel.org" <robh+dt@kernel.org>,
	"mark.rutland@arm.com" <mark.rutland@arm.com>,
	"anup@brainfault.org" <anup@brainfault.org>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	"aou@eecs.berkeley.edu" <aou@eecs.berkeley.edu>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	"shorne@gmail.com" <shorne@gmail.com>
Subject: Re: RFC: simplified RISC-V interrupt and clocksource handling
Date: Fri, 27 Jul 2018 16:44:05 +0200	[thread overview]
Message-ID: <20180727144405.GB29626@lst.de> (raw)
In-Reply-To: <dc346650-0b48-3c2b-9190-b87ea6987e37@wdc.com>

On Thu, Jul 26, 2018 at 04:38:43PM -0700, Atish Patra wrote:
> 1. As per my understanding, timer interrupt now can't be registered as a 
> Linux IRQ now. Thus, /proc/interrupts will not be automatically populated 
> for timer interrupt stats. Am I wrong in my assumption?

Yes, with this code the timer interrupt does not show up in
/proc/interrupts.  I wonder if that is an issue and if there is any
precedence for it?

> 2. The future version of local interrupt controller known as Core Level 
> Interrupt Controller aka CLIC. Do we have to change the current design
> again for CLIC in future?
>
> Here are the docs:
> https://github.com/sifive/clic-spec/blob/master/clic.adoc

This doesn't really look like 'the future' version but a proposal for
something more like low end realtime microcontrollers ala ARM Cortex M*.
At least the priorities don't really make much sense for a general
purpose SOC.

Either way the existing architectural scause/sie interrupt handling will
remain but can be opted out, but if we really want to support the CLIC
it would have to grow a new irqchip driver, and the PLIC driver would
require a few dozend new lines of glue code to chain underneath it.

  reply	other threads:[~2018-07-27 14:44 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-26 14:37 RFC: simplified RISC-V interrupt and clocksource handling Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 1/9] RISC-V: remove timer leftovers Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 2/9] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 3/9] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 4/9] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 5/9] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-08-02  9:48   ` Thomas Gleixner
2018-08-02  9:48     ` Thomas Gleixner
2018-08-02  9:59     ` Christoph Hellwig
2018-08-02  9:59       ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 6/9] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 7/9] irqchip: add a RISC-V PLIC driver Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-28  0:04   ` Atish Patra
2018-07-28  0:04     ` Atish Patra
2018-07-30 15:51     ` Anup Patel
2018-07-30 15:51       ` Anup Patel
2018-07-31  3:21     ` Atish Patra
2018-07-31  3:21       ` Atish Patra
2018-07-31  3:21       ` Atish Patra
2018-07-31 16:57       ` Christoph Hellwig
2018-07-31 16:57         ` Christoph Hellwig
2018-08-01  0:38         ` Atish Patra
2018-08-01  0:38           ` Atish Patra
2018-08-01  0:38           ` Atish Patra
2018-08-01  7:14           ` Christoph Hellwig
2018-08-01  7:14             ` Christoph Hellwig
2018-08-01 12:16           ` Christoph Hellwig
2018-08-01 12:16             ` Christoph Hellwig
2018-08-02  1:09             ` Atish Patra
2018-08-02  1:09               ` Atish Patra
2018-08-02  9:53               ` Christoph Hellwig
2018-08-02  9:53                 ` Christoph Hellwig
2018-08-01 14:18           ` Christoph Hellwig
2018-08-01 14:18             ` Christoph Hellwig
2018-08-02  1:02             ` Atish Patra
2018-08-02  1:02               ` Atish Patra
2018-08-02  9:50               ` Christoph Hellwig
2018-08-02  9:50                 ` Christoph Hellwig
2018-07-31 16:37     ` Christoph Hellwig
2018-07-31 16:37       ` Christoph Hellwig
2018-08-02 10:04   ` Thomas Gleixner
2018-08-02 10:04     ` Thomas Gleixner
2018-08-02 11:51     ` Christoph Hellwig
2018-08-02 11:51       ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 8/9] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-08-02  7:24   ` Nikolay Borisov
2018-08-02  7:24     ` Nikolay Borisov
2018-08-02  9:52     ` Christoph Hellwig
2018-08-02  9:52       ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 9/9] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 18:51   ` Atish Patra
2018-07-26 18:51     ` Atish Patra
2018-07-27 14:41     ` Christoph Hellwig
2018-07-27 14:41       ` Christoph Hellwig
2018-07-27 17:44       ` Atish Patra
2018-07-27 17:44         ` Atish Patra
2018-07-28 21:12   ` kbuild test robot
2018-07-28 21:12     ` kbuild test robot
2018-07-28 21:16   ` kbuild test robot
2018-07-28 21:16     ` kbuild test robot
2018-07-26 23:38 ` RFC: simplified RISC-V interrupt and clocksource handling Atish Patra
2018-07-26 23:38   ` Atish Patra
2018-07-27 14:44   ` Christoph Hellwig [this message]
2018-07-27 14:44     ` Christoph Hellwig

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