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From: hch@lst.de (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH 5/9] RISC-V: implement low-level interrupt handling
Date: Thu, 2 Aug 2018 11:59:11 +0200	[thread overview]
Message-ID: <20180802095911.GA14841@lst.de> (raw)
In-Reply-To: <alpine.DEB.2.21.1808021147540.2037@nanos.tec.linutronix.de>

On Thu, Aug 02, 2018 at 11:48:55AM +0200, Thomas Gleixner wrote:
> > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> > index 9aaf6c986771..fa2c08e3c05e 100644
> > --- a/arch/riscv/kernel/entry.S
> > +++ b/arch/riscv/kernel/entry.S
> > @@ -168,8 +168,8 @@ ENTRY(handle_exception)
> >  
> >  	/* Handle interrupts */
> >  	move a0, sp /* pt_regs */
> > -	REG_L a1, handle_arch_irq
> > -	jr a1
> > +	move a1, s4 /* scause */
> > +	tail do_IRQ
> 
> What's the reason for doing the whole exception dance in ASM ?

I'll let Palmer defend it.  But for now I just want minimal changes
to actually get a booting system..

WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Thomas Gleixner <tglx@linutronix.de>
Cc: Christoph Hellwig <hch@lst.de>,
	palmer@sifive.com, jason@lakedaemon.net, marc.zyngier@arm.com,
	robh+dt@kernel.org, mark.rutland@arm.com, anup@brainfault.org,
	atish.patra@wdc.com, devicetree@vger.kernel.org,
	aou@eecs.berkeley.edu, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org, shorne@gmail.com
Subject: Re: [PATCH 5/9] RISC-V: implement low-level interrupt handling
Date: Thu, 2 Aug 2018 11:59:11 +0200	[thread overview]
Message-ID: <20180802095911.GA14841@lst.de> (raw)
In-Reply-To: <alpine.DEB.2.21.1808021147540.2037@nanos.tec.linutronix.de>

On Thu, Aug 02, 2018 at 11:48:55AM +0200, Thomas Gleixner wrote:
> > diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S
> > index 9aaf6c986771..fa2c08e3c05e 100644
> > --- a/arch/riscv/kernel/entry.S
> > +++ b/arch/riscv/kernel/entry.S
> > @@ -168,8 +168,8 @@ ENTRY(handle_exception)
> >  
> >  	/* Handle interrupts */
> >  	move a0, sp /* pt_regs */
> > -	REG_L a1, handle_arch_irq
> > -	jr a1
> > +	move a1, s4 /* scause */
> > +	tail do_IRQ
> 
> What's the reason for doing the whole exception dance in ASM ?

I'll let Palmer defend it.  But for now I just want minimal changes
to actually get a booting system..

  reply	other threads:[~2018-08-02  9:59 UTC|newest]

Thread overview: 84+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-26 14:37 RFC: simplified RISC-V interrupt and clocksource handling Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 1/9] RISC-V: remove timer leftovers Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 2/9] RISC-V: simplify software interrupt / IPI code Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 3/9] RISC-V: remove INTERRUPT_CAUSE_* defines from asm/irq.h Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 4/9] RISC-V: add a definition for the SIE SEIE bit Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 5/9] RISC-V: implement low-level interrupt handling Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-08-02  9:48   ` Thomas Gleixner
2018-08-02  9:48     ` Thomas Gleixner
2018-08-02  9:59     ` Christoph Hellwig [this message]
2018-08-02  9:59       ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 6/9] RISC-V: Support per-hart timebase-frequency Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 7/9] irqchip: add a RISC-V PLIC driver Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-28  0:04   ` Atish Patra
2018-07-28  0:04     ` Atish Patra
2018-07-30 15:51     ` Anup Patel
2018-07-30 15:51       ` Anup Patel
2018-07-31  3:21     ` Atish Patra
2018-07-31  3:21       ` Atish Patra
2018-07-31  3:21       ` Atish Patra
2018-07-31 16:57       ` Christoph Hellwig
2018-07-31 16:57         ` Christoph Hellwig
2018-08-01  0:38         ` Atish Patra
2018-08-01  0:38           ` Atish Patra
2018-08-01  0:38           ` Atish Patra
2018-08-01  7:14           ` Christoph Hellwig
2018-08-01  7:14             ` Christoph Hellwig
2018-08-01 12:16           ` Christoph Hellwig
2018-08-01 12:16             ` Christoph Hellwig
2018-08-02  1:09             ` Atish Patra
2018-08-02  1:09               ` Atish Patra
2018-08-02  9:53               ` Christoph Hellwig
2018-08-02  9:53                 ` Christoph Hellwig
2018-08-01 14:18           ` Christoph Hellwig
2018-08-01 14:18             ` Christoph Hellwig
2018-08-02  1:02             ` Atish Patra
2018-08-02  1:02               ` Atish Patra
2018-08-02  9:50               ` Christoph Hellwig
2018-08-02  9:50                 ` Christoph Hellwig
2018-07-31 16:37     ` Christoph Hellwig
2018-07-31 16:37       ` Christoph Hellwig
2018-08-02 10:04   ` Thomas Gleixner
2018-08-02 10:04     ` Thomas Gleixner
2018-08-02 11:51     ` Christoph Hellwig
2018-08-02 11:51       ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 8/9] dt-bindings: interrupt-controller: RISC-V PLIC documentation Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-08-02  7:24   ` Nikolay Borisov
2018-08-02  7:24     ` Nikolay Borisov
2018-08-02  9:52     ` Christoph Hellwig
2018-08-02  9:52       ` Christoph Hellwig
2018-07-26 14:37 ` [PATCH 9/9] clocksource: new RISC-V SBI timer driver Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 14:37   ` Christoph Hellwig
2018-07-26 18:51   ` Atish Patra
2018-07-26 18:51     ` Atish Patra
2018-07-27 14:41     ` Christoph Hellwig
2018-07-27 14:41       ` Christoph Hellwig
2018-07-27 17:44       ` Atish Patra
2018-07-27 17:44         ` Atish Patra
2018-07-28 21:12   ` kbuild test robot
2018-07-28 21:12     ` kbuild test robot
2018-07-28 21:16   ` kbuild test robot
2018-07-28 21:16     ` kbuild test robot
2018-07-26 23:38 ` RFC: simplified RISC-V interrupt and clocksource handling Atish Patra
2018-07-26 23:38   ` Atish Patra
2018-07-27 14:44   ` Christoph Hellwig
2018-07-27 14:44     ` Christoph Hellwig

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