* Re: [PATCH V4 4/4] target-i386: add i440fx 0xcf8 port ascoalesced_pio
@ 2018-08-27 8:25 ` peng.hao2
0 siblings, 0 replies; 4+ messages in thread
From: peng.hao2 @ 2018-08-27 8:25 UTC (permalink / raw)
To: liran.alon
Cc: zhong.weidong, ehabkost, kvm, rkrcmar, mst, qemu-devel, pbonzini
>> On 25 Aug 2018, at 15:19, Peng Hao <peng.hao2@zte.com.cn> wrote:
>>
>> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>> index 0e60834..da73743 100644
>> --- a/hw/pci-host/piix.c
>> +++ b/hw/pci-host/piix.c
>> @@ -327,6 +327,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
>>
>> sysbus_add_io(sbd, 0xcfc, &s->data_mem);
>> sysbus_init_ioports(sbd, 0xcfc, 4);
>> +
>> + /* register i440fx 0xcf8 port as coalesced pio */
>> + memory_region_set_flush_coalesced(&s->data_mem);
>> + memory_region_add_coalescing(&s->conf_mem, 0, 4);
>> }
>>
>Is there a reason to not register this port as coalesced PIO also for Q35?
>In q35_host_realize()?
>If not, I would do that as an extra patch as part of this series.
Just as I mentioned in patch [0/4] , you can add pci-host config port as coalesecd pio. I think it works for q35 port 0xcf8.
>-Liran
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH V4 4/4] target-i386: add i440fx 0xcf8 port ascoalesced_pio
@ 2018-08-27 8:25 ` peng.hao2
0 siblings, 0 replies; 4+ messages in thread
From: peng.hao2 @ 2018-08-27 8:25 UTC (permalink / raw)
To: liran.alon
Cc: pbonzini, mst, ehabkost, rkrcmar, kvm, qemu-devel, zhong.weidong
>> On 25 Aug 2018, at 15:19, Peng Hao <peng.hao2@zte.com.cn> wrote:
>>
>> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
>> index 0e60834..da73743 100644
>> --- a/hw/pci-host/piix.c
>> +++ b/hw/pci-host/piix.c
>> @@ -327,6 +327,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
>>
>> sysbus_add_io(sbd, 0xcfc, &s->data_mem);
>> sysbus_init_ioports(sbd, 0xcfc, 4);
>> +
>> + /* register i440fx 0xcf8 port as coalesced pio */
>> + memory_region_set_flush_coalesced(&s->data_mem);
>> + memory_region_add_coalescing(&s->conf_mem, 0, 4);
>> }
>>
>Is there a reason to not register this port as coalesced PIO also for Q35?
>In q35_host_realize()?
>If not, I would do that as an extra patch as part of this series.
Just as I mentioned in patch [0/4] , you can add pci-host config port as coalesecd pio. I think it works for q35 port 0xcf8.
>-Liran
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [PATCH V4 4/4] target-i386: add i440fx 0xcf8 port ascoalesced_pio
2018-08-27 8:25 ` [Qemu-devel] " peng.hao2
@ 2018-08-27 12:36 ` Michael S. Tsirkin
-1 siblings, 0 replies; 4+ messages in thread
From: Michael S. Tsirkin @ 2018-08-27 12:36 UTC (permalink / raw)
To: peng.hao2
Cc: zhong.weidong, ehabkost, kvm, rkrcmar, qemu-devel, liran.alon,
pbonzini
On Mon, Aug 27, 2018 at 04:25:00PM +0800, peng.hao2@zte.com.cn wrote:
> >> On 25 Aug 2018, at 15:19, Peng Hao <peng.hao2@zte.com.cn> wrote:
> >>
> >> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> >> index 0e60834..da73743 100644
> >> --- a/hw/pci-host/piix.c
> >> +++ b/hw/pci-host/piix.c
> >> @@ -327,6 +327,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
> >>
> >> sysbus_add_io(sbd, 0xcfc, &s->data_mem);
> >> sysbus_init_ioports(sbd, 0xcfc, 4);
> >> +
> >> + /* register i440fx 0xcf8 port as coalesced pio */
> >> + memory_region_set_flush_coalesced(&s->data_mem);
> >> + memory_region_add_coalescing(&s->conf_mem, 0, 4);
> >> }
> >>
>
> >Is there a reason to not register this port as coalesced PIO also for Q35?
> >In q35_host_realize()?
> >If not, I would do that as an extra patch as part of this series.
> Just as I mentioned in patch [0/4] , you can add pci-host config port as coalesecd pio. I think it works for q35 port 0xcf8.
> >-Liran
What's the performance improvement for q35?
--
MST
^ permalink raw reply [flat|nested] 4+ messages in thread
* Re: [Qemu-devel] [PATCH V4 4/4] target-i386: add i440fx 0xcf8 port ascoalesced_pio
@ 2018-08-27 12:36 ` Michael S. Tsirkin
0 siblings, 0 replies; 4+ messages in thread
From: Michael S. Tsirkin @ 2018-08-27 12:36 UTC (permalink / raw)
To: peng.hao2
Cc: liran.alon, pbonzini, ehabkost, rkrcmar, kvm, qemu-devel,
zhong.weidong
On Mon, Aug 27, 2018 at 04:25:00PM +0800, peng.hao2@zte.com.cn wrote:
> >> On 25 Aug 2018, at 15:19, Peng Hao <peng.hao2@zte.com.cn> wrote:
> >>
> >> diff --git a/hw/pci-host/piix.c b/hw/pci-host/piix.c
> >> index 0e60834..da73743 100644
> >> --- a/hw/pci-host/piix.c
> >> +++ b/hw/pci-host/piix.c
> >> @@ -327,6 +327,10 @@ static void i440fx_pcihost_realize(DeviceState *dev, Error **errp)
> >>
> >> sysbus_add_io(sbd, 0xcfc, &s->data_mem);
> >> sysbus_init_ioports(sbd, 0xcfc, 4);
> >> +
> >> + /* register i440fx 0xcf8 port as coalesced pio */
> >> + memory_region_set_flush_coalesced(&s->data_mem);
> >> + memory_region_add_coalescing(&s->conf_mem, 0, 4);
> >> }
> >>
>
> >Is there a reason to not register this port as coalesced PIO also for Q35?
> >In q35_host_realize()?
> >If not, I would do that as an extra patch as part of this series.
> Just as I mentioned in patch [0/4] , you can add pci-host config port as coalesecd pio. I think it works for q35 port 0xcf8.
> >-Liran
What's the performance improvement for q35?
--
MST
^ permalink raw reply [flat|nested] 4+ messages in thread
end of thread, other threads:[~2018-08-27 12:36 UTC | newest]
Thread overview: 4+ messages (download: mbox.gz follow: Atom feed
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2018-08-27 8:25 [PATCH V4 4/4] target-i386: add i440fx 0xcf8 port ascoalesced_pio peng.hao2
2018-08-27 8:25 ` [Qemu-devel] " peng.hao2
2018-08-27 12:36 ` Michael S. Tsirkin
2018-08-27 12:36 ` [Qemu-devel] " Michael S. Tsirkin
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