From: kbuild test robot <lkp@intel.com>
To: Daniel Drake <drake@endlessm.com>
Cc: kbuild-all@01.org, bhelgaas@google.com,
linux-pci@vger.kernel.org, linux@endlessm.com,
nouveau@lists.freedesktop.org, linux-pm@vger.kernel.org,
peter@lekensteyn.nl, kherbst@redhat.com
Subject: Re: [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
Date: Tue, 4 Sep 2018 23:31:03 +0800 [thread overview]
Message-ID: <20180904153103.GH17047@intel.com> (raw)
In-Reply-To: <20180831073057.14626-1-drake@endlessm.com>
[-- Attachment #1: Type: text/plain, Size: 13942 bytes --]
Hi Daniel,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on v4.19-rc2 next-20180831]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniel-Drake/PCI-add-prefetch-quirk-to-work-around-Asus-Nvidia-suspend-issues/20180901-043245
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-s5-09031857 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
All warnings (new ones prefixed by >>):
In file included from include/linux/export.h:45:0,
from include/linux/linkage.h:7,
from include/linux/kernel.h:7,
from drivers/pci/quirks.c:16:
drivers/pci/quirks.c: In function 'quirk_asus_pci_prefetch':
drivers/pci/quirks.c:5134:6: warning: argument 1 null where non-null expected [-Wnonnull]
if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler.h:58:30: note: in definition of macro '__trace_if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~~~
>> drivers/pci/quirks.c:5134:2: note: in expansion of macro 'if'
if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0)
^~
In file included from include/linux/uuid.h:20:0,
from include/linux/mod_devicetable.h:13,
from include/linux/pci.h:21,
from drivers/pci/quirks.c:18:
include/linux/string.h:44:12: note: in a call to function 'strcmp' declared here
extern int strcmp(const char *,const char *);
^~~~~~
# https://github.com/0day-ci/linux/commit/eccd2a8c40e1a705a666e6fe1c52aca3f2130984
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout eccd2a8c40e1a705a666e6fe1c52aca3f2130984
vim +/if +5134 drivers/pci/quirks.c
e7aaf90f9 Bjorn Helgaas 2018-08-15 4983
e7aaf90f9 Bjorn Helgaas 2018-08-15 4984 /*
ad281ecf1 Doug Meyer 2018-05-23 4985 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
ad281ecf1 Doug Meyer 2018-05-23 4986 * NT endpoints via the internal switch fabric. These IDs replace the
ad281ecf1 Doug Meyer 2018-05-23 4987 * originating requestor ID TLPs which access host memory on peer NTB
ad281ecf1 Doug Meyer 2018-05-23 4988 * ports. Therefore, all proxy IDs must be aliased to the NTB device
ad281ecf1 Doug Meyer 2018-05-23 4989 * to permit access when the IOMMU is turned on.
ad281ecf1 Doug Meyer 2018-05-23 4990 */
ad281ecf1 Doug Meyer 2018-05-23 4991 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
ad281ecf1 Doug Meyer 2018-05-23 4992 {
ad281ecf1 Doug Meyer 2018-05-23 4993 void __iomem *mmio;
ad281ecf1 Doug Meyer 2018-05-23 4994 struct ntb_info_regs __iomem *mmio_ntb;
ad281ecf1 Doug Meyer 2018-05-23 4995 struct ntb_ctrl_regs __iomem *mmio_ctrl;
ad281ecf1 Doug Meyer 2018-05-23 4996 struct sys_info_regs __iomem *mmio_sys_info;
ad281ecf1 Doug Meyer 2018-05-23 4997 u64 partition_map;
ad281ecf1 Doug Meyer 2018-05-23 4998 u8 partition;
ad281ecf1 Doug Meyer 2018-05-23 4999 int pp;
ad281ecf1 Doug Meyer 2018-05-23 5000
ad281ecf1 Doug Meyer 2018-05-23 5001 if (pci_enable_device(pdev)) {
ad281ecf1 Doug Meyer 2018-05-23 5002 pci_err(pdev, "Cannot enable Switchtec device\n");
ad281ecf1 Doug Meyer 2018-05-23 5003 return;
ad281ecf1 Doug Meyer 2018-05-23 5004 }
ad281ecf1 Doug Meyer 2018-05-23 5005
ad281ecf1 Doug Meyer 2018-05-23 5006 mmio = pci_iomap(pdev, 0, 0);
ad281ecf1 Doug Meyer 2018-05-23 5007 if (mmio == NULL) {
ad281ecf1 Doug Meyer 2018-05-23 5008 pci_disable_device(pdev);
ad281ecf1 Doug Meyer 2018-05-23 5009 pci_err(pdev, "Cannot iomap Switchtec device\n");
ad281ecf1 Doug Meyer 2018-05-23 5010 return;
ad281ecf1 Doug Meyer 2018-05-23 5011 }
ad281ecf1 Doug Meyer 2018-05-23 5012
ad281ecf1 Doug Meyer 2018-05-23 5013 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
ad281ecf1 Doug Meyer 2018-05-23 5014
ad281ecf1 Doug Meyer 2018-05-23 5015 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
ad281ecf1 Doug Meyer 2018-05-23 5016 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
ad281ecf1 Doug Meyer 2018-05-23 5017 mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
ad281ecf1 Doug Meyer 2018-05-23 5018
ad281ecf1 Doug Meyer 2018-05-23 5019 partition = ioread8(&mmio_ntb->partition_id);
ad281ecf1 Doug Meyer 2018-05-23 5020
ad281ecf1 Doug Meyer 2018-05-23 5021 partition_map = ioread32(&mmio_ntb->ep_map);
ad281ecf1 Doug Meyer 2018-05-23 5022 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
ad281ecf1 Doug Meyer 2018-05-23 5023 partition_map &= ~(1ULL << partition);
ad281ecf1 Doug Meyer 2018-05-23 5024
ad281ecf1 Doug Meyer 2018-05-23 5025 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
ad281ecf1 Doug Meyer 2018-05-23 5026 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
ad281ecf1 Doug Meyer 2018-05-23 5027 u32 table_sz = 0;
ad281ecf1 Doug Meyer 2018-05-23 5028 int te;
ad281ecf1 Doug Meyer 2018-05-23 5029
ad281ecf1 Doug Meyer 2018-05-23 5030 if (!(partition_map & (1ULL << pp)))
ad281ecf1 Doug Meyer 2018-05-23 5031 continue;
ad281ecf1 Doug Meyer 2018-05-23 5032
ad281ecf1 Doug Meyer 2018-05-23 5033 pci_dbg(pdev, "Processing partition %d\n", pp);
ad281ecf1 Doug Meyer 2018-05-23 5034
ad281ecf1 Doug Meyer 2018-05-23 5035 mmio_peer_ctrl = &mmio_ctrl[pp];
ad281ecf1 Doug Meyer 2018-05-23 5036
ad281ecf1 Doug Meyer 2018-05-23 5037 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
ad281ecf1 Doug Meyer 2018-05-23 5038 if (!table_sz) {
ad281ecf1 Doug Meyer 2018-05-23 5039 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
ad281ecf1 Doug Meyer 2018-05-23 5040 continue;
ad281ecf1 Doug Meyer 2018-05-23 5041 }
ad281ecf1 Doug Meyer 2018-05-23 5042
ad281ecf1 Doug Meyer 2018-05-23 5043 if (table_sz > 512) {
ad281ecf1 Doug Meyer 2018-05-23 5044 pci_warn(pdev,
ad281ecf1 Doug Meyer 2018-05-23 5045 "Invalid Switchtec partition %d table_sz %d\n",
ad281ecf1 Doug Meyer 2018-05-23 5046 pp, table_sz);
ad281ecf1 Doug Meyer 2018-05-23 5047 continue;
ad281ecf1 Doug Meyer 2018-05-23 5048 }
ad281ecf1 Doug Meyer 2018-05-23 5049
ad281ecf1 Doug Meyer 2018-05-23 5050 for (te = 0; te < table_sz; te++) {
ad281ecf1 Doug Meyer 2018-05-23 5051 u32 rid_entry;
ad281ecf1 Doug Meyer 2018-05-23 5052 u8 devfn;
ad281ecf1 Doug Meyer 2018-05-23 5053
ad281ecf1 Doug Meyer 2018-05-23 5054 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
ad281ecf1 Doug Meyer 2018-05-23 5055 devfn = (rid_entry >> 1) & 0xFF;
ad281ecf1 Doug Meyer 2018-05-23 5056 pci_dbg(pdev,
ad281ecf1 Doug Meyer 2018-05-23 5057 "Aliasing Partition %d Proxy ID %02x.%d\n",
ad281ecf1 Doug Meyer 2018-05-23 5058 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
ad281ecf1 Doug Meyer 2018-05-23 5059 pci_add_dma_alias(pdev, devfn);
ad281ecf1 Doug Meyer 2018-05-23 5060 }
ad281ecf1 Doug Meyer 2018-05-23 5061 }
ad281ecf1 Doug Meyer 2018-05-23 5062
ad281ecf1 Doug Meyer 2018-05-23 5063 pci_iounmap(pdev, mmio);
ad281ecf1 Doug Meyer 2018-05-23 5064 pci_disable_device(pdev);
ad281ecf1 Doug Meyer 2018-05-23 5065 }
ad281ecf1 Doug Meyer 2018-05-23 5066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8531,
ad281ecf1 Doug Meyer 2018-05-23 5067 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8532,
ad281ecf1 Doug Meyer 2018-05-23 5069 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8533,
ad281ecf1 Doug Meyer 2018-05-23 5071 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8534,
ad281ecf1 Doug Meyer 2018-05-23 5073 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8535,
ad281ecf1 Doug Meyer 2018-05-23 5075 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8536,
ad281ecf1 Doug Meyer 2018-05-23 5077 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8543,
ad281ecf1 Doug Meyer 2018-05-23 5079 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8544,
ad281ecf1 Doug Meyer 2018-05-23 5081 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8545,
ad281ecf1 Doug Meyer 2018-05-23 5083 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8546,
ad281ecf1 Doug Meyer 2018-05-23 5085 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8551,
ad281ecf1 Doug Meyer 2018-05-23 5087 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8552,
ad281ecf1 Doug Meyer 2018-05-23 5089 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8553,
ad281ecf1 Doug Meyer 2018-05-23 5091 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8554,
ad281ecf1 Doug Meyer 2018-05-23 5093 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8555,
ad281ecf1 Doug Meyer 2018-05-23 5095 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5096 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8556,
ad281ecf1 Doug Meyer 2018-05-23 5097 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8561,
ad281ecf1 Doug Meyer 2018-05-23 5099 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8562,
ad281ecf1 Doug Meyer 2018-05-23 5101 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8563,
ad281ecf1 Doug Meyer 2018-05-23 5103 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8564,
ad281ecf1 Doug Meyer 2018-05-23 5105 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8565,
ad281ecf1 Doug Meyer 2018-05-23 5107 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8566,
ad281ecf1 Doug Meyer 2018-05-23 5109 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8571,
ad281ecf1 Doug Meyer 2018-05-23 5111 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8572,
ad281ecf1 Doug Meyer 2018-05-23 5113 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8573,
ad281ecf1 Doug Meyer 2018-05-23 5115 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8574,
ad281ecf1 Doug Meyer 2018-05-23 5117 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8575,
ad281ecf1 Doug Meyer 2018-05-23 5119 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8576,
ad281ecf1 Doug Meyer 2018-05-23 5121 quirk_switchtec_ntb_dma_alias);
eccd2a8c4 Daniel Drake 2018-08-31 5122
eccd2a8c4 Daniel Drake 2018-08-31 5123 /*
eccd2a8c4 Daniel Drake 2018-08-31 5124 * The Nvidia GPU on many Intel-based Asus products is unusable after
eccd2a8c4 Daniel Drake 2018-08-31 5125 * S3 resume. However, for unknown reasons, rewriting the value of register
eccd2a8c4 Daniel Drake 2018-08-31 5126 * 'Prefetchable Base Upper 32 Bits' on the parent PCI bridge works around
eccd2a8c4 Daniel Drake 2018-08-31 5127 * the issue.
eccd2a8c4 Daniel Drake 2018-08-31 5128 */
eccd2a8c4 Daniel Drake 2018-08-31 5129 static void quirk_asus_pci_prefetch(struct pci_dev *bridge)
eccd2a8c4 Daniel Drake 2018-08-31 5130 {
eccd2a8c4 Daniel Drake 2018-08-31 5131 const char *sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
eccd2a8c4 Daniel Drake 2018-08-31 5132 u32 value;
eccd2a8c4 Daniel Drake 2018-08-31 5133
eccd2a8c4 Daniel Drake 2018-08-31 @5134 if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0)
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 34928 bytes --]
WARNING: multiple messages have this Message-ID (diff)
From: kbuild test robot <lkp-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
To: Daniel Drake <drake-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
Cc: linux-pm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
linux-pci-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
kbuild-all-JC7UmRfGjtg@public.gmane.org,
nouveau-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
bhelgaas-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org,
linux-6IF/jdPJHihWk0Htik3J/w@public.gmane.org
Subject: Re: [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues
Date: Tue, 4 Sep 2018 23:31:03 +0800 [thread overview]
Message-ID: <20180904153103.GH17047@intel.com> (raw)
In-Reply-To: <20180831073057.14626-1-drake-6IF/jdPJHihWk0Htik3J/w@public.gmane.org>
[-- Attachment #1: Type: text/plain, Size: 13942 bytes --]
Hi Daniel,
I love your patch! Perhaps something to improve:
[auto build test WARNING on pci/next]
[also build test WARNING on v4.19-rc2 next-20180831]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Daniel-Drake/PCI-add-prefetch-quirk-to-work-around-Asus-Nvidia-suspend-issues/20180901-043245
base: https://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci.git next
config: x86_64-randconfig-s5-09031857 (attached as .config)
compiler: gcc-7 (Debian 7.3.0-16) 7.3.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64
:::::: branch date: 3 days ago
:::::: commit date: 3 days ago
All warnings (new ones prefixed by >>):
In file included from include/linux/export.h:45:0,
from include/linux/linkage.h:7,
from include/linux/kernel.h:7,
from drivers/pci/quirks.c:16:
drivers/pci/quirks.c: In function 'quirk_asus_pci_prefetch':
drivers/pci/quirks.c:5134:6: warning: argument 1 null where non-null expected [-Wnonnull]
if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
include/linux/compiler.h:58:30: note: in definition of macro '__trace_if'
if (__builtin_constant_p(!!(cond)) ? !!(cond) : \
^~~~
>> drivers/pci/quirks.c:5134:2: note: in expansion of macro 'if'
if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0)
^~
In file included from include/linux/uuid.h:20:0,
from include/linux/mod_devicetable.h:13,
from include/linux/pci.h:21,
from drivers/pci/quirks.c:18:
include/linux/string.h:44:12: note: in a call to function 'strcmp' declared here
extern int strcmp(const char *,const char *);
^~~~~~
# https://github.com/0day-ci/linux/commit/eccd2a8c40e1a705a666e6fe1c52aca3f2130984
git remote add linux-review https://github.com/0day-ci/linux
git remote update linux-review
git checkout eccd2a8c40e1a705a666e6fe1c52aca3f2130984
vim +/if +5134 drivers/pci/quirks.c
e7aaf90f9 Bjorn Helgaas 2018-08-15 4983
e7aaf90f9 Bjorn Helgaas 2018-08-15 4984 /*
ad281ecf1 Doug Meyer 2018-05-23 4985 * Microsemi Switchtec NTB uses devfn proxy IDs to move TLPs between
ad281ecf1 Doug Meyer 2018-05-23 4986 * NT endpoints via the internal switch fabric. These IDs replace the
ad281ecf1 Doug Meyer 2018-05-23 4987 * originating requestor ID TLPs which access host memory on peer NTB
ad281ecf1 Doug Meyer 2018-05-23 4988 * ports. Therefore, all proxy IDs must be aliased to the NTB device
ad281ecf1 Doug Meyer 2018-05-23 4989 * to permit access when the IOMMU is turned on.
ad281ecf1 Doug Meyer 2018-05-23 4990 */
ad281ecf1 Doug Meyer 2018-05-23 4991 static void quirk_switchtec_ntb_dma_alias(struct pci_dev *pdev)
ad281ecf1 Doug Meyer 2018-05-23 4992 {
ad281ecf1 Doug Meyer 2018-05-23 4993 void __iomem *mmio;
ad281ecf1 Doug Meyer 2018-05-23 4994 struct ntb_info_regs __iomem *mmio_ntb;
ad281ecf1 Doug Meyer 2018-05-23 4995 struct ntb_ctrl_regs __iomem *mmio_ctrl;
ad281ecf1 Doug Meyer 2018-05-23 4996 struct sys_info_regs __iomem *mmio_sys_info;
ad281ecf1 Doug Meyer 2018-05-23 4997 u64 partition_map;
ad281ecf1 Doug Meyer 2018-05-23 4998 u8 partition;
ad281ecf1 Doug Meyer 2018-05-23 4999 int pp;
ad281ecf1 Doug Meyer 2018-05-23 5000
ad281ecf1 Doug Meyer 2018-05-23 5001 if (pci_enable_device(pdev)) {
ad281ecf1 Doug Meyer 2018-05-23 5002 pci_err(pdev, "Cannot enable Switchtec device\n");
ad281ecf1 Doug Meyer 2018-05-23 5003 return;
ad281ecf1 Doug Meyer 2018-05-23 5004 }
ad281ecf1 Doug Meyer 2018-05-23 5005
ad281ecf1 Doug Meyer 2018-05-23 5006 mmio = pci_iomap(pdev, 0, 0);
ad281ecf1 Doug Meyer 2018-05-23 5007 if (mmio == NULL) {
ad281ecf1 Doug Meyer 2018-05-23 5008 pci_disable_device(pdev);
ad281ecf1 Doug Meyer 2018-05-23 5009 pci_err(pdev, "Cannot iomap Switchtec device\n");
ad281ecf1 Doug Meyer 2018-05-23 5010 return;
ad281ecf1 Doug Meyer 2018-05-23 5011 }
ad281ecf1 Doug Meyer 2018-05-23 5012
ad281ecf1 Doug Meyer 2018-05-23 5013 pci_info(pdev, "Setting Switchtec proxy ID aliases\n");
ad281ecf1 Doug Meyer 2018-05-23 5014
ad281ecf1 Doug Meyer 2018-05-23 5015 mmio_ntb = mmio + SWITCHTEC_GAS_NTB_OFFSET;
ad281ecf1 Doug Meyer 2018-05-23 5016 mmio_ctrl = (void __iomem *) mmio_ntb + SWITCHTEC_NTB_REG_CTRL_OFFSET;
ad281ecf1 Doug Meyer 2018-05-23 5017 mmio_sys_info = mmio + SWITCHTEC_GAS_SYS_INFO_OFFSET;
ad281ecf1 Doug Meyer 2018-05-23 5018
ad281ecf1 Doug Meyer 2018-05-23 5019 partition = ioread8(&mmio_ntb->partition_id);
ad281ecf1 Doug Meyer 2018-05-23 5020
ad281ecf1 Doug Meyer 2018-05-23 5021 partition_map = ioread32(&mmio_ntb->ep_map);
ad281ecf1 Doug Meyer 2018-05-23 5022 partition_map |= ((u64) ioread32(&mmio_ntb->ep_map + 4)) << 32;
ad281ecf1 Doug Meyer 2018-05-23 5023 partition_map &= ~(1ULL << partition);
ad281ecf1 Doug Meyer 2018-05-23 5024
ad281ecf1 Doug Meyer 2018-05-23 5025 for (pp = 0; pp < (sizeof(partition_map) * 8); pp++) {
ad281ecf1 Doug Meyer 2018-05-23 5026 struct ntb_ctrl_regs __iomem *mmio_peer_ctrl;
ad281ecf1 Doug Meyer 2018-05-23 5027 u32 table_sz = 0;
ad281ecf1 Doug Meyer 2018-05-23 5028 int te;
ad281ecf1 Doug Meyer 2018-05-23 5029
ad281ecf1 Doug Meyer 2018-05-23 5030 if (!(partition_map & (1ULL << pp)))
ad281ecf1 Doug Meyer 2018-05-23 5031 continue;
ad281ecf1 Doug Meyer 2018-05-23 5032
ad281ecf1 Doug Meyer 2018-05-23 5033 pci_dbg(pdev, "Processing partition %d\n", pp);
ad281ecf1 Doug Meyer 2018-05-23 5034
ad281ecf1 Doug Meyer 2018-05-23 5035 mmio_peer_ctrl = &mmio_ctrl[pp];
ad281ecf1 Doug Meyer 2018-05-23 5036
ad281ecf1 Doug Meyer 2018-05-23 5037 table_sz = ioread16(&mmio_peer_ctrl->req_id_table_size);
ad281ecf1 Doug Meyer 2018-05-23 5038 if (!table_sz) {
ad281ecf1 Doug Meyer 2018-05-23 5039 pci_warn(pdev, "Partition %d table_sz 0\n", pp);
ad281ecf1 Doug Meyer 2018-05-23 5040 continue;
ad281ecf1 Doug Meyer 2018-05-23 5041 }
ad281ecf1 Doug Meyer 2018-05-23 5042
ad281ecf1 Doug Meyer 2018-05-23 5043 if (table_sz > 512) {
ad281ecf1 Doug Meyer 2018-05-23 5044 pci_warn(pdev,
ad281ecf1 Doug Meyer 2018-05-23 5045 "Invalid Switchtec partition %d table_sz %d\n",
ad281ecf1 Doug Meyer 2018-05-23 5046 pp, table_sz);
ad281ecf1 Doug Meyer 2018-05-23 5047 continue;
ad281ecf1 Doug Meyer 2018-05-23 5048 }
ad281ecf1 Doug Meyer 2018-05-23 5049
ad281ecf1 Doug Meyer 2018-05-23 5050 for (te = 0; te < table_sz; te++) {
ad281ecf1 Doug Meyer 2018-05-23 5051 u32 rid_entry;
ad281ecf1 Doug Meyer 2018-05-23 5052 u8 devfn;
ad281ecf1 Doug Meyer 2018-05-23 5053
ad281ecf1 Doug Meyer 2018-05-23 5054 rid_entry = ioread32(&mmio_peer_ctrl->req_id_table[te]);
ad281ecf1 Doug Meyer 2018-05-23 5055 devfn = (rid_entry >> 1) & 0xFF;
ad281ecf1 Doug Meyer 2018-05-23 5056 pci_dbg(pdev,
ad281ecf1 Doug Meyer 2018-05-23 5057 "Aliasing Partition %d Proxy ID %02x.%d\n",
ad281ecf1 Doug Meyer 2018-05-23 5058 pp, PCI_SLOT(devfn), PCI_FUNC(devfn));
ad281ecf1 Doug Meyer 2018-05-23 5059 pci_add_dma_alias(pdev, devfn);
ad281ecf1 Doug Meyer 2018-05-23 5060 }
ad281ecf1 Doug Meyer 2018-05-23 5061 }
ad281ecf1 Doug Meyer 2018-05-23 5062
ad281ecf1 Doug Meyer 2018-05-23 5063 pci_iounmap(pdev, mmio);
ad281ecf1 Doug Meyer 2018-05-23 5064 pci_disable_device(pdev);
ad281ecf1 Doug Meyer 2018-05-23 5065 }
ad281ecf1 Doug Meyer 2018-05-23 5066 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8531,
ad281ecf1 Doug Meyer 2018-05-23 5067 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5068 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8532,
ad281ecf1 Doug Meyer 2018-05-23 5069 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5070 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8533,
ad281ecf1 Doug Meyer 2018-05-23 5071 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5072 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8534,
ad281ecf1 Doug Meyer 2018-05-23 5073 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5074 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8535,
ad281ecf1 Doug Meyer 2018-05-23 5075 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5076 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8536,
ad281ecf1 Doug Meyer 2018-05-23 5077 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5078 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8543,
ad281ecf1 Doug Meyer 2018-05-23 5079 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5080 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8544,
ad281ecf1 Doug Meyer 2018-05-23 5081 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5082 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8545,
ad281ecf1 Doug Meyer 2018-05-23 5083 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5084 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8546,
ad281ecf1 Doug Meyer 2018-05-23 5085 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5086 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8551,
ad281ecf1 Doug Meyer 2018-05-23 5087 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5088 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8552,
ad281ecf1 Doug Meyer 2018-05-23 5089 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5090 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8553,
ad281ecf1 Doug Meyer 2018-05-23 5091 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5092 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8554,
ad281ecf1 Doug Meyer 2018-05-23 5093 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5094 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8555,
ad281ecf1 Doug Meyer 2018-05-23 5095 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5096 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8556,
ad281ecf1 Doug Meyer 2018-05-23 5097 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5098 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8561,
ad281ecf1 Doug Meyer 2018-05-23 5099 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5100 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8562,
ad281ecf1 Doug Meyer 2018-05-23 5101 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5102 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8563,
ad281ecf1 Doug Meyer 2018-05-23 5103 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5104 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8564,
ad281ecf1 Doug Meyer 2018-05-23 5105 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5106 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8565,
ad281ecf1 Doug Meyer 2018-05-23 5107 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5108 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8566,
ad281ecf1 Doug Meyer 2018-05-23 5109 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5110 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8571,
ad281ecf1 Doug Meyer 2018-05-23 5111 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5112 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8572,
ad281ecf1 Doug Meyer 2018-05-23 5113 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5114 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8573,
ad281ecf1 Doug Meyer 2018-05-23 5115 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5116 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8574,
ad281ecf1 Doug Meyer 2018-05-23 5117 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5118 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8575,
ad281ecf1 Doug Meyer 2018-05-23 5119 quirk_switchtec_ntb_dma_alias);
ad281ecf1 Doug Meyer 2018-05-23 5120 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_MICROSEMI, 0x8576,
ad281ecf1 Doug Meyer 2018-05-23 5121 quirk_switchtec_ntb_dma_alias);
eccd2a8c4 Daniel Drake 2018-08-31 5122
eccd2a8c4 Daniel Drake 2018-08-31 5123 /*
eccd2a8c4 Daniel Drake 2018-08-31 5124 * The Nvidia GPU on many Intel-based Asus products is unusable after
eccd2a8c4 Daniel Drake 2018-08-31 5125 * S3 resume. However, for unknown reasons, rewriting the value of register
eccd2a8c4 Daniel Drake 2018-08-31 5126 * 'Prefetchable Base Upper 32 Bits' on the parent PCI bridge works around
eccd2a8c4 Daniel Drake 2018-08-31 5127 * the issue.
eccd2a8c4 Daniel Drake 2018-08-31 5128 */
eccd2a8c4 Daniel Drake 2018-08-31 5129 static void quirk_asus_pci_prefetch(struct pci_dev *bridge)
eccd2a8c4 Daniel Drake 2018-08-31 5130 {
eccd2a8c4 Daniel Drake 2018-08-31 5131 const char *sys_vendor = dmi_get_system_info(DMI_SYS_VENDOR);
eccd2a8c4 Daniel Drake 2018-08-31 5132 u32 value;
eccd2a8c4 Daniel Drake 2018-08-31 5133
eccd2a8c4 Daniel Drake 2018-08-31 @5134 if (strcmp(sys_vendor, "ASUSTeK COMPUTER INC.") != 0)
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
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_______________________________________________
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next prev parent reply other threads:[~2018-09-04 19:44 UTC|newest]
Thread overview: 24+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-31 7:30 [PATCH] PCI: add prefetch quirk to work around Asus/Nvidia suspend issues Daniel Drake
2018-08-31 7:30 ` Daniel Drake
2018-08-31 19:12 ` Bjorn Helgaas
2018-08-31 19:12 ` Bjorn Helgaas
2018-09-03 8:56 ` Daniel Drake
2018-09-03 8:56 ` Daniel Drake
2018-09-03 12:12 ` Mika Westerberg
2018-09-03 12:12 ` Mika Westerberg
2018-09-04 1:52 ` Daniel Drake
2018-09-04 1:52 ` Daniel Drake
2018-09-04 6:43 ` Mika Westerberg
2018-09-04 6:43 ` Mika Westerberg
2018-09-04 7:07 ` Daniel Drake
2018-09-04 7:07 ` Daniel Drake
2018-09-04 9:36 ` Mika Westerberg
2018-09-04 9:36 ` Mika Westerberg
2018-09-06 9:02 ` Daniel Drake
2018-09-06 9:02 ` Daniel Drake
2018-08-31 21:47 ` kbuild test robot
2018-08-31 21:47 ` kbuild test robot
2018-09-04 15:31 ` kbuild test robot [this message]
2018-09-04 15:31 ` kbuild test robot
2018-09-06 13:35 ` [Nouveau] " Thomas Martitz
2018-09-06 13:35 ` Thomas Martitz
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