From: hch@infradead.org (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver
Date: Mon, 10 Sep 2018 09:35:43 -0700 [thread overview]
Message-ID: <20180910163543.GA13052@infradead.org> (raw)
In-Reply-To: <CAAhSdy2Y-XTZ12i5aV+SzraMZP1YQBhAArpER-YssPcBJNOPOA@mail.gmail.com>
On Mon, Sep 10, 2018 at 10:02:09PM +0530, Anup Patel wrote:
> You are thinking very much in-context of SiFive CPUs only.
No. I think in terms of the RISC-V spec. I could care less about
SiFive to be honest.
> Lot of SOC vendors are trying to come-up with their own CPUs
> and RISC-V spec does not restrict the use of local interrupts.
Yes, it does.
> The mie/mip/sie/sip/uie/uip are all machine word size so on
> riscv64 we can theoretically have maximum 64 local interrupts.
They could in theory IFF someone actually get the use case through
the riscv privileged spec working group.
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: Christoph Hellwig <hch@infradead.org>,
Thomas Gleixner <tglx@linutronix.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Palmer Dabbelt <palmer@sifive.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver
Date: Mon, 10 Sep 2018 09:35:43 -0700 [thread overview]
Message-ID: <20180910163543.GA13052@infradead.org> (raw)
In-Reply-To: <CAAhSdy2Y-XTZ12i5aV+SzraMZP1YQBhAArpER-YssPcBJNOPOA@mail.gmail.com>
On Mon, Sep 10, 2018 at 10:02:09PM +0530, Anup Patel wrote:
> You are thinking very much in-context of SiFive CPUs only.
No. I think in terms of the RISC-V spec. I could care less about
SiFive to be honest.
> Lot of SOC vendors are trying to come-up with their own CPUs
> and RISC-V spec does not restrict the use of local interrupts.
Yes, it does.
> The mie/mip/sie/sip/uie/uip are all machine word size so on
> riscv64 we can theoretically have maximum 64 local interrupts.
They could in theory IFF someone actually get the use case through
the riscv privileged spec working group.
next prev parent reply other threads:[~2018-09-10 16:35 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-06 12:36 [PATCH v2 0/5] New RISC-V Local Interrupt Controller Driver Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 1/5] RISC-V: self-contained IPI handling routine Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 2/5] RISC-V: No need to pass scause as arg to do_IRQ() Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 14:06 ` Christoph Hellwig
2018-09-06 14:06 ` Christoph Hellwig
2018-09-06 14:19 ` Anup Patel
2018-09-06 14:19 ` Anup Patel
2018-09-08 10:46 ` Thomas Gleixner
2018-09-08 10:46 ` Thomas Gleixner
2018-09-10 13:29 ` Christoph Hellwig
2018-09-10 13:29 ` Christoph Hellwig
2018-09-10 13:34 ` Thomas Gleixner
2018-09-10 13:34 ` Thomas Gleixner
2018-09-10 13:37 ` Thomas Gleixner
2018-09-10 13:37 ` Thomas Gleixner
2018-09-10 13:39 ` Christoph Hellwig
2018-09-10 13:39 ` Christoph Hellwig
2018-09-10 13:45 ` Thomas Gleixner
2018-09-10 13:45 ` Thomas Gleixner
2018-09-10 13:49 ` Christoph Hellwig
2018-09-10 13:49 ` Christoph Hellwig
2018-09-10 14:29 ` Anup Patel
2018-09-10 14:29 ` Anup Patel
2018-09-10 16:07 ` Thomas Gleixner
2018-09-10 16:07 ` Thomas Gleixner
2018-09-10 16:11 ` Christoph Hellwig
2018-09-10 16:11 ` Christoph Hellwig
2018-09-10 16:35 ` Anup Patel
2018-09-10 16:35 ` Anup Patel
2018-09-10 16:39 ` Christoph Hellwig
2018-09-10 16:39 ` Christoph Hellwig
2018-09-10 17:11 ` Anup Patel
2018-09-10 17:11 ` Anup Patel
2018-09-10 19:37 ` Thomas Gleixner
2018-09-10 19:37 ` Thomas Gleixner
2018-09-10 22:19 ` Christoph Hellwig
2018-09-10 22:19 ` Christoph Hellwig
2018-09-11 3:57 ` Anup Patel
2018-09-11 3:57 ` Anup Patel
2018-09-11 6:22 ` Christoph Hellwig
2018-09-11 6:22 ` Christoph Hellwig
2018-09-10 22:16 ` Christoph Hellwig
2018-09-10 22:16 ` Christoph Hellwig
2018-09-10 16:13 ` Christoph Hellwig
2018-09-10 16:13 ` Christoph Hellwig
2018-09-10 16:32 ` Anup Patel
2018-09-10 16:32 ` Anup Patel
2018-09-10 16:35 ` Christoph Hellwig [this message]
2018-09-10 16:35 ` Christoph Hellwig
2018-09-10 16:38 ` Anup Patel
2018-09-10 16:38 ` Anup Patel
2018-09-17 14:14 ` Christoph Hellwig
2018-09-17 14:14 ` Christoph Hellwig
2018-09-17 14:28 ` Anup Patel
2018-09-17 14:28 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-06 12:36 ` [PATCH v2 4/5] clocksource: riscv_timer: Make timer interrupt as a per-CPU interrupt Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 5/5] RISC-V: Remove do_IRQ() function Anup Patel
2018-09-06 12:36 ` Anup Patel
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