From: hch@infradead.org (Christoph Hellwig)
To: linux-riscv@lists.infradead.org
Subject: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver
Date: Mon, 10 Sep 2018 15:16:46 -0700 [thread overview]
Message-ID: <20180910221646.GA7368@infradead.org> (raw)
In-Reply-To: <CAAhSdy3AN4YTaAJCR50WMB8CgaoZNeT9uOZt2GH2O6i8Y6z6ew@mail.gmail.com>
On Mon, Sep 10, 2018 at 10:41:22PM +0530, Anup Patel wrote:
> RISC-V priv spec 1.10 defines the 9 bits in MIE and MIP registers and
> other bits are reserved.
>
> The unused bits in MIP are WIRI (reserved write ignored and read ignored)
> and unused bits in MIE are WPRI (reserved write preserve values and
> read ignored).
>
> The RISC-V priv spec 1.10 does not tell that unused reserved bits in
> MIE/MIP cannot be used for:
> 1. CPU implementation specific local interrupts
> 2. Per-CPU device interrupts.
>
> The RISC-V priv spec 1.10 tries to only describe MIE/MIP bits which
> are mandatory on any RISC-V 1.10 compliant CPU but it possible to
> used other reserved bits for implementation specific local interrupts.
Reserved means reserved for future versions of the spec, not for vendor
specific bad ideas.
WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@infradead.org>
To: Anup Patel <anup@brainfault.org>
Cc: Christoph Hellwig <hch@infradead.org>,
Thomas Gleixner <tglx@linutronix.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Jason Cooper <jason@lakedaemon.net>,
Marc Zyngier <marc.zyngier@arm.com>,
Palmer Dabbelt <palmer@sifive.com>,
"linux-kernel@vger.kernel.org List"
<linux-kernel@vger.kernel.org>, Atish Patra <atish.patra@wdc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Palmer Dabbelt <palmer@dabbelt.com>,
linux-riscv@lists.infradead.org
Subject: Re: [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver
Date: Mon, 10 Sep 2018 15:16:46 -0700 [thread overview]
Message-ID: <20180910221646.GA7368@infradead.org> (raw)
In-Reply-To: <CAAhSdy3AN4YTaAJCR50WMB8CgaoZNeT9uOZt2GH2O6i8Y6z6ew@mail.gmail.com>
On Mon, Sep 10, 2018 at 10:41:22PM +0530, Anup Patel wrote:
> RISC-V priv spec 1.10 defines the 9 bits in MIE and MIP registers and
> other bits are reserved.
>
> The unused bits in MIP are WIRI (reserved write ignored and read ignored)
> and unused bits in MIE are WPRI (reserved write preserve values and
> read ignored).
>
> The RISC-V priv spec 1.10 does not tell that unused reserved bits in
> MIE/MIP cannot be used for:
> 1. CPU implementation specific local interrupts
> 2. Per-CPU device interrupts.
>
> The RISC-V priv spec 1.10 tries to only describe MIE/MIP bits which
> are mandatory on any RISC-V 1.10 compliant CPU but it possible to
> used other reserved bits for implementation specific local interrupts.
Reserved means reserved for future versions of the spec, not for vendor
specific bad ideas.
next prev parent reply other threads:[~2018-09-10 22:16 UTC|newest]
Thread overview: 70+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-06 12:36 [PATCH v2 0/5] New RISC-V Local Interrupt Controller Driver Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 1/5] RISC-V: self-contained IPI handling routine Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 2/5] RISC-V: No need to pass scause as arg to do_IRQ() Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 3/5] irqchip: RISC-V Local Interrupt Controller Driver Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 14:06 ` Christoph Hellwig
2018-09-06 14:06 ` Christoph Hellwig
2018-09-06 14:19 ` Anup Patel
2018-09-06 14:19 ` Anup Patel
2018-09-08 10:46 ` Thomas Gleixner
2018-09-08 10:46 ` Thomas Gleixner
2018-09-10 13:29 ` Christoph Hellwig
2018-09-10 13:29 ` Christoph Hellwig
2018-09-10 13:34 ` Thomas Gleixner
2018-09-10 13:34 ` Thomas Gleixner
2018-09-10 13:37 ` Thomas Gleixner
2018-09-10 13:37 ` Thomas Gleixner
2018-09-10 13:39 ` Christoph Hellwig
2018-09-10 13:39 ` Christoph Hellwig
2018-09-10 13:45 ` Thomas Gleixner
2018-09-10 13:45 ` Thomas Gleixner
2018-09-10 13:49 ` Christoph Hellwig
2018-09-10 13:49 ` Christoph Hellwig
2018-09-10 14:29 ` Anup Patel
2018-09-10 14:29 ` Anup Patel
2018-09-10 16:07 ` Thomas Gleixner
2018-09-10 16:07 ` Thomas Gleixner
2018-09-10 16:11 ` Christoph Hellwig
2018-09-10 16:11 ` Christoph Hellwig
2018-09-10 16:35 ` Anup Patel
2018-09-10 16:35 ` Anup Patel
2018-09-10 16:39 ` Christoph Hellwig
2018-09-10 16:39 ` Christoph Hellwig
2018-09-10 17:11 ` Anup Patel
2018-09-10 17:11 ` Anup Patel
2018-09-10 19:37 ` Thomas Gleixner
2018-09-10 19:37 ` Thomas Gleixner
2018-09-10 22:19 ` Christoph Hellwig
2018-09-10 22:19 ` Christoph Hellwig
2018-09-11 3:57 ` Anup Patel
2018-09-11 3:57 ` Anup Patel
2018-09-11 6:22 ` Christoph Hellwig
2018-09-11 6:22 ` Christoph Hellwig
2018-09-10 22:16 ` Christoph Hellwig [this message]
2018-09-10 22:16 ` Christoph Hellwig
2018-09-10 16:13 ` Christoph Hellwig
2018-09-10 16:13 ` Christoph Hellwig
2018-09-10 16:32 ` Anup Patel
2018-09-10 16:32 ` Anup Patel
2018-09-10 16:35 ` Christoph Hellwig
2018-09-10 16:35 ` Christoph Hellwig
2018-09-10 16:38 ` Anup Patel
2018-09-10 16:38 ` Anup Patel
2018-09-17 14:14 ` Christoph Hellwig
2018-09-17 14:14 ` Christoph Hellwig
2018-09-17 14:28 ` Anup Patel
2018-09-17 14:28 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 5:54 ` Anup Patel
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-26 15:38 ` Palmer Dabbelt
2018-09-06 12:36 ` [PATCH v2 4/5] clocksource: riscv_timer: Make timer interrupt as a per-CPU interrupt Anup Patel
2018-09-06 12:36 ` Anup Patel
2018-09-06 12:36 ` [PATCH v2 5/5] RISC-V: Remove do_IRQ() function Anup Patel
2018-09-06 12:36 ` Anup Patel
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