* [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
2018-10-18 22:16 [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
@ 2018-10-18 22:16 ` Manasi Navare
2018-10-20 0:52 ` Souza, Jose
2018-10-18 22:41 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Patchwork
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Manasi Navare @ 2018-10-18 22:16 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Paulo Zanoni
In case of Legacy DP connector on TypeC port, the
flex IO DPMLE register is set to number of lanes configured
by the display driver which will be programmed into DDI_BUF_CTL
PORT_WIDTH_SELECTION.
This needs to be programmed before enabling the shared PLLs hence
add a pre_pll_enable hook for ICL and add this programming in that hook.
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 52 ++++++++++++++++++++++++++++++++
1 file changed, 52 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6b9742baa5f2..fd84f88753cb 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3311,6 +3311,56 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
}
+static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ enum port port)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
+ bool lane_reversal = (dig_port->tc_type == TC_PORT_TYPEC) ? false :
+ dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+
+ val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
+ switch (pipe_config->lane_count) {
+ case 1:
+ val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
+ DFLEXDPMLE1_DPMLETC_ML0(tc_port);
+ break;
+ case 2:
+ val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
+ DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
+ break;
+ case 4:
+ val |= DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port);
+ break;
+ default:
+ MISSING_CASE(pipe_config->lane_count);
+ }
+ I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
+}
+
+static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ const struct drm_connector_state *conn_state)
+{
+ enum port port = encoder->port;
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+ if (intel_port_is_combophy(to_i915(encoder->base.dev), port))
+ return;
+
+ /*
+ * Program the lane count for static/dynamic connections on Type-C ports.
+ * Skip this step for TBT.
+ */
+ if (dig_port->tc_type == TC_PORT_TBT)
+ return;
+
+ intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
+}
+
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -3828,6 +3878,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_encoder->enable = intel_enable_ddi;
if (IS_GEN9_LP(dev_priv))
intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
+ if (IS_ICELAKE(dev_priv))
+ intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
intel_encoder->pre_enable = intel_ddi_pre_enable;
intel_encoder->disable = intel_disable_ddi;
intel_encoder->post_disable = intel_ddi_post_disable;
--
2.18.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
2018-10-18 22:16 ` [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook Manasi Navare
@ 2018-10-20 0:52 ` Souza, Jose
2018-10-22 19:15 ` Manasi Navare
0 siblings, 1 reply; 9+ messages in thread
From: Souza, Jose @ 2018-10-20 0:52 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Navare, Manasi D
Cc: De Marchi, Lucas, Zanoni, Paulo R
On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote:
> In case of Legacy DP connector on TypeC port, the
> flex IO DPMLE register is set to number of lanes configured
> by the display driver which will be programmed into DDI_BUF_CTL
> PORT_WIDTH_SELECTION.
> This needs to be programmed before enabling the shared PLLs hence
> add a pre_pll_enable hook for ICL and add this programming in that
> hook.
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 52
> ++++++++++++++++++++++++++++++++
> 1 file changed, 52 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> b/drivers/gpu/drm/i915/intel_ddi.c
> index 6b9742baa5f2..fd84f88753cb 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3311,6 +3311,56 @@ static void bxt_ddi_pre_pll_enable(struct
> intel_encoder *encoder,
> bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
> }
>
> +static void intel_ddi_set_fia_lane_count(struct intel_encoder
> *encoder,
> + const struct intel_crtc_state
> *pipe_config,
> + enum port port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
> + bool lane_reversal = (dig_port->tc_type == TC_PORT_TYPEC) ?
> false :
> + dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
I guess this is more easy to read:
bool lane_reversal = dig_port->tc_type == TC_PORT_TYPEC && dig_port-
>saved_port_bits & DDI_BUF_PORT_REVERSAL;
> +
> + val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> + switch (pipe_config->lane_count) {
> + case 1:
> + val |= (lane_reversal) ?
> DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
> + DFLEXDPMLE1_DPMLETC_ML0(tc_port);
For me the DFLEXDPMLE1_DPMLETC_ML0(tc_port); should be align with '('
but if bot said that it is okay...
> + break;
> + case 2:
> + val |= (lane_reversal) ?
> DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
> + DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
> + break;
> + case 4:
> + val |= DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port);
> + break;
> + default:
> + MISSING_CASE(pipe_config->lane_count);
> + }
> + I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
> +}
> +
> +static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state
> *pipe_config,
> + const struct drm_connector_state
> *conn_state)
> +{
> + enum port port = encoder->port;
> + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> >base);
> +
> + if (intel_port_is_combophy(to_i915(encoder->base.dev), port))
> + return;
Combophy ports will have dig_port->tc_type == TC_PORT_UNKNOWN so you
can drop this.
With this change:
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> +
> + /*
> + * Program the lane count for static/dynamic connections on
> Type-C ports.
> + * Skip this step for TBT.
> + */
> + if (dig_port->tc_type == TC_PORT_TBT)
> + return;
> +
> + intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
> +}
> +
> void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *intel_dig_port =
> dp_to_dig_port(intel_dp);
> @@ -3828,6 +3878,8 @@ void intel_ddi_init(struct drm_i915_private
> *dev_priv, enum port port)
> intel_encoder->enable = intel_enable_ddi;
> if (IS_GEN9_LP(dev_priv))
> intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> + if (IS_ICELAKE(dev_priv))
> + intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
> intel_encoder->pre_enable = intel_ddi_pre_enable;
> intel_encoder->disable = intel_disable_ddi;
> intel_encoder->post_disable = intel_ddi_post_disable;
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
2018-10-20 0:52 ` Souza, Jose
@ 2018-10-22 19:15 ` Manasi Navare
0 siblings, 0 replies; 9+ messages in thread
From: Manasi Navare @ 2018-10-22 19:15 UTC (permalink / raw)
To: Souza, Jose
Cc: intel-gfx@lists.freedesktop.org, De Marchi, Lucas,
Zanoni, Paulo R
On Fri, Oct 19, 2018 at 05:52:14PM -0700, Souza, Jose wrote:
> On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote:
> > In case of Legacy DP connector on TypeC port, the
> > flex IO DPMLE register is set to number of lanes configured
> > by the display driver which will be programmed into DDI_BUF_CTL
> > PORT_WIDTH_SELECTION.
> > This needs to be programmed before enabling the shared PLLs hence
> > add a pre_pll_enable hook for ICL and add this programming in that
> > hook.
> >
> > Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> > Cc: Jose Roberto de Souza <jose.souza@intel.com>
> > Cc: Animesh Manna <animesh.manna@intel.com>
> > Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> > Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> > ---
> > drivers/gpu/drm/i915/intel_ddi.c | 52
> > ++++++++++++++++++++++++++++++++
> > 1 file changed, 52 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/intel_ddi.c
> > b/drivers/gpu/drm/i915/intel_ddi.c
> > index 6b9742baa5f2..fd84f88753cb 100644
> > --- a/drivers/gpu/drm/i915/intel_ddi.c
> > +++ b/drivers/gpu/drm/i915/intel_ddi.c
> > @@ -3311,6 +3311,56 @@ static void bxt_ddi_pre_pll_enable(struct
> > intel_encoder *encoder,
> > bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
> > }
> >
> > +static void intel_ddi_set_fia_lane_count(struct intel_encoder
> > *encoder,
> > + const struct intel_crtc_state
> > *pipe_config,
> > + enum port port)
> > +{
> > + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> > + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> > >base);
> > + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> > + u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
> > + bool lane_reversal = (dig_port->tc_type == TC_PORT_TYPEC) ?
> > false :
> > + dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
>
> I guess this is more easy to read:
> bool lane_reversal = dig_port->tc_type == TC_PORT_TYPEC && dig_port-
> >saved_port_bits & DDI_BUF_PORT_REVERSAL;
Actually this will not work for TC_PORT_LEGACY since the first condition dig_port->tc_type == TC_PORT_TYPEC will
be false and it will set lane_reversal to false irrespective of DDI_BUF_PORT_REVERSAL because of the &&
>
> > +
> > + val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> > + switch (pipe_config->lane_count) {
> > + case 1:
> > + val |= (lane_reversal) ?
> > DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
> > + DFLEXDPMLE1_DPMLETC_ML0(tc_port);
>
> For me the DFLEXDPMLE1_DPMLETC_ML0(tc_port); should be align with '('
> but if bot said that it is okay...
Ok will check the alignment one more time.
>
> > + break;
> > + case 2:
> > + val |= (lane_reversal) ?
> > DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
> > + DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
> > + break;
> > + case 4:
> > + val |= DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port);
> > + break;
> > + default:
> > + MISSING_CASE(pipe_config->lane_count);
> > + }
> > + I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
> > +}
> > +
> > +static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
> > + const struct intel_crtc_state
> > *pipe_config,
> > + const struct drm_connector_state
> > *conn_state)
> > +{
> > + enum port port = encoder->port;
> > + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder-
> > >base);
> > +
> > + if (intel_port_is_combophy(to_i915(encoder->base.dev), port))
> > + return;
>
> Combophy ports will have dig_port->tc_type == TC_PORT_UNKNOWN so you
> can drop this.
Ok will do.
Manasi
>
> With this change:
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
>
> > +
> > + /*
> > + * Program the lane count for static/dynamic connections on
> > Type-C ports.
> > + * Skip this step for TBT.
> > + */
> > + if (dig_port->tc_type == TC_PORT_TBT)
> > + return;
> > +
> > + intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
> > +}
> > +
> > void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> > {
> > struct intel_digital_port *intel_dig_port =
> > dp_to_dig_port(intel_dp);
> > @@ -3828,6 +3878,8 @@ void intel_ddi_init(struct drm_i915_private
> > *dev_priv, enum port port)
> > intel_encoder->enable = intel_enable_ddi;
> > if (IS_GEN9_LP(dev_priv))
> > intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> > + if (IS_ICELAKE(dev_priv))
> > + intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
> > intel_encoder->pre_enable = intel_ddi_pre_enable;
> > intel_encoder->disable = intel_disable_ddi;
> > intel_encoder->post_disable = intel_ddi_post_disable;
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^ permalink raw reply [flat|nested] 9+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
2018-10-18 22:16 [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
2018-10-18 22:16 ` [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook Manasi Navare
@ 2018-10-18 22:41 ` Patchwork
2018-10-19 21:33 ` [PATCH 1/2] " Srivatsa, Anusha
` (2 subsequent siblings)
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-10-18 22:41 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
URL : https://patchwork.freedesktop.org/series/51223/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5011 -> Patchwork_10509 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51223/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10509 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
fi-skl-6700hq: NOTRUN -> INCOMPLETE (fdo#104108)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
igt@prime_vgem@basic-fence-flip:
fi-skl-iommu: PASS -> FAIL (fdo#104008)
==== Possible fixes ====
igt@drv_getparams_basic@basic-subslice-total:
fi-snb-2520m: DMESG-WARN (fdo#103713) -> PASS +10
igt@kms_frontbuffer_tracking@basic:
fi-skl-6700hq: INCOMPLETE -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-b:
fi-byt-clapper: FAIL (fdo#107362) -> PASS +1
igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
fi-cfl-8109u: INCOMPLETE (fdo#108126, fdo#106070) -> PASS
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103713 https://bugs.freedesktop.org/show_bug.cgi?id=103713
fdo#104008 https://bugs.freedesktop.org/show_bug.cgi?id=104008
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#106070 https://bugs.freedesktop.org/show_bug.cgi?id=106070
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#108126 https://bugs.freedesktop.org/show_bug.cgi?id=108126
== Participating hosts (42 -> 39) ==
Missing (3): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan
== Build changes ==
* Linux: CI_DRM_5011 -> Patchwork_10509
CI_DRM_5011: f66154472620fdd1f364c577ade311ce2b9d445a @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4684: 6f27fddc6dd79c0486181b64201c6773c5c42a24 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10509: 8ec3cf254b07e1de25c03d95e4d0fb66ae9b9e51 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
8ec3cf254b07 drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
6156fe12e5ca drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10509/issues.html
_______________________________________________
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^ permalink raw reply [flat|nested] 9+ messages in thread* Re: [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
2018-10-18 22:16 [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
2018-10-18 22:16 ` [PATCH 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook Manasi Navare
2018-10-18 22:41 ` ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Patchwork
@ 2018-10-19 21:33 ` Srivatsa, Anusha
2018-10-22 19:05 ` Manasi Navare
2018-10-20 0:48 ` Souza, Jose
2018-10-22 14:59 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits (rev2) Patchwork
4 siblings, 1 reply; 9+ messages in thread
From: Srivatsa, Anusha @ 2018-10-19 21:33 UTC (permalink / raw)
To: Navare, Manasi D, intel-gfx@lists.freedesktop.org; +Cc: Zanoni, Paulo R
________________________________________
From: Intel-gfx [intel-gfx-bounces@lists.freedesktop.org] on behalf of Manasi Navare [manasi.d.navare@intel.com]
Sent: Thursday, October 18, 2018 3:16 PM
To: intel-gfx@lists.freedesktop.org
Cc: Zanoni, Paulo R
Subject: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
This patch fixes the macros used for defining the DFLEXDPMLE
register bit fields. This accounts for changes in the spec.
Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
---
drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 81f1c601987d..f5f8a39c4116 100644
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -2057,8 +2057,12 @@ enum i915_power_well_id {
/* ICL PHY DFLEX registers */
#define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
-#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
-#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
+#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
+#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
+#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
+#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
+#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port))
Wont ML0, 1_0, 3, 3_2 suffice?
Anusha
+#define DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port) (15 << (4 * (tc_port)))
/* BXT PHY Ref registers */
#define _PORT_REF_DW3_A 0x16218C
--
2.18.0
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^ permalink raw reply related [flat|nested] 9+ messages in thread* Re: [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
2018-10-19 21:33 ` [PATCH 1/2] " Srivatsa, Anusha
@ 2018-10-22 19:05 ` Manasi Navare
0 siblings, 0 replies; 9+ messages in thread
From: Manasi Navare @ 2018-10-22 19:05 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx@lists.freedesktop.org, Zanoni, Paulo R
On Fri, Oct 19, 2018 at 02:33:35PM -0700, Srivatsa, Anusha wrote:
>
> ________________________________________
> From: Intel-gfx [intel-gfx-bounces@lists.freedesktop.org] on behalf of Manasi Navare [manasi.d.navare@intel.com]
> Sent: Thursday, October 18, 2018 3:16 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Zanoni, Paulo R
> Subject: [Intel-gfx] [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
>
> This patch fixes the macros used for defining the DFLEXDPMLE
> register bit fields. This accounts for changes in the spec.
>
> Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 81f1c601987d..f5f8a39c4116 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,12 @@ enum i915_power_well_id {
>
> /* ICL PHY DFLEX registers */
> #define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> -#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> -#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
> +#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port))
>
> Wont ML0, 1_0, 3, 3_2 suffice?
>
> Anusha
> +#define DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port) (15 << (4 * (tc_port)))
For setting all 4 bits for 4 lanes, we would need ML_3_0. We could do
1_0 | 3_2 but then to keep it consistent with the Spec tables, its better
to have a separate macro for ML3_0.
One of the changes I will do here is rename it as ML3_0, instead of ML_3_0
to keep it consistent with other ML macros.
Manasi
>
> /* BXT PHY Ref registers */
> #define _PORT_REF_DW3_A 0x16218C
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
>
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^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
2018-10-18 22:16 [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
` (2 preceding siblings ...)
2018-10-19 21:33 ` [PATCH 1/2] " Srivatsa, Anusha
@ 2018-10-20 0:48 ` Souza, Jose
2018-10-22 14:59 ` ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits (rev2) Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Souza, Jose @ 2018-10-20 0:48 UTC (permalink / raw)
To: intel-gfx@lists.freedesktop.org, Navare, Manasi D; +Cc: Zanoni, Paulo R
On Thu, 2018-10-18 at 15:16 -0700, Manasi Navare wrote:
> This patch fixes the macros used for defining the DFLEXDPMLE
> register bit fields. This accounts for changes in the spec.
>
> Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for
> DFLEXDPMLE")
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h
> b/drivers/gpu/drm/i915/i915_reg.h
> index 81f1c601987d..f5f8a39c4116 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,12 @@ enum i915_power_well_id {
>
> /* ICL PHY DFLEX registers */
> #define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> -#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> -#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
> +#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 *
> (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML_3_0(tc_port) (15 << (4 *
> (tc_port)))
>
> /* BXT PHY Ref registers */
> #define _PORT_REF_DW3_A 0x16218C
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^ permalink raw reply [flat|nested] 9+ messages in thread* ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits (rev2)
2018-10-18 22:16 [PATCH 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
` (3 preceding siblings ...)
2018-10-20 0:48 ` Souza, Jose
@ 2018-10-22 14:59 ` Patchwork
4 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2018-10-22 14:59 UTC (permalink / raw)
To: Srivatsa, Anusha; +Cc: intel-gfx
== Series Details ==
Series: series starting with [1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits (rev2)
URL : https://patchwork.freedesktop.org/series/51223/
State : failure
== Summary ==
Applying: drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
error: corrupt patch at line 17
error: could not build fake ancestor
Patch failed at 0001 drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
Use 'git am --show-current-patch' to see the failed patch
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
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^ permalink raw reply [flat|nested] 9+ messages in thread