* [PATCH v2 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
2018-10-23 19:12 [PATCH v2 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
@ 2018-10-23 19:12 ` Manasi Navare
2018-10-31 18:40 ` Imre Deak
2018-10-31 23:37 ` Manasi Navare
2018-10-23 19:47 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Patchwork
` (2 subsequent siblings)
3 siblings, 2 replies; 7+ messages in thread
From: Manasi Navare @ 2018-10-23 19:12 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Paulo Zanoni
In case of Legacy DP connector on TypeC port, the
flex IO DPMLE register is set to number of lanes configured
by the display driver which will be programmed into DDI_BUF_CTL
PORT_WIDTH_SELECTION.
This needs to be programmed before enabling the shared PLLs hence
add a pre_pll_enable hook for ICL and add this programming in that hook.
v2:
* Remove the check for combophy port (Jose)
* Simplify the port reversal check logic (Jose)
Cc: Lucas De Marchi <lucas.demarchi@intel.com>
Cc: Jose Roberto de Souza <jose.souza@intel.com>
Cc: Animesh Manna <animesh.manna@intel.com>
Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
---
drivers/gpu/drm/i915/intel_ddi.c | 49 ++++++++++++++++++++++++++++++++
1 file changed, 49 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
index 6b9742baa5f2..246424605768 100644
--- a/drivers/gpu/drm/i915/intel_ddi.c
+++ b/drivers/gpu/drm/i915/intel_ddi.c
@@ -3311,6 +3311,53 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
}
+static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ enum port port)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+ enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
+ u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
+ bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
+
+ val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
+ switch (pipe_config->lane_count) {
+ case 1:
+ val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
+ DFLEXDPMLE1_DPMLETC_ML0(tc_port);
+ break;
+ case 2:
+ val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
+ DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
+ break;
+ case 4:
+ val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
+ break;
+ default:
+ MISSING_CASE(pipe_config->lane_count);
+ }
+ I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
+}
+
+static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
+ const struct intel_crtc_state *pipe_config,
+ const struct drm_connector_state *conn_state)
+{
+ enum port port = encoder->port;
+ struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+ /*
+ * Program the lane count for static/dynamic connections on Type-C ports.
+ * Skip this step for TBT.
+ */
+ if (dig_port->tc_type == TC_PORT_UNKNOWN ||
+ dig_port->tc_type == TC_PORT_TBT)
+ return;
+
+ intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
+}
+
void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
{
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
@@ -3828,6 +3875,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
intel_encoder->enable = intel_enable_ddi;
if (IS_GEN9_LP(dev_priv))
intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
+ if (IS_ICELAKE(dev_priv))
+ intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
intel_encoder->pre_enable = intel_ddi_pre_enable;
intel_encoder->disable = intel_disable_ddi;
intel_encoder->post_disable = intel_ddi_post_disable;
--
2.18.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
2018-10-23 19:12 ` [PATCH v2 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook Manasi Navare
@ 2018-10-31 18:40 ` Imre Deak
2018-10-31 23:37 ` Manasi Navare
1 sibling, 0 replies; 7+ messages in thread
From: Imre Deak @ 2018-10-31 18:40 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx, Lucas De Marchi, Paulo Zanoni
On Tue, Oct 23, 2018 at 12:12:48PM -0700, Manasi Navare wrote:
> In case of Legacy DP connector on TypeC port, the
> flex IO DPMLE register is set to number of lanes configured
> by the display driver which will be programmed into DDI_BUF_CTL
> PORT_WIDTH_SELECTION.
> This needs to be programmed before enabling the shared PLLs hence
> add a pre_pll_enable hook for ICL and add this programming in that hook.
>
> v2:
> * Remove the check for combophy port (Jose)
> * Simplify the port reversal check logic (Jose)
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Looks ok:
Acked-by: Imre Deak <imre.deak@intel.com>
Manasi, are you going to merge this? I could rebase my patchset after
that.
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 49 ++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6b9742baa5f2..246424605768 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3311,6 +3311,53 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
> bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
> }
>
> +static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config,
> + enum port port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> +
> + val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> + switch (pipe_config->lane_count) {
> + case 1:
> + val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
> + DFLEXDPMLE1_DPMLETC_ML0(tc_port);
> + break;
> + case 2:
> + val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
> + DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
> + break;
> + case 4:
> + val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
> + break;
> + default:
> + MISSING_CASE(pipe_config->lane_count);
> + }
> + I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
> +}
> +
> +static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config,
> + const struct drm_connector_state *conn_state)
> +{
> + enum port port = encoder->port;
> + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> +
> + /*
> + * Program the lane count for static/dynamic connections on Type-C ports.
> + * Skip this step for TBT.
> + */
> + if (dig_port->tc_type == TC_PORT_UNKNOWN ||
> + dig_port->tc_type == TC_PORT_TBT)
> + return;
> +
> + intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
> +}
> +
> void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> @@ -3828,6 +3875,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> intel_encoder->enable = intel_enable_ddi;
> if (IS_GEN9_LP(dev_priv))
> intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> + if (IS_ICELAKE(dev_priv))
> + intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
> intel_encoder->pre_enable = intel_ddi_pre_enable;
> intel_encoder->disable = intel_disable_ddi;
> intel_encoder->post_disable = intel_ddi_post_disable;
> --
> 2.18.0
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
2018-10-23 19:12 ` [PATCH v2 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook Manasi Navare
2018-10-31 18:40 ` Imre Deak
@ 2018-10-31 23:37 ` Manasi Navare
1 sibling, 0 replies; 7+ messages in thread
From: Manasi Navare @ 2018-10-31 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Lucas De Marchi, Paulo Zanoni
Pushed to dinq, thanks for the patch and reviews
Manasi
On Tue, Oct 23, 2018 at 12:12:48PM -0700, Manasi Navare wrote:
> In case of Legacy DP connector on TypeC port, the
> flex IO DPMLE register is set to number of lanes configured
> by the display driver which will be programmed into DDI_BUF_CTL
> PORT_WIDTH_SELECTION.
> This needs to be programmed before enabling the shared PLLs hence
> add a pre_pll_enable hook for ICL and add this programming in that hook.
>
> v2:
> * Remove the check for combophy port (Jose)
> * Simplify the port reversal check logic (Jose)
>
> Cc: Lucas De Marchi <lucas.demarchi@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/intel_ddi.c | 49 ++++++++++++++++++++++++++++++++
> 1 file changed, 49 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_ddi.c b/drivers/gpu/drm/i915/intel_ddi.c
> index 6b9742baa5f2..246424605768 100644
> --- a/drivers/gpu/drm/i915/intel_ddi.c
> +++ b/drivers/gpu/drm/i915/intel_ddi.c
> @@ -3311,6 +3311,53 @@ static void bxt_ddi_pre_pll_enable(struct intel_encoder *encoder,
> bxt_ddi_phy_set_lane_optim_mask(encoder, mask);
> }
>
> +static void intel_ddi_set_fia_lane_count(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config,
> + enum port port)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> + enum tc_port tc_port = intel_port_to_tc(dev_priv, port);
> + u32 val = I915_READ(PORT_TX_DFLEXDPMLE1);
> + bool lane_reversal = dig_port->saved_port_bits & DDI_BUF_PORT_REVERSAL;
> +
> + val &= ~DFLEXDPMLE1_DPMLETC_MASK(tc_port);
> + switch (pipe_config->lane_count) {
> + case 1:
> + val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3(tc_port) :
> + DFLEXDPMLE1_DPMLETC_ML0(tc_port);
> + break;
> + case 2:
> + val |= (lane_reversal) ? DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) :
> + DFLEXDPMLE1_DPMLETC_ML1_0(tc_port);
> + break;
> + case 4:
> + val |= DFLEXDPMLE1_DPMLETC_ML3_0(tc_port);
> + break;
> + default:
> + MISSING_CASE(pipe_config->lane_count);
> + }
> + I915_WRITE(PORT_TX_DFLEXDPMLE1, val);
> +}
> +
> +static void icl_ddi_pre_pll_enable(struct intel_encoder *encoder,
> + const struct intel_crtc_state *pipe_config,
> + const struct drm_connector_state *conn_state)
> +{
> + enum port port = encoder->port;
> + struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
> +
> + /*
> + * Program the lane count for static/dynamic connections on Type-C ports.
> + * Skip this step for TBT.
> + */
> + if (dig_port->tc_type == TC_PORT_UNKNOWN ||
> + dig_port->tc_type == TC_PORT_TBT)
> + return;
> +
> + intel_ddi_set_fia_lane_count(encoder, pipe_config, port);
> +}
> +
> void intel_ddi_prepare_link_retrain(struct intel_dp *intel_dp)
> {
> struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
> @@ -3828,6 +3875,8 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
> intel_encoder->enable = intel_enable_ddi;
> if (IS_GEN9_LP(dev_priv))
> intel_encoder->pre_pll_enable = bxt_ddi_pre_pll_enable;
> + if (IS_ICELAKE(dev_priv))
> + intel_encoder->pre_pll_enable = icl_ddi_pre_pll_enable;
> intel_encoder->pre_enable = intel_ddi_pre_enable;
> intel_encoder->disable = intel_disable_ddi;
> intel_encoder->post_disable = intel_ddi_post_disable;
> --
> 2.18.0
>
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread
* ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
2018-10-23 19:12 [PATCH v2 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
2018-10-23 19:12 ` [PATCH v2 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook Manasi Navare
@ 2018-10-23 19:47 ` Patchwork
2018-10-23 23:08 ` ✓ Fi.CI.IGT: " Patchwork
2018-10-31 23:37 ` [PATCH v2 1/2] " Manasi Navare
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-10-23 19:47 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
URL : https://patchwork.freedesktop.org/series/51402/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023 -> Patchwork_10551 =
== Summary - SUCCESS ==
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/51402/revisions/1/mbox/
== Known issues ==
Here are the changes found in Patchwork_10551 that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@drv_selftest@live_contexts:
fi-icl-u: NOTRUN -> INCOMPLETE (fdo#106702)
igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a-frame-sequence:
fi-byt-clapper: PASS -> FAIL (fdo#107362, fdo#103191)
==== Possible fixes ====
igt@gem_ctx_switch@basic-default:
fi-icl-u: DMESG-FAIL -> PASS
igt@gem_exec_suspend@basic-s3:
fi-blb-e6850: INCOMPLETE (fdo#107718) -> PASS
igt@kms_pipe_crc_basic@read-crc-pipe-a:
fi-byt-clapper: FAIL (fdo#107362) -> PASS
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#106702 https://bugs.freedesktop.org/show_bug.cgi?id=106702
fdo#107362 https://bugs.freedesktop.org/show_bug.cgi?id=107362
fdo#107718 https://bugs.freedesktop.org/show_bug.cgi?id=107718
== Participating hosts (49 -> 44) ==
Additional (1): fi-kbl-7560u
Missing (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-apl-guc fi-ctg-p8600
== Build changes ==
* Linux: CI_DRM_5023 -> Patchwork_10551
CI_DRM_5023: 166bc98d7b77005943ab670506f164783cdc3f56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4688: fa6dbf8c048961356fd642df047cb58ab49309b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10551: 3067c0c9d032baa888fac49b66bafc2a5822c609 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3067c0c9d032 drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook
ea229a56b834 drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10551/issues.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 7+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [v2,1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
2018-10-23 19:12 [PATCH v2 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
2018-10-23 19:12 ` [PATCH v2 2/2] drm/i915/ICL: Add pre_pll_enable hook for ICL and set DFLEXDPMLE in this hook Manasi Navare
2018-10-23 19:47 ` ✓ Fi.CI.BAT: success for series starting with [v2,1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Patchwork
@ 2018-10-23 23:08 ` Patchwork
2018-10-31 23:37 ` [PATCH v2 1/2] " Manasi Navare
3 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2018-10-23 23:08 UTC (permalink / raw)
To: Manasi Navare; +Cc: intel-gfx
== Series Details ==
Series: series starting with [v2,1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
URL : https://patchwork.freedesktop.org/series/51402/
State : success
== Summary ==
= CI Bug Log - changes from CI_DRM_5023_full -> Patchwork_10551_full =
== Summary - WARNING ==
Minor unknown changes coming with Patchwork_10551_full need to be verified
manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_10551_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
== Possible new issues ==
Here are the unknown changes that may have been introduced in Patchwork_10551_full:
=== IGT changes ===
==== Warnings ====
igt@pm_rc6_residency@rc6-accuracy:
shard-snb: PASS -> SKIP
== Known issues ==
Here are the changes found in Patchwork_10551_full that come from known issues:
=== IGT changes ===
==== Issues hit ====
igt@gem_exec_await@wide-contexts:
shard-apl: PASS -> FAIL (fdo#106680)
igt@gem_render_copy@linear:
shard-kbl: PASS -> INCOMPLETE (fdo#103665)
igt@kms_busy@extended-pageflip-hang-newfb-render-b:
shard-apl: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_busy@extended-pageflip-modeset-hang-oldfb-render-b:
shard-snb: NOTRUN -> DMESG-WARN (fdo#107956)
igt@kms_color@pipe-b-degamma:
shard-apl: PASS -> FAIL (fdo#104782)
igt@kms_cursor_crc@cursor-128x128-suspend:
shard-apl: PASS -> FAIL (fdo#103232, fdo#103191)
igt@kms_cursor_crc@cursor-256x85-onscreen:
shard-glk: PASS -> FAIL (fdo#103232) +2
igt@kms_cursor_crc@cursor-256x85-random:
shard-apl: PASS -> FAIL (fdo#103232) +3
igt@kms_flip_tiling@flip-changes-tiling:
shard-kbl: PASS -> DMESG-WARN (fdo#103313, fdo#105345)
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-onoff:
shard-apl: PASS -> FAIL (fdo#103167)
igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
shard-glk: PASS -> FAIL (fdo#103167) +4
igt@kms_frontbuffer_tracking@psr-suspend:
shard-skl: PASS -> INCOMPLETE (fdo#106978, fdo#104108)
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-glk: PASS -> FAIL (fdo#103166) +2
igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max:
shard-glk: PASS -> FAIL (fdo#108145)
igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
shard-apl: PASS -> FAIL (fdo#108145)
igt@kms_setmode@basic:
shard-apl: PASS -> FAIL (fdo#99912)
shard-snb: NOTRUN -> FAIL (fdo#99912)
==== Possible fixes ====
igt@kms_ccs@pipe-a-crc-sprite-planes-basic:
shard-glk: FAIL (fdo#108145) -> PASS +1
igt@kms_cursor_crc@cursor-256x256-sliding:
shard-glk: FAIL (fdo#103232) -> PASS +1
igt@kms_cursor_crc@cursor-64x21-offscreen:
shard-skl: FAIL (fdo#103232) -> PASS
igt@kms_cursor_crc@cursor-size-change:
shard-apl: FAIL (fdo#103232) -> PASS
igt@kms_cursor_legacy@cursora-vs-flipa-toggle:
shard-glk: DMESG-WARN (fdo#106538, fdo#105763) -> PASS +1
igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-xtiled:
shard-skl: FAIL (fdo#103184) -> PASS
igt@kms_flip@busy-flip-interruptible:
shard-skl: FAIL (fdo#103257) -> PASS
igt@kms_flip@flip-vs-expired-vblank-interruptible:
shard-skl: FAIL (fdo#105363) -> PASS
igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-pwrite:
shard-glk: FAIL (fdo#103167) -> PASS
igt@kms_frontbuffer_tracking@psr-rgb101010-draw-mmap-cpu:
shard-skl: FAIL (fdo#103167) -> PASS +1
igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
shard-skl: INCOMPLETE (fdo#104108, fdo#107773) -> PASS
igt@kms_plane@plane-position-covered-pipe-a-planes:
shard-apl: FAIL (fdo#103166) -> PASS
igt@kms_rotation_crc@sprite-rotation-180:
shard-apl: INCOMPLETE (fdo#103927) -> PASS
igt@perf@short-reads:
shard-skl: FAIL (fdo#103183) -> PASS
igt@pm_rpm@legacy-planes-dpms:
shard-skl: INCOMPLETE (fdo#107807, fdo#105959) -> PASS
fdo#103166 https://bugs.freedesktop.org/show_bug.cgi?id=103166
fdo#103167 https://bugs.freedesktop.org/show_bug.cgi?id=103167
fdo#103183 https://bugs.freedesktop.org/show_bug.cgi?id=103183
fdo#103184 https://bugs.freedesktop.org/show_bug.cgi?id=103184
fdo#103191 https://bugs.freedesktop.org/show_bug.cgi?id=103191
fdo#103232 https://bugs.freedesktop.org/show_bug.cgi?id=103232
fdo#103257 https://bugs.freedesktop.org/show_bug.cgi?id=103257
fdo#103313 https://bugs.freedesktop.org/show_bug.cgi?id=103313
fdo#103665 https://bugs.freedesktop.org/show_bug.cgi?id=103665
fdo#103927 https://bugs.freedesktop.org/show_bug.cgi?id=103927
fdo#104108 https://bugs.freedesktop.org/show_bug.cgi?id=104108
fdo#104782 https://bugs.freedesktop.org/show_bug.cgi?id=104782
fdo#105345 https://bugs.freedesktop.org/show_bug.cgi?id=105345
fdo#105363 https://bugs.freedesktop.org/show_bug.cgi?id=105363
fdo#105763 https://bugs.freedesktop.org/show_bug.cgi?id=105763
fdo#105959 https://bugs.freedesktop.org/show_bug.cgi?id=105959
fdo#106538 https://bugs.freedesktop.org/show_bug.cgi?id=106538
fdo#106680 https://bugs.freedesktop.org/show_bug.cgi?id=106680
fdo#106978 https://bugs.freedesktop.org/show_bug.cgi?id=106978
fdo#107773 https://bugs.freedesktop.org/show_bug.cgi?id=107773
fdo#107807 https://bugs.freedesktop.org/show_bug.cgi?id=107807
fdo#107956 https://bugs.freedesktop.org/show_bug.cgi?id=107956
fdo#108145 https://bugs.freedesktop.org/show_bug.cgi?id=108145
fdo#99912 https://bugs.freedesktop.org/show_bug.cgi?id=99912
== Participating hosts (6 -> 6) ==
No changes in participating hosts
== Build changes ==
* Linux: CI_DRM_5023 -> Patchwork_10551
CI_DRM_5023: 166bc98d7b77005943ab670506f164783cdc3f56 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4688: fa6dbf8c048961356fd642df047cb58ab49309b2 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_10551: 3067c0c9d032baa888fac49b66bafc2a5822c609 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_10551/shards.html
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^ permalink raw reply [flat|nested] 7+ messages in thread* Re: [PATCH v2 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits
2018-10-23 19:12 [PATCH v2 1/2] drm/i915/icl: Fix the macros for DFLEXDPMLE register bits Manasi Navare
` (2 preceding siblings ...)
2018-10-23 23:08 ` ✓ Fi.CI.IGT: " Patchwork
@ 2018-10-31 23:37 ` Manasi Navare
3 siblings, 0 replies; 7+ messages in thread
From: Manasi Navare @ 2018-10-31 23:37 UTC (permalink / raw)
To: intel-gfx; +Cc: Paulo Zanoni
Pushed to dinq,thanks for the patch and reviews.
Manasi
On Tue, Oct 23, 2018 at 12:12:47PM -0700, Manasi Navare wrote:
> This patch fixes the macros used for defining the DFLEXDPMLE
> register bit fields. This accounts for changes in the spec.
>
> Fixes: a2bc69a1a9d6 ("drm/i915/icl: Add register definition for DFLEXDPMLE")
> Cc: Animesh Manna <animesh.manna@intel.com>
> Cc: Paulo Zanoni <paulo.r.zanoni@intel.com>
> Cc: Jose Roberto de Souza <jose.souza@intel.com>
> Signed-off-by: Manasi Navare <manasi.d.navare@intel.com>
> Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
> ---
> drivers/gpu/drm/i915/i915_reg.h | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
> index 8bd61f946714..9da489b176c9 100644
> --- a/drivers/gpu/drm/i915/i915_reg.h
> +++ b/drivers/gpu/drm/i915/i915_reg.h
> @@ -2057,8 +2057,12 @@ enum i915_power_well_id {
>
> /* ICL PHY DFLEX registers */
> #define PORT_TX_DFLEXDPMLE1 _MMIO(0x1638C0)
> -#define DFLEXDPMLE1_DPMLETC_MASK(n) (0xf << (4 * (n)))
> -#define DFLEXDPMLE1_DPMLETC(n, x) ((x) << (4 * (n)))
> +#define DFLEXDPMLE1_DPMLETC_MASK(tc_port) (0xf << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML0(tc_port) (1 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML1_0(tc_port) (3 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML3(tc_port) (8 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML3_2(tc_port) (12 << (4 * (tc_port)))
> +#define DFLEXDPMLE1_DPMLETC_ML3_0(tc_port) (15 << (4 * (tc_port)))
>
> /* BXT PHY Ref registers */
> #define _PORT_REF_DW3_A 0x16218C
> --
> 2.18.0
>
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^ permalink raw reply [flat|nested] 7+ messages in thread