* [PATCH 0/5] Enable BACO function on VG20
@ 2019-01-11 3:19 Jim Qu
[not found] ` <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org>
0 siblings, 1 reply; 6+ messages in thread
From: Jim Qu @ 2019-01-11 3:19 UTC (permalink / raw)
To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jim Qu
Jim Qu (5):
drm/amdgpu: update NBIO v7.4 to support BACO
drm/amdgpu: also include NBIO v7.4 register mask header
drm/amdgpu: update THM IP register header to support BACO
drm/amdgpu/powerper: add vega20 BACO functins
drm/amdgpu: use BACO reset on vega20 if platform support
drivers/gpu/drm/amd/amdgpu/soc15.c | 1 +
.../include/asic_reg/nbio/nbio_7_4_offset.h | 2 +
.../include/asic_reg/nbio/nbio_7_4_sh_mask.h | 3 +
.../include/asic_reg/thm/thm_11_0_2_offset.h | 3 +
drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +-
.../gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 81 +++++++++++++++++++
.../gpu/drm/amd/powerplay/hwmgr/vega20_baco.h | 34 ++++++++
.../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 5 ++
.../gpu/drm/amd/powerplay/hwmgr/vega20_inc.h | 1 +
9 files changed, 131 insertions(+), 1 deletion(-)
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c
create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h
--
2.17.1
_______________________________________________
amd-gfx mailing list
amd-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/amd-gfx
^ permalink raw reply [flat|nested] 6+ messages in thread[parent not found: <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org>]
* [PATCH 1/5] drm/amdgpu: update NBIO v7.4 to support BACO [not found] ` <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org> @ 2019-01-11 3:19 ` Jim Qu 2019-01-11 3:19 ` [PATCH 2/5] drm/amdgpu: also include NBIO v7.4 register mask header Jim Qu ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Jim Qu @ 2019-01-11 3:19 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jim Qu Change-Id: Ie2ecdb78114e4c319aba33fdc68713047417bc7b Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> --- drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h | 2 ++ drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h | 3 +++ 2 files changed, 5 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h index e932213f87f0..994e796a28d7 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_offset.h @@ -2567,6 +2567,8 @@ // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 // base address: 0x0 +#define mmRCC_BIF_STRAP0 0x0000 +#define mmRCC_BIF_STRAP0_BASE_IDX 2 #define mmRCC_DEV0_EPF0_STRAP0 0x0011 #define mmRCC_DEV0_EPF0_STRAP0_BASE_IDX 2 diff --git a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h index d3704b438f2d..d467b939c971 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h +++ b/drivers/gpu/drm/amd/include/asic_reg/nbio/nbio_7_4_sh_mask.h @@ -19690,6 +19690,9 @@ // addressBlock: nbio_nbif0_rcc_strap_BIFDEC1 +//RCC_BIF_STRAP0 +#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE__SHIFT 0x7 +#define RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK 0x00000080L //RCC_DEV0_EPF0_STRAP0 #define RCC_DEV0_EPF0_STRAP0__STRAP_DEVICE_ID_DEV0_F0__SHIFT 0x0 #define RCC_DEV0_EPF0_STRAP0__STRAP_MAJOR_REV_ID_DEV0_F0__SHIFT 0x10 -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 2/5] drm/amdgpu: also include NBIO v7.4 register mask header [not found] ` <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org> 2019-01-11 3:19 ` [PATCH 1/5] drm/amdgpu: update NBIO v7.4 to support BACO Jim Qu @ 2019-01-11 3:19 ` Jim Qu 2019-01-11 3:19 ` [PATCH 3/5] drm/amdgpu: update THM IP register header to support BACO Jim Qu ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Jim Qu @ 2019-01-11 3:19 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jim Qu Change-Id: Ib5f3afa6c2da4733e39373ce2a950b6ec63ccdff Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h index 6738bad53602..613cb1989b3d 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_inc.h @@ -31,5 +31,6 @@ #include "asic_reg/mp/mp_9_0_sh_mask.h" #include "asic_reg/nbio/nbio_7_4_offset.h" +#include "asic_reg/nbio/nbio_7_4_sh_mask.h" #endif -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 3/5] drm/amdgpu: update THM IP register header to support BACO [not found] ` <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org> 2019-01-11 3:19 ` [PATCH 1/5] drm/amdgpu: update NBIO v7.4 to support BACO Jim Qu 2019-01-11 3:19 ` [PATCH 2/5] drm/amdgpu: also include NBIO v7.4 register mask header Jim Qu @ 2019-01-11 3:19 ` Jim Qu 2019-01-11 3:19 ` [PATCH 4/5] drm/amdgpu/powerper: add vega20 BACO functins Jim Qu 2019-01-11 3:19 ` [PATCH 5/5] drm/amdgpu: use BACO reset on vega20 if platform support Jim Qu 4 siblings, 0 replies; 6+ messages in thread From: Jim Qu @ 2019-01-11 3:19 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jim Qu Change-Id: I484ba66c2e6f20123e6004cb6671e6a6ee6cf27b Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> --- drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h index a9eb57a53e59..a485526f3a51 100644 --- a/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h +++ b/drivers/gpu/drm/amd/include/asic_reg/thm/thm_11_0_2_offset.h @@ -46,4 +46,7 @@ #define mmTHM_TCON_THERM_TRIP 0x0002 #define mmTHM_TCON_THERM_TRIP_BASE_IDX 0 +#define mmTHM_BACO_CNTL 0x0081 +#define mmTHM_BACO_CNTL_BASE_IDX 0 + #endif -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 4/5] drm/amdgpu/powerper: add vega20 BACO functins [not found] ` <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org> ` (2 preceding siblings ...) 2019-01-11 3:19 ` [PATCH 3/5] drm/amdgpu: update THM IP register header to support BACO Jim Qu @ 2019-01-11 3:19 ` Jim Qu 2019-01-11 3:19 ` [PATCH 5/5] drm/amdgpu: use BACO reset on vega20 if platform support Jim Qu 4 siblings, 0 replies; 6+ messages in thread From: Jim Qu @ 2019-01-11 3:19 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jim Qu Change-Id: I1e55db9e508f96353b1b2e6aa153e05962b9e7fe Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> --- drivers/gpu/drm/amd/powerplay/hwmgr/Makefile | 2 +- .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.c | 81 +++++++++++++++++++ .../gpu/drm/amd/powerplay/hwmgr/vega20_baco.h | 34 ++++++++ .../drm/amd/powerplay/hwmgr/vega20_hwmgr.c | 5 ++ 4 files changed, 121 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c create mode 100644 drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile index e563811b2ebe..0b3c6d1d52e4 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/Makefile @@ -35,7 +35,7 @@ HARDWARE_MGR = hwmgr.o processpptables.o \ vega12_thermal.o \ pp_overdriver.o smu_helper.o \ vega20_processpptables.o vega20_hwmgr.o vega20_powertune.o \ - vega20_thermal.o common_baco.o vega10_baco.o + vega20_thermal.o common_baco.o vega10_baco.o vega20_baco.o AMD_PP_HWMGR = $(addprefix $(AMD_PP_PATH)/hwmgr/,$(HARDWARE_MGR)) diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c new file mode 100644 index 000000000000..0d883b358df2 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.c @@ -0,0 +1,81 @@ +#include "amdgpu.h" +#include "soc15.h" +#include "soc15_hw_ip.h" +#include "soc15_common.h" +#include "vega20_inc.h" +#include "vega20_ppsmc.h" +#include "vega20_baco.h" + + + +static const struct soc15_baco_cmd_entry clean_baco_tbl[] = +{ + {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_6), 0, 0, 0, 0}, + {CMD_WRITE, SOC15_REG_ENTRY(NBIF, 0, mmBIOS_SCRATCH_7), 0, 0, 0, 0}, +}; + +int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); + uint32_t reg; + + *cap = false; + if (!phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_BACO)) + return 0; + + if (((RREG32(0x17569) & 0x20000000) >> 29) == 0x1) { + reg = RREG32_SOC15(NBIF, 0, mmRCC_BIF_STRAP0); + + if (reg & RCC_BIF_STRAP0__STRAP_PX_CAPABLE_MASK) + *cap = true; + } + + return 0; +} + +int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); + uint32_t reg; + + reg = RREG32_SOC15(NBIF, 0, mmBACO_CNTL); + + if (reg & BACO_CNTL__BACO_MODE_MASK) + /* gfx has already entered BACO state */ + *state = BACO_STATE_IN; + else + *state = BACO_STATE_OUT; + return 0; +} + +int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state) +{ + struct amdgpu_device *adev = (struct amdgpu_device *)(hwmgr->adev); + enum BACO_STATE cur_state; + uint32_t data; + + vega20_baco_get_state(hwmgr, &cur_state); + + if (cur_state == state) + /* aisc already in the target state */ + return 0; + + if (state == BACO_STATE_IN) { + data = RREG32_SOC15(THM, 0, mmTHM_BACO_CNTL); + data |= 0x80000000; + WREG32_SOC15(THM, 0, mmTHM_BACO_CNTL, data); + + + if(smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_EnterBaco, 0)) + return -1; + + } else if (state == BACO_STATE_OUT) { + if (smum_send_msg_to_smc(hwmgr, PPSMC_MSG_ExitBaco)) + return -1; + if (!soc15_baco_program_registers(hwmgr, clean_baco_tbl, + ARRAY_SIZE(clean_baco_tbl))) + return -1; + } + + return 0; +} diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h new file mode 100644 index 000000000000..db50c20f3976 --- /dev/null +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_baco.h @@ -0,0 +1,32 @@ +/* + * Copyright 2018 Advanced Micro Devices, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR + * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, + * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR + * OTHER DEALINGS IN THE SOFTWARE. + * + */ +#ifndef __VEGA20_BOCO_H__ +#define __VEGA20_BOCO_H__ +#include "hwmgr.h" +#include "common_baco.h" + +extern int vega20_baco_get_capability(struct pp_hwmgr *hwmgr, bool *cap); +extern int vega20_baco_get_state(struct pp_hwmgr *hwmgr, enum BACO_STATE *state); +extern int vega20_baco_set_state(struct pp_hwmgr *hwmgr, enum BACO_STATE state); + +#endif diff --git a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c index 82935a3bd950..2ba387b0f27c 100644 --- a/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c +++ b/drivers/gpu/drm/amd/powerplay/hwmgr/vega20_hwmgr.c @@ -47,6 +47,7 @@ #include "pp_overdriver.h" #include "pp_thermal.h" #include "soc15_common.h" +#include "vega20_baco.h" #include "smuio/smuio_9_0_offset.h" #include "smuio/smuio_9_0_sh_mask.h" #include "nbio/nbio_7_4_sh_mask.h" @@ -3591,6 +3592,10 @@ static const struct pp_hwmgr_func vega20_hwmgr_funcs = { /* smu memory related */ .notify_cac_buffer_info = vega20_notify_cac_buffer_info, .enable_mgpu_fan_boost = vega20_enable_mgpu_fan_boost, + /* BACO related */ + .get_asic_baco_capability = vega20_baco_get_capability, + .get_asic_baco_state = vega20_baco_get_state, + .set_asic_baco_state = vega20_baco_set_state, }; int vega20_hwmgr_init(struct pp_hwmgr *hwmgr) -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH 5/5] drm/amdgpu: use BACO reset on vega20 if platform support [not found] ` <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org> ` (3 preceding siblings ...) 2019-01-11 3:19 ` [PATCH 4/5] drm/amdgpu/powerper: add vega20 BACO functins Jim Qu @ 2019-01-11 3:19 ` Jim Qu 4 siblings, 0 replies; 6+ messages in thread From: Jim Qu @ 2019-01-11 3:19 UTC (permalink / raw) To: amd-gfx-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW; +Cc: Jim Qu Change-Id: I531fa83ccf4abf593194afd6ff0702ba1393d6c7 Signed-off-by: Jim Qu <Jim.Qu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> --- drivers/gpu/drm/amd/amdgpu/soc15.c | 1 + 1 file changed, 1 insertion(+) diff --git a/drivers/gpu/drm/amd/amdgpu/soc15.c b/drivers/gpu/drm/amd/amdgpu/soc15.c index ece6fca476d4..baf90380df6d 100644 --- a/drivers/gpu/drm/amd/amdgpu/soc15.c +++ b/drivers/gpu/drm/amd/amdgpu/soc15.c @@ -462,6 +462,7 @@ static int soc15_asic_reset(struct amdgpu_device *adev) switch (adev->asic_type) { case CHIP_VEGA10: + case CHIP_VEGA20: soc15_asic_get_baco_capability(adev, &baco_reset); break; default: -- 2.17.1 _______________________________________________ amd-gfx mailing list amd-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/amd-gfx ^ permalink raw reply related [flat|nested] 6+ messages in thread
end of thread, other threads:[~2019-01-11 3:19 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-01-11 3:19 [PATCH 0/5] Enable BACO function on VG20 Jim Qu
[not found] ` <20190111031950.32475-1-Jim.Qu-5C7GfCeVMHo@public.gmane.org>
2019-01-11 3:19 ` [PATCH 1/5] drm/amdgpu: update NBIO v7.4 to support BACO Jim Qu
2019-01-11 3:19 ` [PATCH 2/5] drm/amdgpu: also include NBIO v7.4 register mask header Jim Qu
2019-01-11 3:19 ` [PATCH 3/5] drm/amdgpu: update THM IP register header to support BACO Jim Qu
2019-01-11 3:19 ` [PATCH 4/5] drm/amdgpu/powerper: add vega20 BACO functins Jim Qu
2019-01-11 3:19 ` [PATCH 5/5] drm/amdgpu: use BACO reset on vega20 if platform support Jim Qu
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.