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From: Boris Brezillon <bbrezillon@kernel.org>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Stefan Roese <sr@denx.de>, Richard Weinberger <richard@nod.at>,
	Emil Lenngren <emil.lenngren@gmail.com>,
	stable@vger.kernel.org, Marek Vasut <marek.vasut@gmail.com>,
	linux-mtd@lists.infradead.org,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>
Subject: Re: [PATCH] mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache
Date: Fri, 25 Jan 2019 17:08:51 +0100	[thread overview]
Message-ID: <20190125170851.3d918da5@bbrezillon> (raw)
In-Reply-To: <20190125120910.59c33a4b@xps13>

On Fri, 25 Jan 2019 12:09:10 +0100
Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> Hello,
> 
> Boris Brezillon <bbrezillon@kernel.org> wrote on Thu, 24 Jan 2019
> 17:33:57 +0100:
> 
> > On Thu, 24 Jan 2019 17:16:37 +0100
> > Emil Lenngren <emil.lenngren@gmail.com> wrote:
> >   
> > > Hi,
> > > 
> > > Den tors 24 jan. 2019 kl 16:28 skrev Stefan Roese <sr@denx.de>:    
> > > >
> > > > On 24.01.19 15:20, Boris Brezillon wrote:      
> > > > > Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
> > > > > the cache content to 0xFF (depends on vendor implementation), so we
> > > > > must fill the page cache entirely even if we only want to program the
> > > > > data portion of the page, otherwise we might corrupt the BBM or user
> > > > > data previously programmed in OOB area.
> > > > >
> > > > > Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
> > > > > Reported-by: Stefan Roese <sr@denx.de>
> > > > > Cc: <stable@vger.kernel.org>
> > > > > Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>      
> > > >
> > > > Works fine (limited testing only yet), so:
> > > >
> > > > Tested-by: Stefan Roese <sr@denx.de>
> > > > Reviewed-by: Stefan Roese <sr@denx.de>
> > > >
> > > > Thanks,
> > > > Stefan
> > > >      
> > > 
> > > Can this quirk be made vendor specific?    
> > 
> > We can make it vendor specific, as long as it's an opt-in thing. This
> > way, the default behavior is the safest one, and only when we know a
> > chip does reset the cache content on a PROGRAM LOAD time can we add this
> > flag.  
> 
> I am fine with this approach.

Does that stand for a Reviewed-by/Acked-by? To make it clear, I was
saying that we should fix things first (with this fix) and only then
optimize things for chips that actually reset the cache when PROGRAM
LOAD is executed. I was not planning on sending a new version of this
patch, unless you see good reasons to do so.

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <bbrezillon@kernel.org>
To: Miquel Raynal <miquel.raynal@bootlin.com>
Cc: Emil Lenngren <emil.lenngren@gmail.com>,
	Stefan Roese <sr@denx.de>, Richard Weinberger <richard@nod.at>,
	linux-mtd@lists.infradead.org,
	Marek Vasut <marek.vasut@gmail.com>,
	Brian Norris <computersforpeace@gmail.com>,
	David Woodhouse <dwmw2@infradead.org>,
	stable@vger.kernel.org
Subject: Re: [PATCH] mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache
Date: Fri, 25 Jan 2019 17:08:51 +0100	[thread overview]
Message-ID: <20190125170851.3d918da5@bbrezillon> (raw)
In-Reply-To: <20190125120910.59c33a4b@xps13>

On Fri, 25 Jan 2019 12:09:10 +0100
Miquel Raynal <miquel.raynal@bootlin.com> wrote:

> Hello,
> 
> Boris Brezillon <bbrezillon@kernel.org> wrote on Thu, 24 Jan 2019
> 17:33:57 +0100:
> 
> > On Thu, 24 Jan 2019 17:16:37 +0100
> > Emil Lenngren <emil.lenngren@gmail.com> wrote:
> >   
> > > Hi,
> > > 
> > > Den tors 24 jan. 2019 kl 16:28 skrev Stefan Roese <sr@denx.de>:    
> > > >
> > > > On 24.01.19 15:20, Boris Brezillon wrote:      
> > > > > Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
> > > > > the cache content to 0xFF (depends on vendor implementation), so we
> > > > > must fill the page cache entirely even if we only want to program the
> > > > > data portion of the page, otherwise we might corrupt the BBM or user
> > > > > data previously programmed in OOB area.
> > > > >
> > > > > Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
> > > > > Reported-by: Stefan Roese <sr@denx.de>
> > > > > Cc: <stable@vger.kernel.org>
> > > > > Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>      
> > > >
> > > > Works fine (limited testing only yet), so:
> > > >
> > > > Tested-by: Stefan Roese <sr@denx.de>
> > > > Reviewed-by: Stefan Roese <sr@denx.de>
> > > >
> > > > Thanks,
> > > > Stefan
> > > >      
> > > 
> > > Can this quirk be made vendor specific?    
> > 
> > We can make it vendor specific, as long as it's an opt-in thing. This
> > way, the default behavior is the safest one, and only when we know a
> > chip does reset the cache content on a PROGRAM LOAD time can we add this
> > flag.  
> 
> I am fine with this approach.

Does that stand for a Reviewed-by/Acked-by? To make it clear, I was
saying that we should fix things first (with this fix) and only then
optimize things for chips that actually reset the cache when PROGRAM
LOAD is executed. I was not planning on sending a new version of this
patch, unless you see good reasons to do so.

  reply	other threads:[~2019-01-25 16:09 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-01-24 14:20 [PATCH] mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache Boris Brezillon
2019-01-24 14:20 ` Boris Brezillon
2019-01-24 15:25 ` Stefan Roese
2019-01-24 15:25   ` Stefan Roese
2019-01-24 16:16   ` Emil Lenngren
2019-01-24 16:16     ` Emil Lenngren
2019-01-24 16:33     ` Boris Brezillon
2019-01-24 16:33       ` Boris Brezillon
2019-01-25 11:09       ` Miquel Raynal
2019-01-25 11:09         ` Miquel Raynal
2019-01-25 16:08         ` Boris Brezillon [this message]
2019-01-25 16:08           ` Boris Brezillon
2019-01-28  9:55           ` Miquel Raynal
2019-01-28  9:55             ` Miquel Raynal
2019-01-31 11:32 ` Boris Brezillon
2019-01-31 11:32   ` Boris Brezillon

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