Re: [PATCH] mtd: spinand: Handle the case where PROGRAM LOAD does not reset the cache

[Miquel Raynal <miquel.raynal@bootlin.com>]

Hi Boris,

Boris Brezillon <bbrezillon@kernel.org> wrote on Fri, 25 Jan 2019
17:08:51 +0100:

> On Fri, 25 Jan 2019 12:09:10 +0100
> Miquel Raynal <miquel.raynal@bootlin.com> wrote:
> 
> > Hello,
> > 
> > Boris Brezillon <bbrezillon@kernel.org> wrote on Thu, 24 Jan 2019
> > 17:33:57 +0100:
> >   
> > > On Thu, 24 Jan 2019 17:16:37 +0100
> > > Emil Lenngren <emil.lenngren@gmail.com> wrote:
> > >     
> > > > Hi,
> > > > 
> > > > Den tors 24 jan. 2019 kl 16:28 skrev Stefan Roese <sr@denx.de>:      
> > > > >
> > > > > On 24.01.19 15:20, Boris Brezillon wrote:        
> > > > > > Looks like PROGRAM LOAD (AKA write cache) does not necessarily reset
> > > > > > the cache content to 0xFF (depends on vendor implementation), so we
> > > > > > must fill the page cache entirely even if we only want to program the
> > > > > > data portion of the page, otherwise we might corrupt the BBM or user
> > > > > > data previously programmed in OOB area.
> > > > > >
> > > > > > Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs")
> > > > > > Reported-by: Stefan Roese <sr@denx.de>
> > > > > > Cc: <stable@vger.kernel.org>
> > > > > > Signed-off-by: Boris Brezillon <bbrezillon@kernel.org>        
> > > > >
> > > > > Works fine (limited testing only yet), so:
> > > > >
> > > > > Tested-by: Stefan Roese <sr@denx.de>
> > > > > Reviewed-by: Stefan Roese <sr@denx.de>
> > > > >
> > > > > Thanks,
> > > > > Stefan
> > > > >        
> > > > 
> > > > Can this quirk be made vendor specific?      
> > > 
> > > We can make it vendor specific, as long as it's an opt-in thing. This
> > > way, the default behavior is the safest one, and only when we know a
> > > chip does reset the cache content on a PROGRAM LOAD time can we add this
> > > flag.    
> > 
> > I am fine with this approach.  
> 
> Does that stand for a Reviewed-by/Acked-by? To make it clear, I was
> saying that we should fix things first (with this fix) and only then
> optimize things for chips that actually reset the cache when PROGRAM
> LOAD is executed. I was not planning on sending a new version of this
> patch, unless you see good reasons to do so.

I thought you would send a v2 but I am fine with this approach too.

Acked-by: Miquel Raynal <miquel.raynal@bootlin.com>


Thanks,
Miquèl

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