From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: alexandre.belloni@bootlin.com, Nicolas.Ferre@microchip.com,
linux-kernel@vger.kernel.org, Ludovic.Desroches@microchip.com,
broonie@kernel.org, linux-mtd@lists.infradead.org,
linux-spi@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 9/9] spi: atmel-quadspi: add support for sam9x60 qspi controller
Date: Thu, 31 Jan 2019 13:01:50 +0100 [thread overview]
Message-ID: <20190131130137.52b592f8@bbrezillon> (raw)
In-Reply-To: <20190130150818.24902-10-tudor.ambarus@microchip.com>
On Wed, 30 Jan 2019 15:08:47 +0000
<Tudor.Ambarus@microchip.com> wrote:
> +/*
> + * atmel_qspi_set_address_mode() - set address mode.
> + * @cfg: contains register values
> + * @op: describes a SPI memory operation
> + *
> + * The controller allows 24 and 32-bit addressing while NAND-flash requires
> + * 16-bit long. Handling 8-bit long addresses is done using the option field.
> + * For the 16-bit addresses, the workaround depends of the number of requested
> + * dummy bits. If there are 8 or more dummy cycles, the address is shifted and
> + * sent with the first dummy byte. Otherwise opcode is disabled and the first
> + * byte of the address contains the command opcode (works only if the opcode and
> + * address use the same buswidth). The limitation is when the 16-bit address is
> + * used without enough dummy cycles and the opcode is using a different buswidth
> + * than the address.
Too bad they didn't patch the IP to support 1 to 4 address bytes
instead of only 3 or 4 :-(.
______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: alexandre.belloni@bootlin.com, linux-kernel@vger.kernel.org,
Ludovic.Desroches@microchip.com, broonie@kernel.org,
linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 9/9] spi: atmel-quadspi: add support for sam9x60 qspi controller
Date: Thu, 31 Jan 2019 13:01:50 +0100 [thread overview]
Message-ID: <20190131130137.52b592f8@bbrezillon> (raw)
In-Reply-To: <20190130150818.24902-10-tudor.ambarus@microchip.com>
On Wed, 30 Jan 2019 15:08:47 +0000
<Tudor.Ambarus@microchip.com> wrote:
> +/*
> + * atmel_qspi_set_address_mode() - set address mode.
> + * @cfg: contains register values
> + * @op: describes a SPI memory operation
> + *
> + * The controller allows 24 and 32-bit addressing while NAND-flash requires
> + * 16-bit long. Handling 8-bit long addresses is done using the option field.
> + * For the 16-bit addresses, the workaround depends of the number of requested
> + * dummy bits. If there are 8 or more dummy cycles, the address is shifted and
> + * sent with the first dummy byte. Otherwise opcode is disabled and the first
> + * byte of the address contains the command opcode (works only if the opcode and
> + * address use the same buswidth). The limitation is when the 16-bit address is
> + * used without enough dummy cycles and the opcode is using a different buswidth
> + * than the address.
Too bad they didn't patch the IP to support 1 to 4 address bytes
instead of only 3 or 4 :-(.
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: alexandre.belloni@bootlin.com, linux-kernel@vger.kernel.org,
Ludovic.Desroches@microchip.com, broonie@kernel.org,
linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 9/9] spi: atmel-quadspi: add support for sam9x60 qspi controller
Date: Thu, 31 Jan 2019 13:01:50 +0100 [thread overview]
Message-ID: <20190131130137.52b592f8@bbrezillon> (raw)
In-Reply-To: <20190130150818.24902-10-tudor.ambarus@microchip.com>
On Wed, 30 Jan 2019 15:08:47 +0000
<Tudor.Ambarus@microchip.com> wrote:
> +/*
> + * atmel_qspi_set_address_mode() - set address mode.
> + * @cfg: contains register values
> + * @op: describes a SPI memory operation
> + *
> + * The controller allows 24 and 32-bit addressing while NAND-flash requires
> + * 16-bit long. Handling 8-bit long addresses is done using the option field.
> + * For the 16-bit addresses, the workaround depends of the number of requested
> + * dummy bits. If there are 8 or more dummy cycles, the address is shifted and
> + * sent with the first dummy byte. Otherwise opcode is disabled and the first
> + * byte of the address contains the command opcode (works only if the opcode and
> + * address use the same buswidth). The limitation is when the 16-bit address is
> + * used without enough dummy cycles and the opcode is using a different buswidth
> + * than the address.
Too bad they didn't patch the IP to support 1 to 4 address bytes
instead of only 3 or 4 :-(.
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Boris Brezillon <bbrezillon@kernel.org>
To: <Tudor.Ambarus@microchip.com>
Cc: <broonie@kernel.org>, <Nicolas.Ferre@microchip.com>,
<alexandre.belloni@bootlin.com>,
<Ludovic.Desroches@microchip.com>,
linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-spi@vger.kernel.org
Subject: Re: [PATCH 9/9] spi: atmel-quadspi: add support for sam9x60 qspi controller
Date: Thu, 31 Jan 2019 13:01:50 +0100 [thread overview]
Message-ID: <20190131130137.52b592f8@bbrezillon> (raw)
In-Reply-To: <20190130150818.24902-10-tudor.ambarus@microchip.com>
On Wed, 30 Jan 2019 15:08:47 +0000
<Tudor.Ambarus@microchip.com> wrote:
> +/*
> + * atmel_qspi_set_address_mode() - set address mode.
> + * @cfg: contains register values
> + * @op: describes a SPI memory operation
> + *
> + * The controller allows 24 and 32-bit addressing while NAND-flash requires
> + * 16-bit long. Handling 8-bit long addresses is done using the option field.
> + * For the 16-bit addresses, the workaround depends of the number of requested
> + * dummy bits. If there are 8 or more dummy cycles, the address is shifted and
> + * sent with the first dummy byte. Otherwise opcode is disabled and the first
> + * byte of the address contains the command opcode (works only if the opcode and
> + * address use the same buswidth). The limitation is when the 16-bit address is
> + * used without enough dummy cycles and the opcode is using a different buswidth
> + * than the address.
Too bad they didn't patch the IP to support 1 to 4 address bytes
instead of only 3 or 4 :-(.
next prev parent reply other threads:[~2019-01-31 12:02 UTC|newest]
Thread overview: 83+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-01-30 15:08 [PATCH 0/9] spi: atmel-quadspi: introduce sam9x60 qspi contoller Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` [PATCH 1/9] spi: atmel-quadspi: optimize qspi init Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:15 ` Boris Brezillon
2019-01-30 17:15 ` Boris Brezillon
2019-01-30 17:15 ` Boris Brezillon
2019-01-31 10:42 ` Tudor.Ambarus
2019-01-31 10:42 ` Tudor.Ambarus
2019-01-31 10:42 ` Tudor.Ambarus
2019-01-30 15:08 ` [PATCH 2/9] spi: atmel-quadspi: order header files inclusion alphabetically Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:16 ` Boris Brezillon
2019-01-30 17:16 ` Boris Brezillon
2019-01-30 17:16 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 3/9] spi: atmel-quadspi: fix naming scheme Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:19 ` Boris Brezillon
2019-01-30 17:19 ` Boris Brezillon
2019-01-30 17:19 ` Boris Brezillon
2019-01-31 10:43 ` Tudor.Ambarus
2019-01-31 10:43 ` Tudor.Ambarus
2019-01-31 10:43 ` Tudor.Ambarus
2019-01-30 15:08 ` [PATCH 4/9] spi: atmel-quadspi: remove unnecessary cast Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:20 ` Boris Brezillon
2019-01-30 17:20 ` Boris Brezillon
2019-01-30 17:20 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 5/9] spi: atmel-quadspi: return appropriate error code Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:21 ` Boris Brezillon
2019-01-30 17:21 ` Boris Brezillon
2019-01-30 17:21 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 6/9] spi: atmel-quadspi: switch to SPDX license identifiers Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:23 ` Boris Brezillon
2019-01-30 17:23 ` Boris Brezillon
2019-01-30 17:23 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 7/9] dt-bindings: spi: atmel-quadspi: update example to new clock binding Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:25 ` Boris Brezillon
2019-01-30 17:25 ` Boris Brezillon
2019-01-30 17:25 ` Boris Brezillon
2019-01-30 15:08 ` [PATCH 8/9] dt-bindings: spi: atmel-quadspi: QuadSPI driver for Microchip SAM9X60 Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:30 ` Boris Brezillon
2019-01-30 17:30 ` Boris Brezillon
2019-01-30 17:30 ` Boris Brezillon
2019-01-31 10:45 ` Tudor.Ambarus
2019-01-31 10:45 ` Tudor.Ambarus
2019-01-31 10:45 ` Tudor.Ambarus
2019-01-30 15:08 ` [PATCH 9/9] spi: atmel-quadspi: add support for sam9x60 qspi controller Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 15:08 ` Tudor.Ambarus
2019-01-30 17:43 ` Boris Brezillon
2019-01-30 17:43 ` Boris Brezillon
2019-01-30 17:43 ` Boris Brezillon
2019-01-31 10:46 ` Tudor.Ambarus
2019-01-31 10:46 ` Tudor.Ambarus
2019-01-31 10:46 ` Tudor.Ambarus
2019-01-31 11:55 ` Boris Brezillon
2019-01-31 11:55 ` Boris Brezillon
2019-01-31 11:55 ` Boris Brezillon
2019-01-31 12:40 ` Tudor.Ambarus
2019-01-31 12:40 ` Tudor.Ambarus
2019-01-31 12:40 ` Tudor.Ambarus
2019-01-31 13:12 ` Boris Brezillon
2019-01-31 13:12 ` Boris Brezillon
2019-01-31 13:12 ` Boris Brezillon
2019-01-31 12:01 ` Boris Brezillon [this message]
2019-01-31 12:01 ` Boris Brezillon
2019-01-31 12:01 ` Boris Brezillon
2019-01-31 12:01 ` Boris Brezillon
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