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From: keith.busch@intel.com (Keith Busch)
Subject: [PATCH] nvme: Enable acceleration feature of A64FX processor
Date: Tue, 5 Feb 2019 07:39:06 -0700	[thread overview]
Message-ID: <20190205143905.GG22199@localhost.localdomain> (raw)
In-Reply-To: <20190205124757.GA28465@esprimo>

On Tue, Feb 05, 2019@09:56:05PM +0900, Takao Indoh wrote:
> On Fri, Feb 01, 2019@07:54:14AM -0700, Keith Busch wrote:
> > On Fri, Feb 01, 2019@09:46:15PM +0900, Takao Indoh wrote:
> > > From: Takao Indoh <indou.takao at fujitsu.com>
> > > 
> > > Fujitsu A64FX processor has a feature to accelerate data transfer of
> > > internal bus by relaxed ordering. It is enabled when the bit 56 of dma
> > > address is set to 1.
> > 
> > Wait, what? RO is a standard PCIe TLP attribute. Why would we need this?
> 
> I should have explained this patch more carefully.
> 
> Standard PCIe devices can use Relaxed Ordering (RO) by setting Attr
> field in the TLP header, however, this mechanism cannot be utilized if
> the device does not support RO feature. Fujitsu A64FX processor has an
> alternate feature to enable RO in its Root Port by setting the bit 56 of
> DMA address. This mechanism enables to utilize RO feature even if the
> device does not support standard PCIe RO.

I think you're better of just purchasing devices that support the
capability per spec rather than with a non-standard work around.

WARNING: multiple messages have this Message-ID (diff)
From: Keith Busch <keith.busch@intel.com>
To: Takao Indoh <indou.takao@fujitsu.com>
Cc: Takao Indoh <indou.takao@jp.fujitsu.com>,
	axboe@fb.com, hch@lst.de, sagi@grimberg.me,
	linux-nvme@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] nvme: Enable acceleration feature of A64FX processor
Date: Tue, 5 Feb 2019 07:39:06 -0700	[thread overview]
Message-ID: <20190205143905.GG22199@localhost.localdomain> (raw)
In-Reply-To: <20190205124757.GA28465@esprimo>

On Tue, Feb 05, 2019 at 09:56:05PM +0900, Takao Indoh wrote:
> On Fri, Feb 01, 2019 at 07:54:14AM -0700, Keith Busch wrote:
> > On Fri, Feb 01, 2019 at 09:46:15PM +0900, Takao Indoh wrote:
> > > From: Takao Indoh <indou.takao@fujitsu.com>
> > > 
> > > Fujitsu A64FX processor has a feature to accelerate data transfer of
> > > internal bus by relaxed ordering. It is enabled when the bit 56 of dma
> > > address is set to 1.
> > 
> > Wait, what? RO is a standard PCIe TLP attribute. Why would we need this?
> 
> I should have explained this patch more carefully.
> 
> Standard PCIe devices can use Relaxed Ordering (RO) by setting Attr
> field in the TLP header, however, this mechanism cannot be utilized if
> the device does not support RO feature. Fujitsu A64FX processor has an
> alternate feature to enable RO in its Root Port by setting the bit 56 of
> DMA address. This mechanism enables to utilize RO feature even if the
> device does not support standard PCIe RO.

I think you're better of just purchasing devices that support the
capability per spec rather than with a non-standard work around.

  reply	other threads:[~2019-02-05 14:39 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-02-01 12:46 [PATCH] nvme: Enable acceleration feature of A64FX processor Takao Indoh
2019-02-01 12:46 ` Takao Indoh
2019-02-01 14:54 ` Keith Busch
2019-02-01 14:54   ` Keith Busch
2019-02-05 12:56   ` Takao Indoh
2019-02-05 12:56     ` Takao Indoh
2019-02-05 14:39     ` Keith Busch [this message]
2019-02-05 14:39       ` Keith Busch
2019-02-05 16:13       ` Christoph Hellwig
2019-02-05 16:13         ` Christoph Hellwig
2019-02-13 12:03         ` Takao Indoh
2019-02-13 12:03           ` Takao Indoh
2019-02-14 17:11           ` Christoph Hellwig
2019-02-14 17:11             ` Christoph Hellwig
2019-02-14 20:44       ` Elliott, Robert (Persistent Memory)
2019-02-14 20:44         ` Elliott, Robert (Persistent Memory)
2019-02-14 21:17         ` Keith Busch
2019-02-14 21:17           ` Keith Busch
2019-02-20  9:46         ` Takao Indoh
2019-02-20  9:46           ` Takao Indoh
2019-02-22 17:07           ` Keith Busch
2019-02-22 17:07             ` Keith Busch
2019-02-01 15:51 ` Christoph Hellwig
2019-02-01 15:51   ` Christoph Hellwig
2019-02-05 12:56   ` Takao Indoh
2019-02-05 12:56     ` Takao Indoh
2019-02-03  0:17 ` kbuild test robot

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