From: keith.busch@intel.com (Keith Busch)
Subject: [PATCH] nvme: Enable acceleration feature of A64FX processor
Date: Fri, 22 Feb 2019 10:07:15 -0700 [thread overview]
Message-ID: <20190222170715.GA10237@localhost.localdomain> (raw)
In-Reply-To: <20190220094610.GB3559@esprimo>
On Wed, Feb 20, 2019@06:46:11PM +0900, Takao Indoh wrote:
> On Thu, Feb 14, 2019@08:44:48PM +0000, Elliott, Robert (Persistent Memory) wrote:
> > * how does this interact with an iommu, if there is one? Must the
> > address with bit 56 also be granted permission, or is that
> > stripped off before any iommu comparisons?
>
> The latter. A bit 56 is cleared in Root Port before pass it to iommu.
What if the intendend destination is a peer and never hits the root port?
Really, though, PCI device vendors need to just use the existing
capability as intended and not have arch specific work-arounds. I'm sure
nvme can't be the only device class you'd want this behavior.
WARNING: multiple messages have this Message-ID (diff)
From: Keith Busch <keith.busch@intel.com>
To: Takao Indoh <indou.takao@fujitsu.com>
Cc: "Elliott, Robert (Persistent Memory)" <elliott@hpe.com>,
Takao Indoh <indou.takao@jp.fujitsu.com>,
"sagi@grimberg.me" <sagi@grimberg.me>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"linux-nvme@lists.infradead.org" <linux-nvme@lists.infradead.org>,
"axboe@fb.com" <axboe@fb.com>, "hch@lst.de" <hch@lst.de>
Subject: Re: [PATCH] nvme: Enable acceleration feature of A64FX processor
Date: Fri, 22 Feb 2019 10:07:15 -0700 [thread overview]
Message-ID: <20190222170715.GA10237@localhost.localdomain> (raw)
In-Reply-To: <20190220094610.GB3559@esprimo>
On Wed, Feb 20, 2019 at 06:46:11PM +0900, Takao Indoh wrote:
> On Thu, Feb 14, 2019 at 08:44:48PM +0000, Elliott, Robert (Persistent Memory) wrote:
> > * how does this interact with an iommu, if there is one? Must the
> > address with bit 56 also be granted permission, or is that
> > stripped off before any iommu comparisons?
>
> The latter. A bit 56 is cleared in Root Port before pass it to iommu.
What if the intendend destination is a peer and never hits the root port?
Really, though, PCI device vendors need to just use the existing
capability as intended and not have arch specific work-arounds. I'm sure
nvme can't be the only device class you'd want this behavior.
next prev parent reply other threads:[~2019-02-22 17:07 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-02-01 12:46 [PATCH] nvme: Enable acceleration feature of A64FX processor Takao Indoh
2019-02-01 12:46 ` Takao Indoh
2019-02-01 14:54 ` Keith Busch
2019-02-01 14:54 ` Keith Busch
2019-02-05 12:56 ` Takao Indoh
2019-02-05 12:56 ` Takao Indoh
2019-02-05 14:39 ` Keith Busch
2019-02-05 14:39 ` Keith Busch
2019-02-05 16:13 ` Christoph Hellwig
2019-02-05 16:13 ` Christoph Hellwig
2019-02-13 12:03 ` Takao Indoh
2019-02-13 12:03 ` Takao Indoh
2019-02-14 17:11 ` Christoph Hellwig
2019-02-14 17:11 ` Christoph Hellwig
2019-02-14 20:44 ` Elliott, Robert (Persistent Memory)
2019-02-14 20:44 ` Elliott, Robert (Persistent Memory)
2019-02-14 21:17 ` Keith Busch
2019-02-14 21:17 ` Keith Busch
2019-02-20 9:46 ` Takao Indoh
2019-02-20 9:46 ` Takao Indoh
2019-02-22 17:07 ` Keith Busch [this message]
2019-02-22 17:07 ` Keith Busch
2019-02-01 15:51 ` Christoph Hellwig
2019-02-01 15:51 ` Christoph Hellwig
2019-02-05 12:56 ` Takao Indoh
2019-02-05 12:56 ` Takao Indoh
2019-02-03 0:17 ` kbuild test robot
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