All of lore.kernel.org
 help / color / mirror / Atom feed
* [PATCH] drm/i915: FBC needs vblank before enable / disable.
@ 2019-04-03  6:17 kiran.s.kumar
  2019-04-03  6:39 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: FBC needs vblank before enable / disable. (rev4) Patchwork
                   ` (2 more replies)
  0 siblings, 3 replies; 11+ messages in thread
From: kiran.s.kumar @ 2019-04-03  6:17 UTC (permalink / raw)
  To: intel-gfx

From: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>

As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.

In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final segment of the frame as a result of the
missing last pixel indication. As a result of this, we're seeing
corrupted cache line/compression indicators after FBC re-enables
which causes underruns or corruption when they're used to decompress.

WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC

In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.

Change-Id: I8a3baeda363b2d2ec4e9e8673e89013a341c646a
Signed-off-by: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..90360dfc674b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13207,8 +13207,12 @@ static void intel_update_crtc(struct drm_crtc *crtc,
 
 	if (pipe_config->update_pipe && !pipe_config->enable_fbc)
 		intel_fbc_disable(intel_crtc);
-	else if (new_plane_state)
+	else if (new_plane_state) {
+		/* Display WA #1200: GLK */
+		if (IS_GEMINILAKE(dev_priv))
+			intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 		intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
+	}
 
 	intel_begin_crtc_commit(crtc, old_crtc_state);
 
@@ -13419,6 +13423,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 
 			dev_priv->display.crtc_disable(old_intel_crtc_state, state);
 			intel_crtc->active = false;
+			/* Display WA #1200: GLK */
+			intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 			intel_fbc_disable(intel_crtc);
 			intel_disable_shared_dpll(old_intel_crtc_state);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH] drm/i915: FBC needs vblank before enable / disable
@ 2019-05-29  5:58 kiran.s.kumar
  0 siblings, 0 replies; 11+ messages in thread
From: kiran.s.kumar @ 2019-05-29  5:58 UTC (permalink / raw)
  To: intel-gfx

From: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>

As per the display workaround #1200, FBC needs wait for vblank
before enabling and before disabling FBC.

In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final segment of the frame as a result of the
missing last pixel indication. As a result of this, we're seeing corrupted
cache line/compression indicators after FBC re-enables which causes
underruns or corruption when they're used to decompress.

WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC

In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.

v2: Added wait for vblank code in FBC as it will be called if and only if
fbc is enabled.

And also, as per the information from hardware team that the above
WA is for GLK.

Signed-off-by: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>
---
 drivers/gpu/drm/i915/intel_fbc.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_fbc.c b/drivers/gpu/drm/i915/intel_fbc.c
index 5679f2fffb7c..d4b8cfb8419e 100644
--- a/drivers/gpu/drm/i915/intel_fbc.c
+++ b/drivers/gpu/drm/i915/intel_fbc.c
@@ -1094,6 +1094,8 @@ void intel_fbc_enable(struct intel_crtc *crtc,
 		if (fbc->crtc == crtc) {
 			WARN_ON(!crtc_state->enable_fbc);
 			WARN_ON(fbc->active);
+			if (IS_GEMINILAKE(dev_priv))
+				intel_wait_for_vblank(dev_priv, crtc->pipe);
 		}
 		goto out;
 	}
@@ -1134,8 +1136,11 @@ void intel_fbc_disable(struct intel_crtc *crtc)
 		return;
 
 	mutex_lock(&fbc->lock);
-	if (fbc->crtc == crtc)
+	if (fbc->crtc == crtc) {
 		__intel_fbc_disable(dev_priv);
+		if (IS_GEMINILAKE(dev_priv))
+			intel_wait_for_vblank(dev_priv, crtc->pipe);
+	}
 	mutex_unlock(&fbc->lock);
 }
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH] drm/i915: FBC needs vblank before enable / disable.
@ 2019-04-03  7:10 kiran.s.kumar
  0 siblings, 0 replies; 11+ messages in thread
From: kiran.s.kumar @ 2019-04-03  7:10 UTC (permalink / raw)
  To: intel-gfx

From: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>

As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.

In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final segment of the frame as a result of the
missing last pixel indication. As a result of this, we're seeing
corrupted cache line/compression indicators after FBC re-enables
which causes underruns or corruption when they're used to decompress.

WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC

In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.

Signed-off-by: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>
---
 drivers/gpu/drm/i915/intel_display.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..97c9af921ae1 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13207,8 +13207,12 @@ static void intel_update_crtc(struct drm_crtc *crtc,
 
 	if (pipe_config->update_pipe && !pipe_config->enable_fbc)
 		intel_fbc_disable(intel_crtc);
-	else if (new_plane_state)
+	else if (new_plane_state) {
+		/* Display WA #1200: GLK */
+		if (IS_GEMINILAKE(dev_priv))
+			intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 		intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
+	}
 
 	intel_begin_crtc_commit(crtc, old_crtc_state);
 
@@ -13419,6 +13423,10 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 
 			dev_priv->display.crtc_disable(old_intel_crtc_state, state);
 			intel_crtc->active = false;
+			/* Display WA #1200: GLK */
+			if (IS_GEMINILAKE(dev_priv))
+				intel_wait_for_vblank(dev_priv,
+							intel_crtc->pipe);
 			intel_fbc_disable(intel_crtc);
 			intel_disable_shared_dpll(old_intel_crtc_state);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH] drm/i915: FBC needs vblank before enable / disable.
@ 2019-04-03  7:03 kiran.s.kumar
  0 siblings, 0 replies; 11+ messages in thread
From: kiran.s.kumar @ 2019-04-03  7:03 UTC (permalink / raw)
  To: intel-gfx

From: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>

As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.

In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final segment of the frame as a result of the
missing last pixel indication. As a result of this, we're seeing
corrupted cache line/compression indicators after FBC re-enables
which causes underruns or corruption when they're used to decompress.

WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC

In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.

Signed-off-by: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>
---
 drivers/gpu/drm/i915/intel_display.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..90360dfc674b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13207,8 +13207,12 @@ static void intel_update_crtc(struct drm_crtc *crtc,
 
 	if (pipe_config->update_pipe && !pipe_config->enable_fbc)
 		intel_fbc_disable(intel_crtc);
-	else if (new_plane_state)
+	else if (new_plane_state) {
+		/* Display WA #1200: GLK */
+		if (IS_GEMINILAKE(dev_priv))
+			intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 		intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
+	}
 
 	intel_begin_crtc_commit(crtc, old_crtc_state);
 
@@ -13419,6 +13423,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 
 			dev_priv->display.crtc_disable(old_intel_crtc_state, state);
 			intel_crtc->active = false;
+			/* Display WA #1200: GLK */
+			intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 			intel_fbc_disable(intel_crtc);
 			intel_disable_shared_dpll(old_intel_crtc_state);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH] drm/i915: FBC needs vblank before enable / disable.
@ 2019-04-03  4:50 kiran.s.kumar
  0 siblings, 0 replies; 11+ messages in thread
From: kiran.s.kumar @ 2019-04-03  4:50 UTC (permalink / raw)
  To: intel-gfx

From: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>

As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.

In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to
properly recognize the final segment of the frame as a result of the
missing last pixel indication. As a result of this, we're seeing
corrupted cache line/compression indicators after FBC re-enables
which causes underruns or corruption when they're used to decompress.

WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC

In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.

Signed-off-by: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>
---
 drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..5118a36782eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13207,8 +13207,11 @@ static void intel_update_crtc(struct drm_crtc *crtc,
 
 	if (pipe_config->update_pipe && !pipe_config->enable_fbc)
 		intel_fbc_disable(intel_crtc);
-	else if (new_plane_state)
+	else if (new_plane_state) {
+		/* Display WA #1200: GLK */
+		intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 		intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
+	}
 
 	intel_begin_crtc_commit(crtc, old_crtc_state);
 
@@ -13419,6 +13422,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 
 			dev_priv->display.crtc_disable(old_intel_crtc_state, state);
 			intel_crtc->active = false;
+			/* Display WA #1200: GLK */
+			intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 			intel_fbc_disable(intel_crtc);
 			intel_disable_shared_dpll(old_intel_crtc_state);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH] drm/i915: FBC needs vblank before enable / disable.
@ 2019-04-03  4:30 kiran.s.kumar
  2019-04-03 17:54 ` Souza, Jose
  0 siblings, 1 reply; 11+ messages in thread
From: kiran.s.kumar @ 2019-04-03  4:30 UTC (permalink / raw)
  To: intel-gfx

From: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>

As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.

In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to properly
recognize the final segment of the frame as a result of the missing last
pixel indication. As a result of this, we're seeing corrupted cache
line/compression indicators after FBC re-enables which causes underruns or
corruption when they're used to decompress.

WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC

In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.

Change-Id: I2465610bb0a82df99e5c53b1eb4ed74565996b1e
Signed-off-by: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>
---
 drivers/gpu/drm/i915/intel_display.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 8576a7f799f2..5118a36782eb 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -13207,8 +13207,11 @@ static void intel_update_crtc(struct drm_crtc *crtc,
 
 	if (pipe_config->update_pipe && !pipe_config->enable_fbc)
 		intel_fbc_disable(intel_crtc);
-	else if (new_plane_state)
+	else if (new_plane_state) {
+		/* Display WA #1200: GLK */
+		intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 		intel_fbc_enable(intel_crtc, pipe_config, new_plane_state);
+	}
 
 	intel_begin_crtc_commit(crtc, old_crtc_state);
 
@@ -13419,6 +13422,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 
 			dev_priv->display.crtc_disable(old_intel_crtc_state, state);
 			intel_crtc->active = false;
+			/* Display WA #1200: GLK */
+			intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 			intel_fbc_disable(intel_crtc);
 			intel_disable_shared_dpll(old_intel_crtc_state);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
* [PATCH] drm/i915: FBC needs vblank before enable / disable.
@ 2019-04-01 16:30 kiran.s.kumar
  0 siblings, 0 replies; 11+ messages in thread
From: kiran.s.kumar @ 2019-04-01 16:30 UTC (permalink / raw)
  To: intel-gfx

From: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>

As per the display workaround #1200, FBC needs wait for vblank before
enabling and before disabling FBC.

In some cases, depending on whether FBC was compressing in that frame,
several control signals in the compression engine also will fail to properly
recognize the final segment of the frame as a result of the missing last
pixel indication. As a result of this, we're seeing corrupted cache
line/compression indicators after FBC re-enables which causes underruns or
corruption when they're used to decompress.

WA sequence as below:
1) Display enables plane 1A
2) Wait for 1 vblank
3) FBC gets enabled
4) Wait for 1 VBLANK
5) Turn off FBC

In GLK Chrome OS, if FBC is enabled by default, few top lines on the screen
got corrupted. With the above WA, issue was resolved.

Change-Id: I6c5cc8978bc23fb6fc1f5fedd9599c6281bd78e9
Signed-off-by: Kiran Kumar S <kiran.s.kumar@intel.corp-partner.google.com>
---
 drivers/gpu/drm/i915/intel_display.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index c2d8589a4150..fec06447ab72 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -12246,6 +12246,8 @@ static void intel_update_crtc(struct drm_crtc *crtc,
 	}
 
 	if (drm_atomic_get_existing_plane_state(state, crtc->primary)) {
+		/* Display WA #1200: GLK */
+		intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 		intel_fbc_enable(
 		    intel_crtc, pipe_config,
 		    to_intel_plane_state(crtc->primary->state));
@@ -12419,6 +12421,8 @@ static void intel_atomic_commit_tail(struct drm_atomic_state *state)
 			intel_crtc_disable_planes(crtc, old_crtc_state->plane_mask);
 			dev_priv->display.crtc_disable(to_intel_crtc_state(old_crtc_state), state);
 			intel_crtc->active = false;
+			/* Display WA #1200: GLK */
+			intel_wait_for_vblank(dev_priv, intel_crtc->pipe);
 			intel_fbc_disable(intel_crtc);
 			intel_disable_shared_dpll(intel_crtc);
 
-- 
2.7.4

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 11+ messages in thread
end of thread, other threads:[~2019-05-29  6:08 UTC | newest]

Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-04-03  6:17 [PATCH] drm/i915: FBC needs vblank before enable / disable kiran.s.kumar
2019-04-03  6:39 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: FBC needs vblank before enable / disable. (rev4) Patchwork
2019-04-03  7:01 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-04-05 18:10 ` [PATCH] drm/i915: FBC needs vblank before enable / disable Ville Syrjälä
  -- strict thread matches above, loose matches on Subject: below --
2019-05-29  5:58 kiran.s.kumar
2019-04-03  7:10 kiran.s.kumar
2019-04-03  7:03 kiran.s.kumar
2019-04-03  4:50 kiran.s.kumar
2019-04-03  4:30 kiran.s.kumar
2019-04-03 17:54 ` Souza, Jose
2019-04-01 16:30 kiran.s.kumar

This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.