* [PATCH 1/4] drm/i915: Add gen8_de_pipe_fault_mask()
2019-04-15 15:49 [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Ville Syrjala
@ 2019-04-15 15:49 ` Ville Syrjala
2019-04-15 16:37 ` Chris Wilson
2019-04-15 15:49 ` [PATCH 2/4] drm/i915: Introduce struct hpd_irq_regs Ville Syrjala
` (5 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Ville Syrjala @ 2019-04-15 15:49 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reduce the clutter a bit by introducing gen8_de_pipe_fault_mask().
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 15 +++++++++------
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index d934545445e1..6556fe9e5934 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2740,6 +2740,14 @@ static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
return mask;
}
+static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
+{
+ if (INTEL_GEN(dev_priv) >= 9)
+ return GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
+ else
+ return GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
+}
+
static irqreturn_t
gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
{
@@ -2852,12 +2860,7 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (iir & GEN8_PIPE_FIFO_UNDERRUN)
intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
- fault_errors = iir;
- if (INTEL_GEN(dev_priv) >= 9)
- fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
- else
- fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
-
+ fault_errors = iir & gen8_de_pipe_fault_mask(dev_priv);
if (fault_errors)
DRM_ERROR("Fault errors on pipe %c: 0x%08x\n",
pipe_name(pipe),
--
2.21.0
_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 2/4] drm/i915: Introduce struct hpd_irq_regs
2019-04-15 15:49 [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Ville Syrjala
2019-04-15 15:49 ` [PATCH 1/4] drm/i915: Add gen8_de_pipe_fault_mask() Ville Syrjala
@ 2019-04-15 15:49 ` Ville Syrjala
2019-04-15 16:45 ` Chris Wilson
2019-04-15 15:49 ` [PATCH 3/4] drm/i915: Split pch irq handling to ack+handler Ville Syrjala
` (4 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Ville Syrjala @ 2019-04-15 15:49 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
Collect the hpd related register values into a struct for
so that it's more convenient to pass them around.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 241 ++++++++++++++++++--------------
1 file changed, 137 insertions(+), 104 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 6556fe9e5934..b6f7b98b9ddb 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1684,6 +1684,11 @@ static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
}
}
+struct hpd_irq_regs {
+ u32 dig_hotplug_reg;
+ u32 hotplug_trigger;
+};
+
/*
* Get a bit mask of pins that have triggered, and which ones may be long.
* This can be called multiple times with the same masks to accumulate
@@ -1693,14 +1698,16 @@ static bool i9xx_port_hotplug_long_detect(enum hpd_pin pin, u32 val)
*/
static void intel_get_hpd_pins(struct drm_i915_private *dev_priv,
u32 *pin_mask, u32 *long_mask,
- u32 hotplug_trigger, u32 dig_hotplug_reg,
- const u32 hpd[HPD_NUM_PINS],
+ const struct hpd_irq_regs *hpd,
+ const u32 hpd_pins[HPD_NUM_PINS],
bool long_pulse_detect(enum hpd_pin pin, u32 val))
{
+ u32 hotplug_trigger = hpd->hotplug_trigger;
+ u32 dig_hotplug_reg = hpd->dig_hotplug_reg;
enum hpd_pin pin;
for_each_hpd_pin(pin) {
- if ((hpd[pin] & hotplug_trigger) == 0)
+ if ((hpd_pins[pin] & hotplug_trigger) == 0)
continue;
*pin_mask |= BIT(pin);
@@ -2072,12 +2079,14 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (IS_G4X(dev_priv) || IS_VALLEYVIEW(dev_priv) ||
IS_CHERRYVIEW(dev_priv)) {
- u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
+ struct hpd_irq_regs hpd = {
+ .hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X,
+ .dig_hotplug_reg = hotplug_status & HOTPLUG_INT_STATUS_G4X,
+ };
- if (hotplug_trigger) {
+ if (hpd.hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- hotplug_trigger, hotplug_trigger,
- hpd_status_g4x,
+ &hpd, hpd_status_g4x,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -2086,12 +2095,14 @@ static void i9xx_hpd_irq_handler(struct drm_i915_private *dev_priv,
if (hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
dp_aux_irq_handler(dev_priv);
} else {
- u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
+ struct hpd_irq_regs hpd = {
+ .hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915,
+ .dig_hotplug_reg = hotplug_status & HOTPLUG_INT_STATUS_I915,
+ };
- if (hotplug_trigger) {
+ if (hpd.hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- hotplug_trigger, hotplug_trigger,
- hpd_status_i915,
+ &hpd, hpd_status_i915,
i9xx_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
@@ -2265,44 +2276,51 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
return ret;
}
-static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
- u32 hotplug_trigger,
- const u32 hpd[HPD_NUM_PINS])
+static void ibx_hpd_irq_ack(struct drm_i915_private *dev_priv,
+ struct hpd_irq_regs *hpd)
{
- u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
-
/*
* Somehow the PCH doesn't seem to really ack the interrupt to the CPU
* unless we touch the hotplug register, even if hotplug_trigger is
* zero. Not acking leads to "The master control interrupt lied (SDE)!"
* errors.
*/
- dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
- if (!hotplug_trigger) {
+ hpd->dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
+ if (!hpd->hotplug_trigger) {
u32 mask = PORTA_HOTPLUG_STATUS_MASK |
PORTD_HOTPLUG_STATUS_MASK |
PORTC_HOTPLUG_STATUS_MASK |
PORTB_HOTPLUG_STATUS_MASK;
- dig_hotplug_reg &= ~mask;
+ hpd->dig_hotplug_reg &= ~mask;
}
- I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
- if (!hotplug_trigger)
+ I915_WRITE(PCH_PORT_HOTPLUG, hpd->dig_hotplug_reg);
+}
+
+static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
+ const struct hpd_irq_regs *hpd,
+ const u32 hpd_pins[HPD_NUM_PINS])
+{
+ u32 pin_mask = 0, long_mask = 0;
+
+ if (!hpd->hotplug_trigger)
return;
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
- dig_hotplug_reg, hpd,
- pch_port_hotplug_long_detect);
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hpd, hpd_pins, pch_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
+ struct hpd_irq_regs hpd = {};
int pipe;
- u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
- ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ibx);
+ hpd.hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
+
+ ibx_hpd_irq_ack(dev_priv, &hpd);
+ ibx_hpd_irq_handler(dev_priv, &hpd, hpd_ibx);
if (pch_iir & SDE_AUDIO_POWER_MASK) {
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
@@ -2385,10 +2403,13 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
+ struct hpd_irq_regs hpd = {};
int pipe;
- u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
- ibx_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_cpt);
+ hpd.hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
+
+ ibx_hpd_irq_ack(dev_priv, &hpd);
+ ibx_hpd_irq_handler(dev_priv, &hpd, hpd_cpt);
if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
@@ -2421,31 +2442,28 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
- u32 ddi_hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
- u32 tc_hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
+ struct hpd_irq_regs ddi = {};
+ struct hpd_irq_regs tc = {};
u32 pin_mask = 0, long_mask = 0;
- if (ddi_hotplug_trigger) {
- u32 dig_hotplug_reg;
+ ddi.hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
+ tc.hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
- dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
- I915_WRITE(SHOTPLUG_CTL_DDI, dig_hotplug_reg);
+ if (ddi.hotplug_trigger) {
+ ddi.dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
+ I915_WRITE(SHOTPLUG_CTL_DDI, ddi.dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- ddi_hotplug_trigger,
- dig_hotplug_reg, hpd_icp,
+ &ddi, hpd_icp,
icp_ddi_port_hotplug_long_detect);
}
- if (tc_hotplug_trigger) {
- u32 dig_hotplug_reg;
-
- dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
- I915_WRITE(SHOTPLUG_CTL_TC, dig_hotplug_reg);
+ if (tc.hotplug_trigger) {
+ tc.dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
+ I915_WRITE(SHOTPLUG_CTL_TC, tc.dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- tc_hotplug_trigger,
- dig_hotplug_reg, hpd_icp,
+ &tc, hpd_icp,
icp_tc_port_hotplug_long_detect);
}
@@ -2458,30 +2476,29 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
{
- u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
+ u32 pin_mask = 0, long_mask = 0;
+ struct hpd_irq_regs hpd = {};
+ struct hpd_irq_regs hpd2 = {};
+
+ hpd.hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
~SDE_PORTE_HOTPLUG_SPT;
- u32 hotplug2_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
- u32 pin_mask = 0, long_mask = 0;
+ hpd2.hotplug_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
- if (hotplug_trigger) {
- u32 dig_hotplug_reg;
-
- dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
- I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
+ if (hpd.hotplug_trigger) {
+ hpd.dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
+ I915_WRITE(PCH_PORT_HOTPLUG, hpd.dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- hotplug_trigger, dig_hotplug_reg, hpd_spt,
+ &hpd, hpd_spt,
spt_port_hotplug_long_detect);
}
- if (hotplug2_trigger) {
- u32 dig_hotplug_reg;
-
- dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
- I915_WRITE(PCH_PORT_HOTPLUG2, dig_hotplug_reg);
+ if (hpd2.hotplug_trigger) {
+ hpd2.dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
+ I915_WRITE(PCH_PORT_HOTPLUG2, hpd2.dig_hotplug_reg);
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- hotplug2_trigger, dig_hotplug_reg, hpd_spt,
+ &hpd2, hpd_spt,
spt_port_hotplug2_long_detect);
}
@@ -2492,17 +2509,21 @@ static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
gmbus_irq_handler(dev_priv);
}
+static void ilk_hpd_irq_ack(struct drm_i915_private *dev_priv,
+ struct hpd_irq_regs *hpd)
+{
+ hpd->dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
+ I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, hpd->dig_hotplug_reg);
+}
+
static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
- u32 hotplug_trigger,
- const u32 hpd[HPD_NUM_PINS])
+ const struct hpd_irq_regs *hpd,
+ const u32 hpd_pins[HPD_NUM_PINS])
{
- u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
+ u32 pin_mask = 0, long_mask = 0;
- dig_hotplug_reg = I915_READ(DIGITAL_PORT_HOTPLUG_CNTRL);
- I915_WRITE(DIGITAL_PORT_HOTPLUG_CNTRL, dig_hotplug_reg);
-
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
- dig_hotplug_reg, hpd,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hpd, hpd_pins,
ilk_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -2511,11 +2532,14 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
u32 de_iir)
{
+ struct hpd_irq_regs hpd = {};
enum pipe pipe;
- u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
- if (hotplug_trigger)
- ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ilk);
+ hpd.hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
+ if (hpd.hotplug_trigger) {
+ ilk_hpd_irq_ack(dev_priv, &hpd);
+ ilk_hpd_irq_handler(dev_priv, &hpd, hpd_ilk);
+ }
if (de_iir & DE_AUX_CHANNEL_A)
dp_aux_irq_handler(dev_priv);
@@ -2557,11 +2581,14 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
u32 de_iir)
{
+ struct hpd_irq_regs hpd = {};
enum pipe pipe;
- u32 hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
- if (hotplug_trigger)
- ilk_hpd_irq_handler(dev_priv, hotplug_trigger, hpd_ivb);
+ hpd.hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
+ if (hpd.hotplug_trigger) {
+ ilk_hpd_irq_ack(dev_priv, &hpd);
+ ilk_hpd_irq_handler(dev_priv, &hpd, hpd_ivb);
+ }
if (de_iir & DE_ERR_INT_IVB)
ivb_err_int_handler(dev_priv);
@@ -2671,17 +2698,21 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
return ret;
}
+static void bxt_hpd_irq_ack(struct drm_i915_private *dev_priv,
+ struct hpd_irq_regs *hpd)
+{
+ hpd->dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
+ I915_WRITE(PCH_PORT_HOTPLUG, hpd->dig_hotplug_reg);
+}
+
static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
- u32 hotplug_trigger,
- const u32 hpd[HPD_NUM_PINS])
+ const struct hpd_irq_regs *hpd,
+ const u32 hpd_pins[HPD_NUM_PINS])
{
- u32 dig_hotplug_reg, pin_mask = 0, long_mask = 0;
+ u32 pin_mask = 0, long_mask = 0;
- dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
- I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
-
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, hotplug_trigger,
- dig_hotplug_reg, hpd,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ hpd, hpd_pins,
bxt_port_hotplug_long_detect);
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
@@ -2689,29 +2720,28 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
{
+ struct hpd_irq_regs tc = {};
+ struct hpd_irq_regs tbt = {};
u32 pin_mask = 0, long_mask = 0;
- u32 trigger_tc = iir & GEN11_DE_TC_HOTPLUG_MASK;
- u32 trigger_tbt = iir & GEN11_DE_TBT_HOTPLUG_MASK;
- if (trigger_tc) {
- u32 dig_hotplug_reg;
+ tc.hotplug_trigger = iir & GEN11_DE_TC_HOTPLUG_MASK;
+ tbt.hotplug_trigger = iir & GEN11_DE_TBT_HOTPLUG_MASK;
- dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
- I915_WRITE(GEN11_TC_HOTPLUG_CTL, dig_hotplug_reg);
+ if (tc.hotplug_trigger) {
+ tc.dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
+ I915_WRITE(GEN11_TC_HOTPLUG_CTL, tc.dig_hotplug_reg);
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tc,
- dig_hotplug_reg, hpd_gen11,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ &tc, hpd_gen11,
gen11_port_hotplug_long_detect);
}
- if (trigger_tbt) {
- u32 dig_hotplug_reg;
+ if (tbt.hotplug_trigger) {
+ tbt.dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
+ I915_WRITE(GEN11_TBT_HOTPLUG_CTL, tbt.dig_hotplug_reg);
- dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
- I915_WRITE(GEN11_TBT_HOTPLUG_CTL, dig_hotplug_reg);
-
- intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask, trigger_tbt,
- dig_hotplug_reg, hpd_gen11,
+ intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
+ &tbt, hpd_gen11,
gen11_port_hotplug_long_detect);
}
@@ -2797,7 +2827,6 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (master_ctl & GEN8_DE_PORT_IRQ) {
iir = I915_READ(GEN8_DE_PORT_IIR);
if (iir) {
- u32 tmp_mask;
bool found = false;
I915_WRITE(GEN8_DE_PORT_IIR, iir);
@@ -2809,17 +2838,21 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
}
if (IS_GEN9_LP(dev_priv)) {
- tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
- if (tmp_mask) {
- bxt_hpd_irq_handler(dev_priv, tmp_mask,
- hpd_bxt);
+ struct hpd_irq_regs ddi = {};
+
+ ddi.hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
+ if (ddi.hotplug_trigger) {
+ bxt_hpd_irq_ack(dev_priv, &ddi);
+ bxt_hpd_irq_handler(dev_priv, &ddi, hpd_bxt);
found = true;
}
} else if (IS_BROADWELL(dev_priv)) {
- tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
- if (tmp_mask) {
- ilk_hpd_irq_handler(dev_priv,
- tmp_mask, hpd_bdw);
+ struct hpd_irq_regs ddi = {};
+
+ ddi.hotplug_trigger = iir & GEN8_PORT_DP_A_HOTPLUG;
+ if (ddi.hotplug_trigger) {
+ ilk_hpd_irq_ack(dev_priv, &ddi);
+ ilk_hpd_irq_handler(dev_priv, &ddi, hpd_bdw);
found = true;
}
}
--
2.21.0
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread* [PATCH 3/4] drm/i915: Split pch irq handling to ack+handler
2019-04-15 15:49 [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Ville Syrjala
2019-04-15 15:49 ` [PATCH 1/4] drm/i915: Add gen8_de_pipe_fault_mask() Ville Syrjala
2019-04-15 15:49 ` [PATCH 2/4] drm/i915: Introduce struct hpd_irq_regs Ville Syrjala
@ 2019-04-15 15:49 ` Ville Syrjala
2019-04-15 16:48 ` Chris Wilson
2019-04-15 15:49 ` [PATCH 4/4] drm/i915: Finish the irq ack+handler split for ilk+ Ville Syrjala
` (3 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Ville Syrjala @ 2019-04-15 15:49 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
The proper way to process interrupts is to first acknowledge them
all, and later process them. Start down that path for pch interrupts
by collecting the relevant register values into a struct so that
we can carry them from the ack part to the handler part.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 198 +++++++++++++++++++++-----------
1 file changed, 131 insertions(+), 67 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b6f7b98b9ddb..14e0e9fe1853 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2276,6 +2276,19 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
return ret;
}
+struct pch_irq_regs {
+ u32 iir;
+ u32 serr_int; /* cpt/lpt */
+ union {
+ struct hpd_irq_regs hpd; /* ibx+ */
+ struct hpd_irq_regs ddi; /* icp+ */
+ };
+ union {
+ struct hpd_irq_regs hpd2; /* spt+ */
+ struct hpd_irq_regs tc; /* icp+ */
+ };
+};
+
static void ibx_hpd_irq_ack(struct drm_i915_private *dev_priv,
struct hpd_irq_regs *hpd)
{
@@ -2312,15 +2325,21 @@ static void ibx_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
-static void ibx_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+static void ibx_irq_ack(struct drm_i915_private *dev_priv,
+ struct pch_irq_regs *pch)
{
- struct hpd_irq_regs hpd = {};
- int pipe;
+ pch->hpd.hotplug_trigger = pch->iir & SDE_HOTPLUG_MASK;
- hpd.hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
+ ibx_hpd_irq_ack(dev_priv, &pch->hpd);
+}
- ibx_hpd_irq_ack(dev_priv, &hpd);
- ibx_hpd_irq_handler(dev_priv, &hpd, hpd_ibx);
+static void ibx_irq_handler(struct drm_i915_private *dev_priv,
+ const struct pch_irq_regs *pch)
+{
+ u32 pch_iir = pch->iir;
+ enum pipe pipe;
+
+ ibx_hpd_irq_handler(dev_priv, &pch->hpd, hpd_ibx);
if (pch_iir & SDE_AUDIO_POWER_MASK) {
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
@@ -2386,9 +2405,17 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
I915_WRITE(GEN7_ERR_INT, err_int);
}
-static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
+static void cpt_serr_int_ack(struct drm_i915_private *dev_priv,
+ struct pch_irq_regs *pch)
{
- u32 serr_int = I915_READ(SERR_INT);
+ pch->serr_int = I915_READ(SERR_INT);
+ I915_WRITE(SERR_INT, pch->serr_int);
+}
+
+static void cpt_serr_int_handler(struct drm_i915_private *dev_priv,
+ const struct pch_irq_regs *pch)
+{
+ u32 serr_int = pch->serr_int;
enum pipe pipe;
if (serr_int & SERR_INT_POISON)
@@ -2397,19 +2424,26 @@ static void cpt_serr_int_handler(struct drm_i915_private *dev_priv)
for_each_pipe(dev_priv, pipe)
if (serr_int & SERR_INT_TRANS_FIFO_UNDERRUN(pipe))
intel_pch_fifo_underrun_irq_handler(dev_priv, pipe);
-
- I915_WRITE(SERR_INT, serr_int);
}
-static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+static void cpt_irq_ack(struct drm_i915_private *dev_priv,
+ struct pch_irq_regs *pch)
{
- struct hpd_irq_regs hpd = {};
- int pipe;
+ pch->hpd.hotplug_trigger = pch->iir & SDE_HOTPLUG_MASK_CPT;
+
+ ibx_hpd_irq_ack(dev_priv, &pch->hpd);
- hpd.hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
+ if (pch->iir & SDE_ERROR_CPT)
+ cpt_serr_int_ack(dev_priv, pch);
+}
+
+static void cpt_irq_handler(struct drm_i915_private *dev_priv,
+ const struct pch_irq_regs *pch)
+{
+ u32 pch_iir = pch->iir;
+ enum pipe pipe;
- ibx_hpd_irq_ack(dev_priv, &hpd);
- ibx_hpd_irq_handler(dev_priv, &hpd, hpd_cpt);
+ ibx_hpd_irq_handler(dev_priv, &pch->hpd, hpd_cpt);
if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
@@ -2437,33 +2471,41 @@ static void cpt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
I915_READ(FDI_RX_IIR(pipe)));
if (pch_iir & SDE_ERROR_CPT)
- cpt_serr_int_handler(dev_priv);
+ cpt_serr_int_handler(dev_priv, pch);
}
-static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+static void icp_irq_ack(struct drm_i915_private *dev_priv,
+ struct pch_irq_regs *pch)
{
- struct hpd_irq_regs ddi = {};
- struct hpd_irq_regs tc = {};
+ pch->ddi.hotplug_trigger = pch->iir & SDE_DDI_MASK_ICP;
+ pch->tc.hotplug_trigger = pch->iir & SDE_TC_MASK_ICP;
+
+ if (pch->ddi.hotplug_trigger) {
+ pch->ddi.dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
+ I915_WRITE(SHOTPLUG_CTL_DDI, pch->ddi.dig_hotplug_reg);
+ }
+
+ if (pch->tc.hotplug_trigger) {
+ pch->tc.dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
+ I915_WRITE(SHOTPLUG_CTL_TC, pch->tc.dig_hotplug_reg);
+ }
+}
+
+static void icp_irq_handler(struct drm_i915_private *dev_priv,
+ const struct pch_irq_regs *pch)
+{
+ u32 pch_iir = pch->iir;
u32 pin_mask = 0, long_mask = 0;
- ddi.hotplug_trigger = pch_iir & SDE_DDI_MASK_ICP;
- tc.hotplug_trigger = pch_iir & SDE_TC_MASK_ICP;
-
- if (ddi.hotplug_trigger) {
- ddi.dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_DDI);
- I915_WRITE(SHOTPLUG_CTL_DDI, ddi.dig_hotplug_reg);
-
+ if (pch->ddi.hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- &ddi, hpd_icp,
+ &pch->ddi, hpd_icp,
icp_ddi_port_hotplug_long_detect);
}
- if (tc.hotplug_trigger) {
- tc.dig_hotplug_reg = I915_READ(SHOTPLUG_CTL_TC);
- I915_WRITE(SHOTPLUG_CTL_TC, tc.dig_hotplug_reg);
-
+ if (pch->tc.hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- &tc, hpd_icp,
+ &pch->tc, hpd_icp,
icp_tc_port_hotplug_long_detect);
}
@@ -2474,31 +2516,39 @@ static void icp_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
gmbus_irq_handler(dev_priv);
}
-static void spt_irq_handler(struct drm_i915_private *dev_priv, u32 pch_iir)
+static void spt_irq_ack(struct drm_i915_private *dev_priv,
+ struct pch_irq_regs *pch)
{
- u32 pin_mask = 0, long_mask = 0;
- struct hpd_irq_regs hpd = {};
- struct hpd_irq_regs hpd2 = {};
-
- hpd.hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_SPT &
+ pch->hpd.hotplug_trigger = pch->iir & SDE_HOTPLUG_MASK_SPT &
~SDE_PORTE_HOTPLUG_SPT;
- hpd2.hotplug_trigger = pch_iir & SDE_PORTE_HOTPLUG_SPT;
+ pch->hpd2.hotplug_trigger = pch->iir & SDE_PORTE_HOTPLUG_SPT;
- if (hpd.hotplug_trigger) {
- hpd.dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
- I915_WRITE(PCH_PORT_HOTPLUG, hpd.dig_hotplug_reg);
+ if (pch->hpd.hotplug_trigger) {
+ pch->hpd.dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
+ I915_WRITE(PCH_PORT_HOTPLUG, pch->hpd.dig_hotplug_reg);
+ }
+ if (pch->hpd2.hotplug_trigger) {
+ pch->hpd2.dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
+ I915_WRITE(PCH_PORT_HOTPLUG2, pch->hpd2.dig_hotplug_reg);
+ }
+}
+
+static void spt_irq_handler(struct drm_i915_private *dev_priv,
+ const struct pch_irq_regs *pch)
+{
+ u32 pch_iir = pch->iir;
+ u32 pin_mask = 0, long_mask = 0;
+
+ if (pch->hpd.hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- &hpd, hpd_spt,
+ &pch->hpd, hpd_spt,
spt_port_hotplug_long_detect);
}
- if (hpd2.hotplug_trigger) {
- hpd2.dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG2);
- I915_WRITE(PCH_PORT_HOTPLUG2, hpd2.dig_hotplug_reg);
-
+ if (pch->hpd2.hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- &hpd2, hpd_spt,
+ &pch->hpd2, hpd_spt,
spt_port_hotplug2_long_detect);
}
@@ -2563,15 +2613,20 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
/* check event from PCH */
if (de_iir & DE_PCH_EVENT) {
- u32 pch_iir = I915_READ(SDEIIR);
+ struct pch_irq_regs pch = {};
- if (HAS_PCH_CPT(dev_priv))
- cpt_irq_handler(dev_priv, pch_iir);
- else
- ibx_irq_handler(dev_priv, pch_iir);
+ pch.iir = I915_READ(SDEIIR);
+
+ if (HAS_PCH_CPT(dev_priv)) {
+ cpt_irq_ack(dev_priv, &pch);
+ cpt_irq_handler(dev_priv, &pch);
+ } else {
+ ibx_irq_ack(dev_priv, &pch);
+ ibx_irq_handler(dev_priv, &pch);
+ }
/* should clear PCH hotplug event before clear CPU irq */
- I915_WRITE(SDEIIR, pch_iir);
+ I915_WRITE(SDEIIR, pch.iir);
}
if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
@@ -2613,12 +2668,15 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
/* check event from PCH */
if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
- u32 pch_iir = I915_READ(SDEIIR);
+ struct pch_irq_regs pch = {};
- cpt_irq_handler(dev_priv, pch_iir);
+ pch.iir = I915_READ(SDEIIR);
+
+ cpt_irq_ack(dev_priv, &pch);
+ cpt_irq_handler(dev_priv, &pch);
/* clear PCH hotplug event before clear CPU irq */
- I915_WRITE(SDEIIR, pch_iir);
+ I915_WRITE(SDEIIR, pch.iir);
}
}
@@ -2902,22 +2960,28 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
master_ctl & GEN8_DE_PCH_IRQ) {
+ struct pch_irq_regs pch = {};
+
/*
* FIXME(BDW): Assume for now that the new interrupt handling
* scheme also closed the SDE interrupt handling race we've seen
* on older pch-split platforms. But this needs testing.
*/
- iir = I915_READ(SDEIIR);
- if (iir) {
- I915_WRITE(SDEIIR, iir);
+ pch.iir = I915_READ(SDEIIR);
+ if (pch.iir) {
+ I915_WRITE(SDEIIR, pch.iir);
ret = IRQ_HANDLED;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
- icp_irq_handler(dev_priv, iir);
- else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
- spt_irq_handler(dev_priv, iir);
- else
- cpt_irq_handler(dev_priv, iir);
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
+ icp_irq_ack(dev_priv, &pch);
+ icp_irq_handler(dev_priv, &pch);
+ } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) {
+ spt_irq_ack(dev_priv, &pch);
+ spt_irq_handler(dev_priv, &pch);
+ } else {
+ cpt_irq_ack(dev_priv, &pch);
+ cpt_irq_handler(dev_priv, &pch);
+ }
} else {
/*
* Like on previous PCH there seems to be something
--
2.21.0
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^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 3/4] drm/i915: Split pch irq handling to ack+handler
2019-04-15 15:49 ` [PATCH 3/4] drm/i915: Split pch irq handling to ack+handler Ville Syrjala
@ 2019-04-15 16:48 ` Chris Wilson
2019-04-15 16:56 ` Ville Syrjälä
0 siblings, 1 reply; 15+ messages in thread
From: Chris Wilson @ 2019-04-15 16:48 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2019-04-15 16:49:03)
> @@ -2563,15 +2613,20 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
>
> /* check event from PCH */
> if (de_iir & DE_PCH_EVENT) {
> - u32 pch_iir = I915_READ(SDEIIR);
> + struct pch_irq_regs pch = {};
If I am following along correctly, we don't need the memset here as we
only ever check dependent members after a guard (such as the iir or
hotplug trigger).
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 3/4] drm/i915: Split pch irq handling to ack+handler
2019-04-15 16:48 ` Chris Wilson
@ 2019-04-15 16:56 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2019-04-15 16:56 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, Apr 15, 2019 at 05:48:04PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-15 16:49:03)
> > @@ -2563,15 +2613,20 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
> >
> > /* check event from PCH */
> > if (de_iir & DE_PCH_EVENT) {
> > - u32 pch_iir = I915_READ(SDEIIR);
> > + struct pch_irq_regs pch = {};
>
> If I am following along correctly, we don't need the memset here as we
> only ever check dependent members after a guard (such as the iir or
> hotplug trigger).
IIRC I did the zero inits to avoid false positives from the compiler
once these structs get hoisted up to the main irq handler. But I must
admit it's been a while since I wrote the basic form of this the memory
is getting hazy.
>
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
--
Ville Syrjälä
Intel
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^ permalink raw reply [flat|nested] 15+ messages in thread
* [PATCH 4/4] drm/i915: Finish the irq ack+handler split for ilk+
2019-04-15 15:49 [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Ville Syrjala
` (2 preceding siblings ...)
2019-04-15 15:49 ` [PATCH 3/4] drm/i915: Split pch irq handling to ack+handler Ville Syrjala
@ 2019-04-15 15:49 ` Ville Syrjala
2019-04-15 16:52 ` Chris Wilson
2019-04-15 15:55 ` [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Chris Wilson
` (2 subsequent siblings)
6 siblings, 1 reply; 15+ messages in thread
From: Ville Syrjala @ 2019-04-15 15:49 UTC (permalink / raw)
To: intel-gfx
From: Ville Syrjälä <ville.syrjala@linux.intel.com>
All the older platforms already follow the ack+handler apporoach
for interrupts. Convert ilk+ as well. As the number of registers
involved is rather large we'll introduce a few more structs to
carry the register values around.
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_irq.c | 445 +++++++++++++++++++++-----------
1 file changed, 295 insertions(+), 150 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index 14e0e9fe1853..6a437c7170b9 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -2276,6 +2276,13 @@ static irqreturn_t cherryview_irq_handler(int irq, void *arg)
return ret;
}
+struct ilk_de_irq_regs {
+ u32 iir;
+ u32 err_int; /* ivb/hsw */
+ u32 psr_iir; /* hsw */
+ struct hpd_irq_regs hpd;
+};
+
struct pch_irq_regs {
u32 iir;
u32 serr_int; /* cpt/lpt */
@@ -2382,9 +2389,17 @@ static void ibx_irq_handler(struct drm_i915_private *dev_priv,
intel_pch_fifo_underrun_irq_handler(dev_priv, PIPE_B);
}
-static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
+static void ivb_err_int_ack(struct drm_i915_private *dev_priv,
+ struct ilk_de_irq_regs *de)
{
- u32 err_int = I915_READ(GEN7_ERR_INT);
+ de->err_int = I915_READ(GEN7_ERR_INT);
+ I915_WRITE(GEN7_ERR_INT, de->err_int);
+}
+
+static void ivb_err_int_handler(struct drm_i915_private *dev_priv,
+ const struct ilk_de_irq_regs *de)
+{
+ u32 err_int = de->err_int;
enum pipe pipe;
if (err_int & ERR_INT_POISON)
@@ -2401,8 +2416,6 @@ static void ivb_err_int_handler(struct drm_i915_private *dev_priv)
hsw_pipe_crc_irq_handler(dev_priv, pipe);
}
}
-
- I915_WRITE(GEN7_ERR_INT, err_int);
}
static void cpt_serr_int_ack(struct drm_i915_private *dev_priv,
@@ -2579,17 +2592,38 @@ static void ilk_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
+static void ilk_display_irq_ack(struct drm_i915_private *dev_priv,
+ struct ilk_de_irq_regs *de,
+ struct pch_irq_regs *pch)
+{
+ de->hpd.hotplug_trigger = de->iir & DE_DP_A_HOTPLUG;
+
+ if (de->hpd.hotplug_trigger)
+ ilk_hpd_irq_ack(dev_priv, &de->hpd);
+
+ /* check event from PCH */
+ if (de->iir & DE_PCH_EVENT) {
+ pch->iir = I915_READ(SDEIIR);
+
+ if (HAS_PCH_CPT(dev_priv))
+ cpt_irq_ack(dev_priv, pch);
+ else
+ ibx_irq_ack(dev_priv, pch);
+
+ /* should clear PCH hotplug event before clear CPU irq */
+ I915_WRITE(SDEIIR, pch->iir);
+ }
+}
+
static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
- u32 de_iir)
+ const struct ilk_de_irq_regs *de,
+ const struct pch_irq_regs *pch)
{
- struct hpd_irq_regs hpd = {};
+ u32 de_iir = de->iir;
enum pipe pipe;
- hpd.hotplug_trigger = de_iir & DE_DP_A_HOTPLUG;
- if (hpd.hotplug_trigger) {
- ilk_hpd_irq_ack(dev_priv, &hpd);
- ilk_hpd_irq_handler(dev_priv, &hpd, hpd_ilk);
- }
+ if (de->hpd.hotplug_trigger)
+ ilk_hpd_irq_handler(dev_priv, &de->hpd, hpd_ilk);
if (de_iir & DE_AUX_CHANNEL_A)
dp_aux_irq_handler(dev_priv);
@@ -2613,47 +2647,65 @@ static void ilk_display_irq_handler(struct drm_i915_private *dev_priv,
/* check event from PCH */
if (de_iir & DE_PCH_EVENT) {
- struct pch_irq_regs pch = {};
-
- pch.iir = I915_READ(SDEIIR);
-
- if (HAS_PCH_CPT(dev_priv)) {
- cpt_irq_ack(dev_priv, &pch);
- cpt_irq_handler(dev_priv, &pch);
- } else {
- ibx_irq_ack(dev_priv, &pch);
- ibx_irq_handler(dev_priv, &pch);
- }
-
- /* should clear PCH hotplug event before clear CPU irq */
- I915_WRITE(SDEIIR, pch.iir);
+ if (HAS_PCH_CPT(dev_priv))
+ cpt_irq_handler(dev_priv, pch);
+ else
+ ibx_irq_handler(dev_priv, pch);
}
if (IS_GEN(dev_priv, 5) && de_iir & DE_PCU_EVENT)
ironlake_rps_change_irq_handler(dev_priv);
}
+static void hsw_psr_irq_ack(struct drm_i915_private *dev_priv,
+ u32 *psr_iir)
+{
+ *psr_iir = I915_READ(EDP_PSR_IIR);
+ if (*psr_iir)
+ I915_WRITE(EDP_PSR_IIR, *psr_iir);
+}
+
+static void ivb_display_irq_ack(struct drm_i915_private *dev_priv,
+ struct ilk_de_irq_regs *de,
+ struct pch_irq_regs *pch)
+{
+ de->hpd.hotplug_trigger = de->iir & DE_DP_A_HOTPLUG_IVB;
+
+ if (de->hpd.hotplug_trigger)
+ ilk_hpd_irq_ack(dev_priv, &de->hpd);
+
+ if (de->iir & DE_ERR_INT_IVB)
+ ivb_err_int_ack(dev_priv, de);
+
+ if (de->iir & DE_EDP_PSR_INT_HSW)
+ hsw_psr_irq_ack(dev_priv, &de->psr_iir);
+
+ /* check event from PCH */
+ if (!HAS_PCH_NOP(dev_priv) && de->iir & DE_PCH_EVENT_IVB) {
+ pch->iir = I915_READ(SDEIIR);
+
+ cpt_irq_ack(dev_priv, pch);
+
+ /* clear PCH hotplug event before clear CPU irq */
+ I915_WRITE(SDEIIR, pch->iir);
+ }
+}
+
static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
- u32 de_iir)
+ const struct ilk_de_irq_regs *de,
+ const struct pch_irq_regs *pch)
{
- struct hpd_irq_regs hpd = {};
+ u32 de_iir = de->iir;
enum pipe pipe;
- hpd.hotplug_trigger = de_iir & DE_DP_A_HOTPLUG_IVB;
- if (hpd.hotplug_trigger) {
- ilk_hpd_irq_ack(dev_priv, &hpd);
- ilk_hpd_irq_handler(dev_priv, &hpd, hpd_ivb);
- }
+ if (de->hpd.hotplug_trigger)
+ ilk_hpd_irq_handler(dev_priv, &de->hpd, hpd_ivb);
if (de_iir & DE_ERR_INT_IVB)
- ivb_err_int_handler(dev_priv);
+ ivb_err_int_handler(dev_priv, de);
- if (de_iir & DE_EDP_PSR_INT_HSW) {
- u32 psr_iir = I915_READ(EDP_PSR_IIR);
-
- intel_psr_irq_handler(dev_priv, psr_iir);
- I915_WRITE(EDP_PSR_IIR, psr_iir);
- }
+ if (de_iir & DE_EDP_PSR_INT_HSW)
+ intel_psr_irq_handler(dev_priv, de->psr_iir);
if (de_iir & DE_AUX_CHANNEL_A_IVB)
dp_aux_irq_handler(dev_priv);
@@ -2662,22 +2714,13 @@ static void ivb_display_irq_handler(struct drm_i915_private *dev_priv,
intel_opregion_asle_intr(dev_priv);
for_each_pipe(dev_priv, pipe) {
- if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)))
+ if (de_iir & DE_PIPE_VBLANK_IVB(pipe))
drm_handle_vblank(&dev_priv->drm, pipe);
}
/* check event from PCH */
- if (!HAS_PCH_NOP(dev_priv) && (de_iir & DE_PCH_EVENT_IVB)) {
- struct pch_irq_regs pch = {};
-
- pch.iir = I915_READ(SDEIIR);
-
- cpt_irq_ack(dev_priv, &pch);
- cpt_irq_handler(dev_priv, &pch);
-
- /* clear PCH hotplug event before clear CPU irq */
- I915_WRITE(SDEIIR, pch.iir);
- }
+ if (!HAS_PCH_NOP(dev_priv) && de_iir & DE_PCH_EVENT_IVB)
+ cpt_irq_handler(dev_priv, pch);
}
/*
@@ -2692,7 +2735,9 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
{
struct drm_device *dev = arg;
struct drm_i915_private *dev_priv = to_i915(dev);
- u32 de_iir, gt_iir, de_ier, sde_ier = 0;
+ u32 gt_iir, pm_iir = 0, de_ier, sde_ier = 0;
+ struct ilk_de_irq_regs de = {};
+ struct pch_irq_regs pch = {};
irqreturn_t ret = IRQ_NONE;
if (!intel_irqs_enabled(dev_priv))
@@ -2718,38 +2763,50 @@ static irqreturn_t ironlake_irq_handler(int irq, void *arg)
/* Find, clear, then process each source of interrupt */
gt_iir = I915_READ(GTIIR);
- if (gt_iir) {
+ de.iir = I915_READ(DEIIR);
+ if (INTEL_GEN(dev_priv) >= 6)
+ pm_iir = I915_READ(GEN6_PMIIR);
+
+ if (gt_iir)
I915_WRITE(GTIIR, gt_iir);
- ret = IRQ_HANDLED;
- if (INTEL_GEN(dev_priv) >= 6)
- snb_gt_irq_handler(dev_priv, gt_iir);
- else
- ilk_gt_irq_handler(dev_priv, gt_iir);
- }
- de_iir = I915_READ(DEIIR);
- if (de_iir) {
- I915_WRITE(DEIIR, de_iir);
- ret = IRQ_HANDLED;
+ if (de.iir) {
if (INTEL_GEN(dev_priv) >= 7)
- ivb_display_irq_handler(dev_priv, de_iir);
+ ivb_display_irq_ack(dev_priv, &de, &pch);
else
- ilk_display_irq_handler(dev_priv, de_iir);
- }
+ ilk_display_irq_ack(dev_priv, &de, &pch);
- if (INTEL_GEN(dev_priv) >= 6) {
- u32 pm_iir = I915_READ(GEN6_PMIIR);
- if (pm_iir) {
- I915_WRITE(GEN6_PMIIR, pm_iir);
- ret = IRQ_HANDLED;
- gen6_rps_irq_handler(dev_priv, pm_iir);
- }
+ I915_WRITE(DEIIR, de.iir);
}
+ if (pm_iir)
+ I915_WRITE(GEN6_PMIIR, pm_iir);
+
I915_WRITE(DEIER, de_ier);
if (!HAS_PCH_NOP(dev_priv))
I915_WRITE(SDEIER, sde_ier);
+ if (gt_iir) {
+ ret = IRQ_HANDLED;
+ if (INTEL_GEN(dev_priv) >= 6)
+ snb_gt_irq_handler(dev_priv, gt_iir);
+ else
+ ilk_gt_irq_handler(dev_priv, gt_iir);
+ }
+
+ if (de.iir) {
+ ret = IRQ_HANDLED;
+ if (INTEL_GEN(dev_priv) >= 7)
+ ivb_display_irq_handler(dev_priv, &de, &pch);
+ else
+ ilk_display_irq_handler(dev_priv, &de, &pch);
+ }
+
+ if (pm_iir) {
+ ret = IRQ_HANDLED;
+ gen6_rps_irq_handler(dev_priv, pm_iir);
+ }
+
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
enable_rpm_wakeref_asserts(dev_priv);
@@ -2776,37 +2833,129 @@ static void bxt_hpd_irq_handler(struct drm_i915_private *dev_priv,
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
}
-static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv, u32 iir)
+struct gen8_de_irq_regs {
+ u32 pipe_iir[I915_MAX_PIPES];
+ u32 port_iir;
+ u32 misc_iir;
+ u32 psr_iir;
+ u32 hpd_iir; /* icl+ */
+ struct hpd_irq_regs ddi;
+ struct hpd_irq_regs tc, tbt; /* icl+ */
+};
+
+static void gen11_hpd_irq_ack(struct drm_i915_private *dev_priv,
+ struct gen8_de_irq_regs *de)
+{
+ de->tc.hotplug_trigger = de->hpd_iir & GEN11_DE_TC_HOTPLUG_MASK;
+ de->tbt.hotplug_trigger = de->hpd_iir & GEN11_DE_TBT_HOTPLUG_MASK;
+
+ if (de->tc.hotplug_trigger) {
+ de->tc.dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
+ I915_WRITE(GEN11_TC_HOTPLUG_CTL, de->tc.dig_hotplug_reg);
+ }
+
+ if (de->tbt.hotplug_trigger) {
+ de->tbt.dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
+ I915_WRITE(GEN11_TBT_HOTPLUG_CTL, de->tbt.dig_hotplug_reg);
+ }
+}
+
+static void gen11_hpd_irq_handler(struct drm_i915_private *dev_priv,
+ const struct gen8_de_irq_regs *de)
{
- struct hpd_irq_regs tc = {};
- struct hpd_irq_regs tbt = {};
u32 pin_mask = 0, long_mask = 0;
- tc.hotplug_trigger = iir & GEN11_DE_TC_HOTPLUG_MASK;
- tbt.hotplug_trigger = iir & GEN11_DE_TBT_HOTPLUG_MASK;
-
- if (tc.hotplug_trigger) {
- tc.dig_hotplug_reg = I915_READ(GEN11_TC_HOTPLUG_CTL);
- I915_WRITE(GEN11_TC_HOTPLUG_CTL, tc.dig_hotplug_reg);
-
+ if (de->tc.hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- &tc, hpd_gen11,
+ &de->tc, hpd_gen11,
gen11_port_hotplug_long_detect);
}
- if (tbt.hotplug_trigger) {
- tbt.dig_hotplug_reg = I915_READ(GEN11_TBT_HOTPLUG_CTL);
- I915_WRITE(GEN11_TBT_HOTPLUG_CTL, tbt.dig_hotplug_reg);
-
+ if (de->tbt.hotplug_trigger) {
intel_get_hpd_pins(dev_priv, &pin_mask, &long_mask,
- &tbt, hpd_gen11,
+ &de->tbt, hpd_gen11,
gen11_port_hotplug_long_detect);
}
if (pin_mask)
intel_hpd_irq_handler(dev_priv, pin_mask, long_mask);
else
- DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", iir);
+ DRM_ERROR("Unexpected DE HPD interrupt 0x%08x\n", de->hpd_iir);
+}
+
+static void
+gen8_de_irq_ack(struct drm_i915_private *dev_priv, u32 master_ctl,
+ struct gen8_de_irq_regs *de, struct pch_irq_regs *pch)
+{
+ enum pipe pipe;
+
+ if (master_ctl & GEN8_DE_MISC_IRQ) {
+ de->misc_iir = I915_READ(GEN8_DE_MISC_IIR);
+
+ if (de->misc_iir) {
+ if (de->misc_iir & GEN8_DE_EDP_PSR)
+ hsw_psr_irq_ack(dev_priv, &de->psr_iir);
+
+ I915_WRITE(GEN8_DE_MISC_IIR, de->misc_iir);
+ }
+ }
+
+ if (INTEL_GEN(dev_priv) >= 11 && master_ctl & GEN11_DE_HPD_IRQ) {
+ de->hpd_iir = I915_READ(GEN11_DE_HPD_IIR);
+
+ if (de->hpd_iir) {
+ gen11_hpd_irq_ack(dev_priv, de);
+
+ I915_WRITE(GEN11_DE_HPD_IIR, de->hpd_iir);
+ }
+ }
+
+ if (master_ctl & GEN8_DE_PORT_IRQ) {
+ de->port_iir = I915_READ(GEN8_DE_PORT_IIR);
+
+ if (de->port_iir) {
+ if (IS_GEN9_LP(dev_priv)) {
+ de->ddi.hotplug_trigger = de->port_iir & BXT_DE_PORT_HOTPLUG_MASK;
+ if (de->ddi.hotplug_trigger)
+ bxt_hpd_irq_ack(dev_priv, &de->ddi);
+ } else if (IS_BROADWELL(dev_priv)) {
+ de->ddi.hotplug_trigger = de->port_iir & GEN8_PORT_DP_A_HOTPLUG;
+ if (de->ddi.hotplug_trigger)
+ ilk_hpd_irq_ack(dev_priv, &de->ddi);
+ }
+
+ I915_WRITE(GEN8_DE_PORT_IIR, de->port_iir);
+ }
+ }
+
+ for_each_pipe(dev_priv, pipe) {
+ if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
+ continue;
+
+ de->pipe_iir[pipe] = I915_READ(GEN8_DE_PIPE_IIR(pipe));
+ if (de->pipe_iir[pipe])
+ I915_WRITE(GEN8_DE_PIPE_IIR(pipe), de->pipe_iir[pipe]);
+ }
+
+ if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
+ master_ctl & GEN8_DE_PCH_IRQ) {
+ /*
+ * FIXME(BDW): Assume for now that the new interrupt handling
+ * scheme also closed the SDE interrupt handling race we've seen
+ * on older pch-split platforms. But this needs testing.
+ */
+ pch->iir = I915_READ(SDEIIR);
+ if (pch->iir) {
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_ack(dev_priv, pch);
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
+ spt_irq_ack(dev_priv, pch);
+ else
+ cpt_irq_ack(dev_priv, pch);
+
+ I915_WRITE(SDEIIR, pch->iir);
+ }
+ }
}
static u32 gen8_de_port_aux_mask(struct drm_i915_private *dev_priv)
@@ -2837,57 +2986,51 @@ static u32 gen8_de_pipe_fault_mask(struct drm_i915_private *dev_priv)
}
static irqreturn_t
-gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
+gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl,
+ const struct gen8_de_irq_regs *de,
+ const struct pch_irq_regs *pch)
{
irqreturn_t ret = IRQ_NONE;
- u32 iir;
enum pipe pipe;
if (master_ctl & GEN8_DE_MISC_IRQ) {
- iir = I915_READ(GEN8_DE_MISC_IIR);
+ u32 iir = de->misc_iir;
+
if (iir) {
bool found = false;
- I915_WRITE(GEN8_DE_MISC_IIR, iir);
- ret = IRQ_HANDLED;
-
if (iir & GEN8_DE_MISC_GSE) {
intel_opregion_asle_intr(dev_priv);
found = true;
}
if (iir & GEN8_DE_EDP_PSR) {
- u32 psr_iir = I915_READ(EDP_PSR_IIR);
-
- intel_psr_irq_handler(dev_priv, psr_iir);
- I915_WRITE(EDP_PSR_IIR, psr_iir);
+ intel_psr_irq_handler(dev_priv, de->psr_iir);
found = true;
}
if (!found)
DRM_ERROR("Unexpected DE Misc interrupt\n");
- }
- else
+ } else {
DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
+ }
}
if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
- iir = I915_READ(GEN11_DE_HPD_IIR);
- if (iir) {
- I915_WRITE(GEN11_DE_HPD_IIR, iir);
- ret = IRQ_HANDLED;
- gen11_hpd_irq_handler(dev_priv, iir);
- } else {
+ u32 iir = de->hpd_iir;
+
+ if (iir)
+ gen11_hpd_irq_handler(dev_priv, de);
+ else
DRM_ERROR("The master control interrupt lied, (DE HPD)!\n");
- }
}
if (master_ctl & GEN8_DE_PORT_IRQ) {
- iir = I915_READ(GEN8_DE_PORT_IIR);
+ u32 iir = de->port_iir;
+
if (iir) {
bool found = false;
- I915_WRITE(GEN8_DE_PORT_IIR, iir);
ret = IRQ_HANDLED;
if (iir & gen8_de_port_aux_mask(dev_priv)) {
@@ -2895,24 +3038,12 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
found = true;
}
- if (IS_GEN9_LP(dev_priv)) {
- struct hpd_irq_regs ddi = {};
-
- ddi.hotplug_trigger = iir & BXT_DE_PORT_HOTPLUG_MASK;
- if (ddi.hotplug_trigger) {
- bxt_hpd_irq_ack(dev_priv, &ddi);
- bxt_hpd_irq_handler(dev_priv, &ddi, hpd_bxt);
- found = true;
- }
- } else if (IS_BROADWELL(dev_priv)) {
- struct hpd_irq_regs ddi = {};
-
- ddi.hotplug_trigger = iir & GEN8_PORT_DP_A_HOTPLUG;
- if (ddi.hotplug_trigger) {
- ilk_hpd_irq_ack(dev_priv, &ddi);
- ilk_hpd_irq_handler(dev_priv, &ddi, hpd_bdw);
- found = true;
- }
+ if (IS_GEN9_LP(dev_priv) && de->ddi.hotplug_trigger) {
+ bxt_hpd_irq_handler(dev_priv, &de->ddi, hpd_bxt);
+ found = true;
+ } else if (IS_BROADWELL(dev_priv) && de->ddi.hotplug_trigger) {
+ ilk_hpd_irq_handler(dev_priv, &de->ddi, hpd_bdw);
+ found = true;
}
if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
@@ -2922,25 +3053,24 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (!found)
DRM_ERROR("Unexpected DE Port interrupt\n");
- }
- else
+ } else {
DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
+ }
}
for_each_pipe(dev_priv, pipe) {
+ u32 iir = de->pipe_iir[pipe];
u32 fault_errors;
if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
continue;
- iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
if (!iir) {
DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
continue;
}
ret = IRQ_HANDLED;
- I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
if (iir & GEN8_PIPE_VBLANK)
drm_handle_vblank(&dev_priv->drm, pipe);
@@ -2960,28 +3090,22 @@ gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) &&
master_ctl & GEN8_DE_PCH_IRQ) {
- struct pch_irq_regs pch = {};
+ u32 iir = pch->iir;
/*
* FIXME(BDW): Assume for now that the new interrupt handling
* scheme also closed the SDE interrupt handling race we've seen
* on older pch-split platforms. But this needs testing.
*/
- pch.iir = I915_READ(SDEIIR);
- if (pch.iir) {
- I915_WRITE(SDEIIR, pch.iir);
+ if (iir) {
ret = IRQ_HANDLED;
- if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP) {
- icp_irq_ack(dev_priv, &pch);
- icp_irq_handler(dev_priv, &pch);
- } else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT) {
- spt_irq_ack(dev_priv, &pch);
- spt_irq_handler(dev_priv, &pch);
- } else {
- cpt_irq_ack(dev_priv, &pch);
- cpt_irq_handler(dev_priv, &pch);
- }
+ if (INTEL_PCH_TYPE(dev_priv) >= PCH_ICP)
+ icp_irq_handler(dev_priv, pch);
+ else if (INTEL_PCH_TYPE(dev_priv) >= PCH_SPT)
+ spt_irq_handler(dev_priv, pch);
+ else
+ cpt_irq_handler(dev_priv, pch);
} else {
/*
* Like on previous PCH there seems to be something
@@ -3018,6 +3142,8 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
void __iomem * const regs = dev_priv->uncore.regs;
u32 master_ctl;
u32 gt_iir[4];
+ struct gen8_de_irq_regs de = {};
+ struct pch_irq_regs pch = {};
if (!intel_irqs_enabled(dev_priv))
return IRQ_NONE;
@@ -3034,7 +3160,7 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & ~GEN8_GT_IRQS) {
disable_rpm_wakeref_asserts(dev_priv);
- gen8_de_irq_handler(dev_priv, master_ctl);
+ gen8_de_irq_ack(dev_priv, master_ctl, &de, &pch);
enable_rpm_wakeref_asserts(dev_priv);
}
@@ -3042,6 +3168,12 @@ static irqreturn_t gen8_irq_handler(int irq, void *arg)
gen8_gt_irq_handler(dev_priv, master_ctl, gt_iir);
+ if (master_ctl & ~GEN8_GT_IRQS) {
+ disable_rpm_wakeref_asserts(dev_priv);
+ gen8_de_irq_handler(dev_priv, master_ctl, &de, &pch);
+ enable_rpm_wakeref_asserts(dev_priv);
+ }
+
return IRQ_HANDLED;
}
@@ -3214,6 +3346,9 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
void __iomem * const regs = i915->uncore.regs;
u32 master_ctl;
u32 gu_misc_iir;
+ u32 disp_ctl = 0;
+ struct gen8_de_irq_regs de = {};
+ struct pch_irq_regs pch = {};
if (!intel_irqs_enabled(i915))
return IRQ_NONE;
@@ -3229,14 +3364,14 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
/* IRQs are synced during runtime_suspend, we don't require a wakeref */
if (master_ctl & GEN11_DISPLAY_IRQ) {
- const u32 disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
+ disp_ctl = raw_reg_read(regs, GEN11_DISPLAY_INT_CTL);
disable_rpm_wakeref_asserts(i915);
/*
* GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
* for the display related bits.
*/
- gen8_de_irq_handler(i915, disp_ctl);
+ gen8_de_irq_ack(i915, disp_ctl, &de, &pch);
enable_rpm_wakeref_asserts(i915);
}
@@ -3244,6 +3379,16 @@ static irqreturn_t gen11_irq_handler(int irq, void *arg)
gen11_master_intr_enable(regs);
+ if (master_ctl & GEN11_DISPLAY_IRQ) {
+ disable_rpm_wakeref_asserts(i915);
+ /*
+ * GEN11_DISPLAY_INT_CTL has same format as GEN8_MASTER_IRQ
+ * for the display related bits.
+ */
+ gen8_de_irq_handler(i915, disp_ctl, &de, &pch);
+ enable_rpm_wakeref_asserts(i915);
+ }
+
gen11_gu_misc_irq_handler(i915, gu_misc_iir);
return IRQ_HANDLED;
--
2.21.0
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 15+ messages in thread* Re: [PATCH 4/4] drm/i915: Finish the irq ack+handler split for ilk+
2019-04-15 15:49 ` [PATCH 4/4] drm/i915: Finish the irq ack+handler split for ilk+ Ville Syrjala
@ 2019-04-15 16:52 ` Chris Wilson
2019-04-15 17:04 ` Ville Syrjälä
0 siblings, 1 reply; 15+ messages in thread
From: Chris Wilson @ 2019-04-15 16:52 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2019-04-15 16:49:04)
> static irqreturn_t
> -gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> +gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl,
> + const struct gen8_de_irq_regs *de,
> + const struct pch_irq_regs *pch)
> {
> }
>
> if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
Can GEN11_DE_HPD_IRQ be raised on any other platform?
Lgtm,
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 4/4] drm/i915: Finish the irq ack+handler split for ilk+
2019-04-15 16:52 ` Chris Wilson
@ 2019-04-15 17:04 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2019-04-15 17:04 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, Apr 15, 2019 at 05:52:51PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-15 16:49:04)
> > static irqreturn_t
> > -gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl)
> > +gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl,
> > + const struct gen8_de_irq_regs *de,
> > + const struct pch_irq_regs *pch)
> > {
> > }
> >
> > if (INTEL_GEN(dev_priv) >= 11 && (master_ctl & GEN11_DE_HPD_IRQ)) {
>
> Can GEN11_DE_HPD_IRQ be raised on any other platform?
Looks like the bit wasn't used pre-icl.
>
> Lgtm,
> Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
> -Chris
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler
2019-04-15 15:49 [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Ville Syrjala
` (3 preceding siblings ...)
2019-04-15 15:49 ` [PATCH 4/4] drm/i915: Finish the irq ack+handler split for ilk+ Ville Syrjala
@ 2019-04-15 15:55 ` Chris Wilson
2019-04-15 16:36 ` Ville Syrjälä
2019-04-15 16:33 ` ✓ Fi.CI.BAT: success for " Patchwork
2019-04-15 18:25 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 1 reply; 15+ messages in thread
From: Chris Wilson @ 2019-04-15 15:55 UTC (permalink / raw)
To: Ville Syrjala, intel-gfx
Quoting Ville Syrjala (2019-04-15 16:49:00)
> From: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> I never finished the irq ack+handler split for ilk+. Let's try to do
> that now since people seem keen on cleaning up stuff in there. One
> thing I didn't dare touch is gen11_gt_irq_handler() as that thing
> looks a bit nuts.
>
> A bit of a downside:
> Total: Before=39303, After=40393, chg +2.77%
>
> If we changed all _ack()s to raw_reg_{read,write} we'd get:
> Total: Before=39303, After=39258, chg -0.11%
> but that ignores the "hang when accessing registers in the
> same cacheline" fail. So would need a bit more thought.
Otoh, all irq registers should be guarded by either the
dev_priv->irq_lock spinlock or be single threaded by the nature of
interrupt dispatch (handwavy). So we might be able to argue that for the
limited set of registers accessed here, we should be safe.
-Chris
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* Re: [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler
2019-04-15 15:55 ` [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Chris Wilson
@ 2019-04-15 16:36 ` Ville Syrjälä
0 siblings, 0 replies; 15+ messages in thread
From: Ville Syrjälä @ 2019-04-15 16:36 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Mon, Apr 15, 2019 at 04:55:25PM +0100, Chris Wilson wrote:
> Quoting Ville Syrjala (2019-04-15 16:49:00)
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > I never finished the irq ack+handler split for ilk+. Let's try to do
> > that now since people seem keen on cleaning up stuff in there. One
> > thing I didn't dare touch is gen11_gt_irq_handler() as that thing
> > looks a bit nuts.
> >
> > A bit of a downside:
> > Total: Before=39303, After=40393, chg +2.77%
> >
> > If we changed all _ack()s to raw_reg_{read,write} we'd get:
> > Total: Before=39303, After=39258, chg -0.11%
> > but that ignores the "hang when accessing registers in the
> > same cacheline" fail. So would need a bit more thought.
>
> Otoh, all irq registers should be guarded by either the
> dev_priv->irq_lock spinlock or be single threaded by the nature of
> interrupt dispatch (handwavy). So we might be able to argue that for the
> limited set of registers accessed here, we should be safe.
Hmm. Yes, I suppose you are correct. The only thing that might bite us
is some unguarded READ_FW()s etc. I guess we can hope those don't exist.
At least I can't immediately spot anything that looks dangerous.
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread
* ✓ Fi.CI.BAT: success for drm/i915: Finish the ack+handler split for irq handler
2019-04-15 15:49 [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Ville Syrjala
` (4 preceding siblings ...)
2019-04-15 15:55 ` [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Chris Wilson
@ 2019-04-15 16:33 ` Patchwork
2019-04-15 18:25 ` ✓ Fi.CI.IGT: " Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2019-04-15 16:33 UTC (permalink / raw)
To: Ville Syrjala; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Finish the ack+handler split for irq handler
URL : https://patchwork.freedesktop.org/series/59512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934 -> Patchwork_12802
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59512/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12802 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@i915_selftest@live_execlists:
- fi-apl-guc: PASS -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-a:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +1
* igt@kms_chamelium@hdmi-crc-fast:
- fi-bsw-n3050: NOTRUN -> SKIP [fdo#109271] +57
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- fi-glk-dsi: PASS -> INCOMPLETE [fdo#103359] / [k.org#198133]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-byt-clapper: PASS -> FAIL [fdo#103191]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@i915_selftest@live_contexts:
- fi-bdw-gvtdvm: DMESG-FAIL [fdo#110235 ] -> PASS
* igt@i915_selftest@live_hangcheck:
- fi-skl-iommu: INCOMPLETE [fdo#108602] / [fdo#108744] -> PASS
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: FAIL [fdo#103191] -> PASS
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103359]: https://bugs.freedesktop.org/show_bug.cgi?id=103359
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108602]: https://bugs.freedesktop.org/show_bug.cgi?id=108602
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#108744]: https://bugs.freedesktop.org/show_bug.cgi?id=108744
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110235 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110235
[k.org#198133]: https://bugzilla.kernel.org/show_bug.cgi?id=198133
Participating hosts (50 -> 42)
------------------------------
Additional (1): fi-bsw-n3050
Missing (9): fi-kbl-soraka fi-ilk-m540 fi-byt-squawks fi-icl-u2 fi-bsw-cyan fi-ctg-p8600 fi-icl-dsi fi-bdw-samus fi-snb-2600
Build changes
-------------
* Linux: CI_DRM_5934 -> Patchwork_12802
CI_DRM_5934: cc5334c0e706ec423c5f1a139cf3da7bd3287db6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4946: 56bdc68638cec64c6b02cd6b220b52b76059b51a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12802: 3095d2548755ef26f4a6c695d268060e25a49644 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
3095d2548755 drm/i915: Finish the irq ack+handler split for ilk+
add2118deabe drm/i915: Split pch irq handling to ack+handler
019e6bc3ba8a drm/i915: Introduce struct hpd_irq_regs
132f7567cc34 drm/i915: Add gen8_de_pipe_fault_mask()
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12802/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread* ✓ Fi.CI.IGT: success for drm/i915: Finish the ack+handler split for irq handler
2019-04-15 15:49 [PATCH 0/4] drm/i915: Finish the ack+handler split for irq handler Ville Syrjala
` (5 preceding siblings ...)
2019-04-15 16:33 ` ✓ Fi.CI.BAT: success for " Patchwork
@ 2019-04-15 18:25 ` Patchwork
6 siblings, 0 replies; 15+ messages in thread
From: Patchwork @ 2019-04-15 18:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Finish the ack+handler split for irq handler
URL : https://patchwork.freedesktop.org/series/59512/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5934_full -> Patchwork_12802_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Known issues
------------
Here are the changes found in Patchwork_12802_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@unwedge-stress:
- shard-snb: PASS -> FAIL [fdo#109661]
* igt@gem_exec_parse@basic-allowed:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
* igt@gem_exec_schedule@independent-bsd1:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +6
* igt@gem_pread@stolen-uncached:
- shard-iclb: NOTRUN -> SKIP [fdo#109277]
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: PASS -> FAIL [fdo#108686]
* igt@gem_userptr_blits@coherency-unsync:
- shard-iclb: NOTRUN -> SKIP [fdo#109290]
* igt@i915_pm_rpm@gem-evict-pwrite:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@i915_query@query-topology-known-pci-ids:
- shard-iclb: NOTRUN -> SKIP [fdo#109303]
* igt@i915_selftest@live_workarounds:
- shard-iclb: PASS -> DMESG-FAIL [fdo#108954]
* igt@i915_suspend@fence-restore-untiled:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +2
* igt@kms_atomic_transition@2x-modeset-transitions-nonblocking:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] +21
* igt@kms_busy@basic-modeset-f:
- shard-apl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_busy@extended-pageflip-hang-newfb-render-f:
- shard-kbl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_chamelium@hdmi-hpd-storm:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +2
* igt@kms_content_protection@atomic-dpms:
- shard-apl: NOTRUN -> FAIL [fdo#110321] / [fdo#110336]
* igt@kms_cursor_crc@cursor-512x512-random:
- shard-iclb: NOTRUN -> SKIP [fdo#109279]
* igt@kms_draw_crc@draw-method-xrgb8888-blt-ytiled:
- shard-glk: PASS -> FAIL [fdo#103184] / [fdo#107589]
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-iclb: NOTRUN -> SKIP [fdo#109274]
* igt@kms_flip@absolute-wf_vblank-interruptible:
- shard-apl: PASS -> DMESG-WARN [fdo#110376]
* igt@kms_flip@flip-vs-expired-vblank:
- shard-glk: PASS -> FAIL [fdo#102887] / [fdo#105363]
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-pri-indfb-draw-pwrite:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +53
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-indfb-draw-blt:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +5
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-mmap-gtt:
- shard-iclb: PASS -> FAIL [fdo#109247] +18
* igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-cur-indfb-draw-render:
- shard-iclb: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-cur-indfb-move:
- shard-apl: NOTRUN -> SKIP [fdo#109271] +22
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +3
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
- shard-kbl: PASS -> DMESG-WARN [fdo#108566]
* igt@kms_plane_alpha_blend@pipe-c-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +1
* igt@kms_psr@cursor_mmap_gtt:
- shard-iclb: PASS -> FAIL [fdo#107383] / [fdo#110215] +3
* igt@kms_psr@psr2_cursor_plane_move:
- shard-iclb: NOTRUN -> SKIP [fdo#109441]
* igt@kms_rotation_crc@multiplane-rotation-cropping-bottom:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_universal_plane@disable-primary-vs-flip-pipe-d:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +1
* igt@kms_vblank@pipe-a-ts-continuation-dpms-suspend:
- shard-skl: PASS -> INCOMPLETE [fdo#104108]
* igt@v3d_get_bo_offset@create-get-offsets:
- shard-iclb: NOTRUN -> SKIP [fdo#109315]
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s3:
- shard-kbl: DMESG-WARN [fdo#108566] -> PASS +1
* igt@i915_pm_rpm@i2c:
- shard-iclb: FAIL [fdo#104097] -> PASS
* igt@kms_flip@flip-vs-expired-vblank-interruptible:
- shard-glk: FAIL [fdo#102887] / [fdo#105363] -> PASS
* igt@kms_flip@modeset-vs-vblank-race:
- shard-glk: FAIL [fdo#103060] -> PASS
* igt@kms_flip_tiling@flip-to-x-tiled:
- shard-skl: FAIL [fdo#108134] -> PASS
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-iclb: FAIL [fdo#103167] -> PASS +5
* igt@kms_frontbuffer_tracking@fbc-suspend:
- shard-skl: FAIL [fdo#108040] -> PASS
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-blt:
- shard-iclb: FAIL [fdo#109247] -> PASS +23
* igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-pwrite:
- shard-skl: FAIL [fdo#103167] -> PASS
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +2
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
- shard-skl: FAIL [fdo#108145] -> PASS +1
* igt@kms_plane_lowres@pipe-a-tiling-y:
- shard-iclb: FAIL [fdo#103166] -> PASS
* igt@kms_plane_scaling@pipe-b-scaler-with-pixel-format:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: SKIP [fdo#109441] -> PASS +2
* igt@kms_psr@sprite_mmap_cpu:
- shard-iclb: FAIL [fdo#107383] / [fdo#110215] -> PASS
* igt@kms_setmode@basic:
- shard-apl: FAIL [fdo#99912] -> PASS
#### Warnings ####
* igt@i915_pm_rpm@dpms-non-lpsp:
- shard-skl: INCOMPLETE [fdo#107807] -> SKIP [fdo#109271]
[fdo#102887]: https://bugs.freedesktop.org/show_bug.cgi?id=102887
[fdo#103060]: https://bugs.freedesktop.org/show_bug.cgi?id=103060
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#104097]: https://bugs.freedesktop.org/show_bug.cgi?id=104097
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105363]: https://bugs.freedesktop.org/show_bug.cgi?id=105363
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#107383]: https://bugs.freedesktop.org/show_bug.cgi?id=107383
[fdo#107589]: https://bugs.freedesktop.org/show_bug.cgi?id=107589
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108040]: https://bugs.freedesktop.org/show_bug.cgi?id=108040
[fdo#108134]: https://bugs.freedesktop.org/show_bug.cgi?id=108134
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108954]: https://bugs.freedesktop.org/show_bug.cgi?id=108954
[fdo#109247]: https://bugs.freedesktop.org/show_bug.cgi?id=109247
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109277]: https://bugs.freedesktop.org/show_bug.cgi?id=109277
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109290]: https://bugs.freedesktop.org/show_bug.cgi?id=109290
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110215]: https://bugs.freedesktop.org/show_bug.cgi?id=110215
[fdo#110321]: https://bugs.freedesktop.org/show_bug.cgi?id=110321
[fdo#110336]: https://bugs.freedesktop.org/show_bug.cgi?id=110336
[fdo#110376]: https://bugs.freedesktop.org/show_bug.cgi?id=110376
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5934 -> Patchwork_12802
CI_DRM_5934: cc5334c0e706ec423c5f1a139cf3da7bd3287db6 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4946: 56bdc68638cec64c6b02cd6b220b52b76059b51a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12802: 3095d2548755ef26f4a6c695d268060e25a49644 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12802/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 15+ messages in thread