* [PATCH 01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
@ 2019-04-19 17:13 ` Chris Wilson
2019-04-23 16:49 ` Ville Syrjälä
2019-04-19 17:13 ` [PATCH 02/10] drm/i915: Lift acquiring the vlv punit magic to a common sb-get Chris Wilson
` (12 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:13 UTC (permalink / raw)
To: intel-gfx
While we talk to the punit over its sideband, we need to prevent the cpu
from sleeping in order to prevent a potential machine hang.
Note that by itself, it appears that pm_qos_update_request (via
intel_idle) doesn't provide a sufficient barrier to ensure that all core
are indeed awake (out of Cstate) and that the package is awake. To do so,
we need to supplement the pm_qos with a manual ping on_each_cpu.
v2: Restrict the heavy-weight wakeup to just the ISOF_PORT_PUNIT, there
is insufficient evidence to implicate a wider problem atm. Similarly,
restrict the w/a to Valleyview, as Cherryview doesn't have an angry cadre
of users.
The working theory, courtesy of Ville and Hans, is the issue lies within
the power delivery and so is likely to be unit and board specific and
occurs when both the unit/fw require extra power at the same time as the
cpu package is changing its own power state.
References: https://bugzilla.kernel.org/show_bug.cgi?id=109051
References: https://bugs.freedesktop.org/show_bug.cgi?id=102657
References: https://bugzilla.kernel.org/show_bug.cgi?id=195255
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Hans de Goede <hdegoede@redhat.com>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
---
drivers/gpu/drm/i915/i915_drv.c | 6 +
drivers/gpu/drm/i915/i915_drv.h | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 203 +++++++++++++++++---------
3 files changed, 139 insertions(+), 71 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
index 5e2ae2300454..9e657a0410c2 100644
--- a/drivers/gpu/drm/i915/i915_drv.c
+++ b/drivers/gpu/drm/i915/i915_drv.c
@@ -884,6 +884,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
mutex_init(&dev_priv->backlight_lock);
mutex_init(&dev_priv->sb_lock);
+ pm_qos_add_request(&dev_priv->sb_qos,
+ PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
+
mutex_init(&dev_priv->av_mutex);
mutex_init(&dev_priv->wm.wm_mutex);
mutex_init(&dev_priv->pps_mutex);
@@ -943,6 +946,9 @@ static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
i915_gem_cleanup_early(dev_priv);
i915_workqueues_cleanup(dev_priv);
i915_engines_cleanup(dev_priv);
+
+ pm_qos_remove_request(&dev_priv->sb_qos);
+ mutex_destroy(&dev_priv->sb_lock);
}
/**
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 71612e7fc8bc..afb979ff416f 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -1561,6 +1561,7 @@ struct drm_i915_private {
/* Sideband mailbox protection */
struct mutex sb_lock;
+ struct pm_qos_request sb_qos;
/** Cached value of IMR to avoid reads in updating the bitfield */
union {
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 57de41b1f989..fc8913461622 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -22,6 +22,8 @@
*
*/
+#include <asm/iosf_mbi.h>
+
#include "i915_drv.h"
#include "intel_drv.h"
@@ -39,19 +41,50 @@
/* Private register write, double-word addressing, non-posted */
#define SB_CRWRDA_NP 0x07
-static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
- u32 port, u32 opcode, u32 addr, u32 *val)
+static void ping(void *info)
{
- u32 cmd, be = 0xf, bar = 0;
- bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
+}
- cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
- (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
- (bar << IOSF_BAR_SHIFT);
+static void __vlv_punit_get(struct drm_i915_private *i915)
+{
+ iosf_mbi_punit_acquire();
- WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
+ /*
+ * Prevent the cpu from sleeping while we use this sideband, otherwise
+ * the punit may cause a machine hang. The issue appears to be isolated
+ * with changing the power state of the CPU package while changing
+ * the power state via the punit, and we have only observed it
+ * reliably on 4-core Baytail systems suggesting the issue is in the
+ * power delivery mechanism and likely to be be board/function
+ * specific. Hence we presume the workaround needs only be applied
+ * to the Valleyview P-unit and not all sideband communications.
+ */
+ if (IS_VALLEYVIEW(i915)) {
+ pm_qos_update_request(&i915->sb_qos, 0);
+ on_each_cpu(ping, NULL, 1);
+ }
+}
- if (intel_wait_for_register(&dev_priv->uncore,
+static void __vlv_punit_put(struct drm_i915_private *i915)
+{
+ if (IS_VALLEYVIEW(i915))
+ pm_qos_update_request(&i915->sb_qos, PM_QOS_DEFAULT_VALUE);
+
+ iosf_mbi_punit_release();
+}
+
+static int vlv_sideband_rw(struct drm_i915_private *i915,
+ u32 devfn, u32 port, u32 opcode,
+ u32 addr, u32 *val)
+{
+ struct intel_uncore *uncore = &i915->uncore;
+ const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
+ int err;
+
+ lockdep_assert_held(&i915->sb_lock);
+
+ /* Flush the previous comms, just in case it failed last time. */
+ if (intel_wait_for_register(uncore,
VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
5)) {
DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
@@ -59,131 +92,156 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
return -EAGAIN;
}
- I915_WRITE(VLV_IOSF_ADDR, addr);
- I915_WRITE(VLV_IOSF_DATA, is_read ? 0 : *val);
- I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
-
- if (intel_wait_for_register(&dev_priv->uncore,
- VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
- 5)) {
+ preempt_disable();
+
+ intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr);
+ intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
+ intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ,
+ (devfn << IOSF_DEVFN_SHIFT) |
+ (opcode << IOSF_OPCODE_SHIFT) |
+ (port << IOSF_PORT_SHIFT) |
+ (0xf << IOSF_BYTE_ENABLES_SHIFT) |
+ (0 << IOSF_BAR_SHIFT) |
+ IOSF_SB_BUSY);
+
+ if (__intel_wait_for_register_fw(uncore,
+ VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
+ 10000, 0, NULL) == 0) {
+ if (is_read)
+ *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
+ err = 0;
+ } else {
DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
is_read ? "read" : "write");
- return -ETIMEDOUT;
+ err = -ETIMEDOUT;
}
- if (is_read)
- *val = I915_READ(VLV_IOSF_DATA);
+ preempt_enable();
- return 0;
+ return err;
}
-u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
+u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
{
u32 val = 0;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
+ WARN_ON(!mutex_is_locked(&i915->pcu_lock));
+
+ mutex_lock(&i915->sb_lock);
+ __vlv_punit_get(i915);
- mutex_lock(&dev_priv->sb_lock);
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRRDDA_NP, addr, &val);
- mutex_unlock(&dev_priv->sb_lock);
+
+ __vlv_punit_put(i915);
+ mutex_unlock(&i915->sb_lock);
return val;
}
-int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
+int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
{
int err;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
+ WARN_ON(!mutex_is_locked(&i915->pcu_lock));
- mutex_lock(&dev_priv->sb_lock);
- err = vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
+ mutex_lock(&i915->sb_lock);
+ __vlv_punit_get(i915);
+
+ err = vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRWRDA_NP, addr, &val);
- mutex_unlock(&dev_priv->sb_lock);
+
+ __vlv_punit_put(i915);
+ mutex_unlock(&i915->sb_lock);
return err;
}
-u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
{
u32 val = 0;
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
SB_CRRDDA_NP, reg, &val);
return val;
}
-void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
{
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
SB_CRWRDA_NP, reg, &val);
}
-u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
+u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
{
u32 val = 0;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
+ WARN_ON(!mutex_is_locked(&i915->pcu_lock));
- mutex_lock(&dev_priv->sb_lock);
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
+ mutex_lock(&i915->sb_lock);
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
SB_CRRDDA_NP, addr, &val);
- mutex_unlock(&dev_priv->sb_lock);
+ mutex_unlock(&i915->sb_lock);
return val;
}
-u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
+u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
{
u32 val = 0;
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
+
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
SB_CRRDDA_NP, reg, &val);
+
return val;
}
-void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
+void vlv_iosf_sb_write(struct drm_i915_private *i915,
u8 port, u32 reg, u32 val)
{
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
SB_CRWRDA_NP, reg, &val);
}
-u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
{
u32 val = 0;
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
+
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
SB_CRRDDA_NP, reg, &val);
+
return val;
}
-void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
{
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
SB_CRWRDA_NP, reg, &val);
}
-u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
+u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
{
u32 val = 0;
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
+
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
SB_CRRDDA_NP, reg, &val);
+
return val;
}
-void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
+void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
{
- vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
+ vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
SB_CRWRDA_NP, reg, &val);
}
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
+u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
{
+ int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
u32 val = 0;
- vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
- SB_MRD_NP, reg, &val);
+ vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
/*
* FIXME: There might be some registers where all 1's is a valid value,
@@ -195,10 +253,27 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
return val;
}
-void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
+void vlv_dpio_write(struct drm_i915_private *i915,
+ enum pipe pipe, int reg, u32 val)
+{
+ int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
+
+ vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
+}
+
+u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
{
- vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
- SB_MWR_NP, reg, &val);
+ u32 val = 0;
+
+ vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
+ reg, &val);
+ return val;
+}
+
+void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
+{
+ vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
+ reg, &val);
}
/* SBI access */
@@ -279,17 +354,3 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
return;
}
}
-
-u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
-{
- u32 val = 0;
- vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
- reg, &val);
- return val;
-}
-
-void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
-{
- vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
- reg, &val);
-}
--
2.20.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
2019-04-19 17:13 ` [PATCH 01/10] drm/i915: Disable preemption and sleeping while using the punit sideband Chris Wilson
@ 2019-04-23 16:49 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2019-04-23 16:49 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Apr 19, 2019 at 06:13:53PM +0100, Chris Wilson wrote:
> While we talk to the punit over its sideband, we need to prevent the cpu
> from sleeping in order to prevent a potential machine hang.
>
> Note that by itself, it appears that pm_qos_update_request (via
> intel_idle) doesn't provide a sufficient barrier to ensure that all core
> are indeed awake (out of Cstate) and that the package is awake. To do so,
> we need to supplement the pm_qos with a manual ping on_each_cpu.
>
> v2: Restrict the heavy-weight wakeup to just the ISOF_PORT_PUNIT, there
> is insufficient evidence to implicate a wider problem atm. Similarly,
> restrict the w/a to Valleyview, as Cherryview doesn't have an angry cadre
> of users.
>
> The working theory, courtesy of Ville and Hans, is the issue lies within
> the power delivery and so is likely to be unit and board specific and
> occurs when both the unit/fw require extra power at the same time as the
> cpu package is changing its own power state.
>
> References: https://bugzilla.kernel.org/show_bug.cgi?id=109051
> References: https://bugs.freedesktop.org/show_bug.cgi?id=102657
> References: https://bugzilla.kernel.org/show_bug.cgi?id=195255
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Hans de Goede <hdegoede@redhat.com>
> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/i915_drv.c | 6 +
> drivers/gpu/drm/i915/i915_drv.h | 1 +
> drivers/gpu/drm/i915/intel_sideband.c | 203 +++++++++++++++++---------
> 3 files changed, 139 insertions(+), 71 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.c b/drivers/gpu/drm/i915/i915_drv.c
> index 5e2ae2300454..9e657a0410c2 100644
> --- a/drivers/gpu/drm/i915/i915_drv.c
> +++ b/drivers/gpu/drm/i915/i915_drv.c
> @@ -884,6 +884,9 @@ static int i915_driver_init_early(struct drm_i915_private *dev_priv)
> mutex_init(&dev_priv->backlight_lock);
>
> mutex_init(&dev_priv->sb_lock);
> + pm_qos_add_request(&dev_priv->sb_qos,
> + PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
> +
> mutex_init(&dev_priv->av_mutex);
> mutex_init(&dev_priv->wm.wm_mutex);
> mutex_init(&dev_priv->pps_mutex);
> @@ -943,6 +946,9 @@ static void i915_driver_cleanup_early(struct drm_i915_private *dev_priv)
> i915_gem_cleanup_early(dev_priv);
> i915_workqueues_cleanup(dev_priv);
> i915_engines_cleanup(dev_priv);
> +
> + pm_qos_remove_request(&dev_priv->sb_qos);
> + mutex_destroy(&dev_priv->sb_lock);
> }
>
> /**
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 71612e7fc8bc..afb979ff416f 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -1561,6 +1561,7 @@ struct drm_i915_private {
>
> /* Sideband mailbox protection */
> struct mutex sb_lock;
> + struct pm_qos_request sb_qos;
Should we call it punit_qos maybe?
I'm a bit sad to all the complexity for this, but no one has come up
with a way to really fix it so I guess we just have to swallow this.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> /** Cached value of IMR to avoid reads in updating the bitfield */
> union {
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 57de41b1f989..fc8913461622 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -22,6 +22,8 @@
> *
> */
>
> +#include <asm/iosf_mbi.h>
> +
> #include "i915_drv.h"
> #include "intel_drv.h"
>
> @@ -39,19 +41,50 @@
> /* Private register write, double-word addressing, non-posted */
> #define SB_CRWRDA_NP 0x07
>
> -static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
> - u32 port, u32 opcode, u32 addr, u32 *val)
> +static void ping(void *info)
> {
> - u32 cmd, be = 0xf, bar = 0;
> - bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
> +}
>
> - cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
> - (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
> - (bar << IOSF_BAR_SHIFT);
> +static void __vlv_punit_get(struct drm_i915_private *i915)
> +{
> + iosf_mbi_punit_acquire();
>
> - WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
> + /*
> + * Prevent the cpu from sleeping while we use this sideband, otherwise
> + * the punit may cause a machine hang. The issue appears to be isolated
> + * with changing the power state of the CPU package while changing
> + * the power state via the punit, and we have only observed it
> + * reliably on 4-core Baytail systems suggesting the issue is in the
> + * power delivery mechanism and likely to be be board/function
> + * specific. Hence we presume the workaround needs only be applied
> + * to the Valleyview P-unit and not all sideband communications.
> + */
> + if (IS_VALLEYVIEW(i915)) {
> + pm_qos_update_request(&i915->sb_qos, 0);
> + on_each_cpu(ping, NULL, 1);
> + }
> +}
>
> - if (intel_wait_for_register(&dev_priv->uncore,
> +static void __vlv_punit_put(struct drm_i915_private *i915)
> +{
> + if (IS_VALLEYVIEW(i915))
> + pm_qos_update_request(&i915->sb_qos, PM_QOS_DEFAULT_VALUE);
> +
> + iosf_mbi_punit_release();
> +}
> +
> +static int vlv_sideband_rw(struct drm_i915_private *i915,
> + u32 devfn, u32 port, u32 opcode,
> + u32 addr, u32 *val)
> +{
> + struct intel_uncore *uncore = &i915->uncore;
> + const bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
> + int err;
> +
> + lockdep_assert_held(&i915->sb_lock);
> +
> + /* Flush the previous comms, just in case it failed last time. */
> + if (intel_wait_for_register(uncore,
> VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
> 5)) {
> DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
> @@ -59,131 +92,156 @@ static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
> return -EAGAIN;
> }
>
> - I915_WRITE(VLV_IOSF_ADDR, addr);
> - I915_WRITE(VLV_IOSF_DATA, is_read ? 0 : *val);
> - I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
> -
> - if (intel_wait_for_register(&dev_priv->uncore,
> - VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
> - 5)) {
> + preempt_disable();
> +
> + intel_uncore_write_fw(uncore, VLV_IOSF_ADDR, addr);
> + intel_uncore_write_fw(uncore, VLV_IOSF_DATA, is_read ? 0 : *val);
> + intel_uncore_write_fw(uncore, VLV_IOSF_DOORBELL_REQ,
> + (devfn << IOSF_DEVFN_SHIFT) |
> + (opcode << IOSF_OPCODE_SHIFT) |
> + (port << IOSF_PORT_SHIFT) |
> + (0xf << IOSF_BYTE_ENABLES_SHIFT) |
> + (0 << IOSF_BAR_SHIFT) |
> + IOSF_SB_BUSY);
> +
> + if (__intel_wait_for_register_fw(uncore,
> + VLV_IOSF_DOORBELL_REQ, IOSF_SB_BUSY, 0,
> + 10000, 0, NULL) == 0) {
> + if (is_read)
> + *val = intel_uncore_read_fw(uncore, VLV_IOSF_DATA);
> + err = 0;
> + } else {
> DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
> is_read ? "read" : "write");
> - return -ETIMEDOUT;
> + err = -ETIMEDOUT;
> }
>
> - if (is_read)
> - *val = I915_READ(VLV_IOSF_DATA);
> + preempt_enable();
>
> - return 0;
> + return err;
> }
>
> -u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr)
> +u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
> {
> u32 val = 0;
>
> - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
> + WARN_ON(!mutex_is_locked(&i915->pcu_lock));
> +
> + mutex_lock(&i915->sb_lock);
> + __vlv_punit_get(i915);
>
> - mutex_lock(&dev_priv->sb_lock);
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> SB_CRRDDA_NP, addr, &val);
> - mutex_unlock(&dev_priv->sb_lock);
> +
> + __vlv_punit_put(i915);
> + mutex_unlock(&i915->sb_lock);
>
> return val;
> }
>
> -int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val)
> +int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
> {
> int err;
>
> - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
> + WARN_ON(!mutex_is_locked(&i915->pcu_lock));
>
> - mutex_lock(&dev_priv->sb_lock);
> - err = vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> + mutex_lock(&i915->sb_lock);
> + __vlv_punit_get(i915);
> +
> + err = vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> SB_CRWRDA_NP, addr, &val);
> - mutex_unlock(&dev_priv->sb_lock);
> +
> + __vlv_punit_put(i915);
> + mutex_unlock(&i915->sb_lock);
>
> return err;
> }
>
> -u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
> +u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
> {
> u32 val = 0;
>
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
> SB_CRRDDA_NP, reg, &val);
>
> return val;
> }
>
> -void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_BUNIT,
> SB_CRWRDA_NP, reg, &val);
> }
>
> -u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
> +u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
> {
> u32 val = 0;
>
> - WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
> + WARN_ON(!mutex_is_locked(&i915->pcu_lock));
>
> - mutex_lock(&dev_priv->sb_lock);
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_NC,
> + mutex_lock(&i915->sb_lock);
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
> SB_CRRDDA_NP, addr, &val);
> - mutex_unlock(&dev_priv->sb_lock);
> + mutex_unlock(&i915->sb_lock);
>
> return val;
> }
>
> -u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg)
> +u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg)
> {
> u32 val = 0;
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
> +
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
> SB_CRRDDA_NP, reg, &val);
> +
> return val;
> }
>
> -void vlv_iosf_sb_write(struct drm_i915_private *dev_priv,
> +void vlv_iosf_sb_write(struct drm_i915_private *i915,
> u8 port, u32 reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), port,
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), port,
> SB_CRWRDA_NP, reg, &val);
> }
>
> -u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
> +u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg)
> {
> u32 val = 0;
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
> +
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
> SB_CRRDDA_NP, reg, &val);
> +
> return val;
> }
>
> -void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCK,
> SB_CRWRDA_NP, reg, &val);
> }
>
> -u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
> +u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg)
> {
> u32 val = 0;
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
> +
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
> SB_CRRDDA_NP, reg, &val);
> +
> return val;
> }
>
> -void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> +void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val)
> {
> - vlv_sideband_rw(dev_priv, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
> + vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_CCU,
> SB_CRWRDA_NP, reg, &val);
> }
>
> -u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
> +u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg)
> {
> + int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
> u32 val = 0;
>
> - vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
> - SB_MRD_NP, reg, &val);
> + vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MRD_NP, reg, &val);
>
> /*
> * FIXME: There might be some registers where all 1's is a valid value,
> @@ -195,10 +253,27 @@ u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
> return val;
> }
>
> -void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
> +void vlv_dpio_write(struct drm_i915_private *i915,
> + enum pipe pipe, int reg, u32 val)
> +{
> + int port = i915->dpio_phy_iosf_port[DPIO_PHY(pipe)];
> +
> + vlv_sideband_rw(i915, DPIO_DEVFN, port, SB_MWR_NP, reg, &val);
> +}
> +
> +u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg)
> {
> - vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
> - SB_MWR_NP, reg, &val);
> + u32 val = 0;
> +
> + vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
> + reg, &val);
> + return val;
> +}
> +
> +void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
> +{
> + vlv_sideband_rw(i915, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
> + reg, &val);
> }
>
> /* SBI access */
> @@ -279,17 +354,3 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> return;
> }
> }
> -
> -u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
> -{
> - u32 val = 0;
> - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
> - reg, &val);
> - return val;
> -}
> -
> -void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
> -{
> - vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
> - reg, &val);
> -}
> --
> 2.20.1
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 02/10] drm/i915: Lift acquiring the vlv punit magic to a common sb-get
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
2019-04-19 17:13 ` [PATCH 01/10] drm/i915: Disable preemption and sleeping while using the punit sideband Chris Wilson
@ 2019-04-19 17:13 ` Chris Wilson
2019-04-23 16:55 ` Ville Syrjälä
2019-04-19 17:13 ` [PATCH 03/10] drm/i915: Lift sideband locking for vlv_punit_(read|write) Chris Wilson
` (11 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:13 UTC (permalink / raw)
To: intel-gfx
As we now employ a very heavy pm_qos around the punit access, we want to
minimise the number of synchronous requests by performing one for the
whole punit sequence rather than around individual accesses. The
sideband lock is used for this, so push the pm_qos into the sideband
lock acquisition and release, moving it from the lowlevel punit rw
routine to the callers. In the first step, we move the punit magic into
the common sideband lock so that we can acquire a bunch of ports
simultaneously, and if need be extend the workaround protection later.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 124 +++++++++++++++++++++---
drivers/gpu/drm/i915/intel_cdclk.c | 6 +-
drivers/gpu/drm/i915/intel_display.c | 37 +++----
drivers/gpu/drm/i915/intel_dp.c | 4 +-
drivers/gpu/drm/i915/intel_dpio_phy.c | 37 +++----
drivers/gpu/drm/i915/intel_dsi_vbt.c | 8 +-
drivers/gpu/drm/i915/intel_hdmi.c | 4 +-
drivers/gpu/drm/i915/intel_pm.c | 4 +-
drivers/gpu/drm/i915/intel_runtime_pm.c | 8 +-
drivers/gpu/drm/i915/intel_sideband.c | 45 ++++++---
drivers/gpu/drm/i915/vlv_dsi.c | 8 +-
drivers/gpu/drm/i915/vlv_dsi_pll.c | 14 +--
12 files changed, 206 insertions(+), 93 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index afb979ff416f..162d988dbceb 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3449,25 +3449,119 @@ int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
/* intel_sideband.c */
-u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
-int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
-u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
-u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
-void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
-u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
-u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
-void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
+
+enum {
+ VLV_IOSF_SB_BUNIT,
+ VLV_IOSF_SB_CCK,
+ VLV_IOSF_SB_CCU,
+ VLV_IOSF_SB_DPIO,
+ VLV_IOSF_SB_FLISDSI,
+ VLV_IOSF_SB_GPIO,
+ VLV_IOSF_SB_NC,
+ VLV_IOSF_SB_PUNIT,
+};
+
+void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
+u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
+void vlv_iosf_sb_write(struct drm_i915_private *i915,
+ u8 port, u32 reg, u32 val);
+void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
+
+static inline void vlv_bunit_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
+}
+
+u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
+void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_bunit_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
+}
+
+static inline void vlv_cck_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
+}
+
+u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
+void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_cck_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
+}
+
+static inline void vlv_ccu_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
+}
+
+u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
+void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_ccu_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
+}
+
+static inline void vlv_dpio_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
+}
+
+u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
+void vlv_dpio_write(struct drm_i915_private *i915,
+ enum pipe pipe, int reg, u32 val);
+
+static inline void vlv_dpio_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
+}
+
+static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
+}
+
+u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
+void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
+}
+
+static inline void vlv_nc_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
+}
+
+u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
+
+static inline void vlv_nc_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
+}
+
+static inline void vlv_punit_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
+}
+
+u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
+int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
+
+static inline void vlv_punit_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
+}
+
u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
enum intel_sbi_destination destination);
void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
enum intel_sbi_destination destination);
-u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
-void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
/* intel_dpio_phy.c */
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index ae40a8679314..5845d0a37599 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -557,7 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
}
mutex_unlock(&dev_priv->pcu_lock);
- mutex_lock(&dev_priv->sb_lock);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));
if (cdclk == 400000) {
u32 divider;
@@ -591,7 +592,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
val |= 3000 / 250; /* 3.0 usec */
vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_iosf_sb_put(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));
intel_update_cdclk(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 3bd40a4a6739..11bb07650f87 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -153,10 +153,10 @@ int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
/* Obtain SKU information */
- mutex_lock(&dev_priv->sb_lock);
+ vlv_cck_get(dev_priv);
hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
CCK_FUSE_HPLL_FREQ_MASK;
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_cck_put(dev_priv);
return vco_freq[hpll_freq] * 1000;
}
@@ -167,9 +167,9 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
u32 val;
int divider;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_cck_get(dev_priv);
val = vlv_cck_read(dev_priv, reg);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_cck_put(dev_priv);
divider = val & CCK_FREQUENCY_VALUES;
@@ -1080,9 +1080,9 @@ void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
u32 val;
bool cur_state;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_cck_get(dev_priv);
val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_cck_put(dev_priv);
cur_state = val & DSI_PLL_VCO_EN;
I915_STATE_WARN(cur_state != state,
@@ -1392,14 +1392,14 @@ static void _chv_enable_pll(struct intel_crtc *crtc,
enum dpio_channel port = vlv_pipe_to_channel(pipe);
u32 tmp;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* Enable back the 10bit clock to display controller */
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
tmp |= DPIO_DCLKP_EN;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
/*
* Need to wait > 100ns between dclkp clock enable bit and PLL enable.
@@ -1556,14 +1556,14 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
I915_WRITE(DPLL(pipe), val);
POSTING_READ(DPLL(pipe));
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* Disable 10bit clock to display controller */
val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
val &= ~DPIO_DCLKP_EN;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
}
void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
@@ -7225,7 +7225,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
return;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
bestn = pipe_config->dpll.n;
bestm1 = pipe_config->dpll.m1;
@@ -7302,7 +7302,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
- mutex_unlock(&dev_priv->sb_lock);
+
+ vlv_dpio_put(dev_priv);
}
static void chv_prepare_pll(struct intel_crtc *crtc,
@@ -7335,7 +7336,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
dpio_val = 0;
loopfilter = 0;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* p1 and p2 divider */
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
@@ -7407,7 +7408,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
DPIO_AFC_RECAL);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
}
/**
@@ -8033,9 +8034,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
return;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
clock.m2 = mdiv & DPIO_M2DIV_MASK;
@@ -8144,13 +8145,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
return;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
clock.m2 = (pll_dw0 & 0xff) << 22;
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 560274d1c50b..4fc25dcc97d4 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -3148,12 +3148,12 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
intel_dp_link_down(encoder, old_crtc_state);
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* Assert data lane reset */
chv_data_lane_soft_reset(encoder, old_crtc_state, true);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
}
static void
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index ab4ac7158b79..c784f3daaf51 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -648,7 +648,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
u32 val;
int i;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* Clear calc init */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
@@ -729,8 +729,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
}
- mutex_unlock(&dev_priv->sb_lock);
-
+ vlv_dpio_put(dev_priv);
}
void chv_data_lane_soft_reset(struct intel_encoder *encoder,
@@ -800,7 +799,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
chv_phy_powergate_lanes(encoder, true, lane_mask);
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* Assert data lane reset */
chv_data_lane_soft_reset(encoder, crtc_state, true);
@@ -855,7 +854,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
val |= CHV_CMN_USEDCLKCHANNEL;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
}
void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
@@ -870,7 +869,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
int data, i, stagger;
u32 val;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* allow hardware to manage TX FIFO reset source */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
@@ -935,7 +934,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
/* Deassert data lane reset */
chv_data_lane_soft_reset(encoder, crtc_state, false);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
}
void chv_phy_release_cl2_override(struct intel_encoder *encoder)
@@ -956,7 +955,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
u32 val;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* disable left/right clock distribution */
if (pipe != PIPE_B) {
@@ -969,7 +968,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
}
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
/*
* Leave the power down bit cleared for at least one
@@ -993,7 +992,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
enum dpio_channel port = vlv_dport_to_channel(dport);
enum pipe pipe = intel_crtc->pipe;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
+
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
@@ -1006,7 +1006,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
- mutex_unlock(&dev_priv->sb_lock);
+
+ vlv_dpio_put(dev_priv);
}
void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
@@ -1019,7 +1020,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
enum pipe pipe = crtc->pipe;
/* Program Tx lane resets to default */
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
+
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
DPIO_PCS_TX_LANE2_RESET |
DPIO_PCS_TX_LANE1_RESET);
@@ -1033,7 +1035,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
- mutex_unlock(&dev_priv->sb_lock);
+
+ vlv_dpio_put(dev_priv);
}
void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
@@ -1047,7 +1050,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
enum pipe pipe = crtc->pipe;
u32 val;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* Enable clock channels for this port */
val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
@@ -1063,7 +1066,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
}
void vlv_phy_reset_lanes(struct intel_encoder *encoder,
@@ -1075,8 +1078,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
enum dpio_channel port = vlv_dport_to_channel(dport);
enum pipe pipe = crtc->pipe;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
}
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 3074448446bc..2304488f2d35 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -248,7 +248,7 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
pconf0 = VLV_GPIO_PCONF0(map->base_offset);
padval = VLV_GPIO_PAD_VAL(map->base_offset);
- mutex_lock(&dev_priv->sb_lock);
+ vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
if (!map->init) {
/* FIXME: remove constant below */
vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
@@ -257,7 +257,7 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
tmp = 0x4 | value;
vlv_iosf_sb_write(dev_priv, port, padval, tmp);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
}
static void chv_exec_gpio(struct drm_i915_private *dev_priv,
@@ -303,12 +303,12 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv,
cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
- mutex_lock(&dev_priv->sb_lock);
+ vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
vlv_iosf_sb_write(dev_priv, port, cfg0,
CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
CHV_GPIO_GPIOTXSTATE(value));
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
}
static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index e1005d7b75fd..8b72365f9309 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -2630,12 +2630,12 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder,
struct drm_device *dev = encoder->base.dev;
struct drm_i915_private *dev_priv = to_i915(dev);
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* Assert data lane reset */
chv_data_lane_soft_reset(encoder, old_crtc_state, true);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
}
static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 7aa9a8c12b54..6c2f416b95a6 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -7803,9 +7803,9 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
vlv_init_gpll_ref_freq(dev_priv);
- mutex_lock(&dev_priv->sb_lock);
+ vlv_cck_get(dev_priv);
val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_cck_put(dev_priv);
switch ((val >> 2) & 0x7) {
case 3:
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index d4f4262d0fee..9c1294c29566 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1569,7 +1569,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
1))
DRM_ERROR("Display PHY %d is not power up\n", phy);
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
/* Enable dynamic power down */
tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
@@ -1592,7 +1592,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
}
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
@@ -1655,9 +1655,9 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
else
reg = _CHV_CMN_DW6_CH1;
- mutex_lock(&dev_priv->sb_lock);
+ vlv_dpio_get(dev_priv);
val = vlv_dpio_read(dev_priv, pipe, reg);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_dpio_put(dev_priv);
/*
* This assumes !override is only used when the port is disabled.
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index fc8913461622..b2fc605e2e29 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -73,6 +73,22 @@ static void __vlv_punit_put(struct drm_i915_private *i915)
iosf_mbi_punit_release();
}
+void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
+{
+ if (ports & BIT(VLV_IOSF_SB_PUNIT))
+ __vlv_punit_get(i915);
+
+ mutex_lock(&i915->sb_lock);
+}
+
+void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
+{
+ mutex_unlock(&i915->sb_lock);
+
+ if (ports & BIT(VLV_IOSF_SB_PUNIT))
+ __vlv_punit_put(i915);
+}
+
static int vlv_sideband_rw(struct drm_i915_private *i915,
u32 devfn, u32 port, u32 opcode,
u32 addr, u32 *val)
@@ -82,6 +98,8 @@ static int vlv_sideband_rw(struct drm_i915_private *i915,
int err;
lockdep_assert_held(&i915->sb_lock);
+ if (port == IOSF_PORT_PUNIT)
+ iosf_mbi_assert_punit_acquired();
/* Flush the previous comms, just in case it failed last time. */
if (intel_wait_for_register(uncore,
@@ -125,16 +143,14 @@ u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
{
u32 val = 0;
- WARN_ON(!mutex_is_locked(&i915->pcu_lock));
+ lockdep_assert_held(&i915->pcu_lock);
- mutex_lock(&i915->sb_lock);
- __vlv_punit_get(i915);
+ vlv_punit_get(i915);
vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRRDDA_NP, addr, &val);
- __vlv_punit_put(i915);
- mutex_unlock(&i915->sb_lock);
+ vlv_punit_put(i915);
return val;
}
@@ -143,16 +159,14 @@ int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
{
int err;
- WARN_ON(!mutex_is_locked(&i915->pcu_lock));
+ lockdep_assert_held(&i915->pcu_lock);
- mutex_lock(&i915->sb_lock);
- __vlv_punit_get(i915);
+ vlv_punit_get(i915);
err = vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRWRDA_NP, addr, &val);
- __vlv_punit_put(i915);
- mutex_unlock(&i915->sb_lock);
+ vlv_punit_put(i915);
return err;
}
@@ -177,12 +191,10 @@ u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
{
u32 val = 0;
- WARN_ON(!mutex_is_locked(&i915->pcu_lock));
-
- mutex_lock(&i915->sb_lock);
+ vlv_nc_get(i915);
vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
SB_CRRDDA_NP, addr, &val);
- mutex_unlock(&i915->sb_lock);
+ vlv_nc_put(i915);
return val;
}
@@ -281,7 +293,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
enum intel_sbi_destination destination)
{
u32 value = 0;
- WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
+
+ lockdep_assert_held(&dev_priv->sb_lock);
if (intel_wait_for_register(&dev_priv->uncore,
SBI_CTL_STAT, SBI_BUSY, 0,
@@ -321,7 +334,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
{
u32 tmp;
- WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
+ lockdep_assert_held(&dev_priv->sb_lock);
if (intel_wait_for_register(&dev_priv->uncore,
SBI_CTL_STAT, SBI_BUSY, 0,
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index e0b1ec821960..dc1839bfde3e 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -248,7 +248,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
static void band_gap_reset(struct drm_i915_private *dev_priv)
{
- mutex_lock(&dev_priv->sb_lock);
+ vlv_flisdsi_get(dev_priv);
vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
@@ -257,7 +257,7 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_flisdsi_put(dev_priv);
}
static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
@@ -515,11 +515,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
- mutex_lock(&dev_priv->sb_lock);
+ vlv_flisdsi_get(dev_priv);
/* program rcomp for compliance, reduce from 50 ohms to 45 ohms
* needed everytime after power gate */
vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_flisdsi_put(dev_priv);
/* bandgap reset is needed after everytime we do power gate */
band_gap_reset(dev_priv);
diff --git a/drivers/gpu/drm/i915/vlv_dsi_pll.c b/drivers/gpu/drm/i915/vlv_dsi_pll.c
index 5e7b1fb2db5d..25b811174f5c 100644
--- a/drivers/gpu/drm/i915/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/vlv_dsi_pll.c
@@ -149,7 +149,7 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder,
DRM_DEBUG_KMS("\n");
- mutex_lock(&dev_priv->sb_lock);
+ vlv_cck_get(dev_priv);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
@@ -166,11 +166,11 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder,
if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
DSI_PLL_LOCK, 20)) {
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_cck_put(dev_priv);
DRM_ERROR("DSI PLL lock failed\n");
return;
}
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_cck_put(dev_priv);
DRM_DEBUG_KMS("DSI PLL locked\n");
}
@@ -182,14 +182,14 @@ void vlv_dsi_pll_disable(struct intel_encoder *encoder)
DRM_DEBUG_KMS("\n");
- mutex_lock(&dev_priv->sb_lock);
+ vlv_cck_get(dev_priv);
tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
tmp &= ~DSI_PLL_VCO_EN;
tmp |= DSI_PLL_LDO_GATE;
vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_cck_put(dev_priv);
}
bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
@@ -266,10 +266,10 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
DRM_DEBUG_KMS("\n");
- mutex_lock(&dev_priv->sb_lock);
+ vlv_cck_get(dev_priv);
pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
- mutex_unlock(&dev_priv->sb_lock);
+ vlv_cck_put(dev_priv);
config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
config->dsi_pll.div = pll_div;
--
2.20.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 02/10] drm/i915: Lift acquiring the vlv punit magic to a common sb-get
2019-04-19 17:13 ` [PATCH 02/10] drm/i915: Lift acquiring the vlv punit magic to a common sb-get Chris Wilson
@ 2019-04-23 16:55 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2019-04-23 16:55 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Apr 19, 2019 at 06:13:54PM +0100, Chris Wilson wrote:
> As we now employ a very heavy pm_qos around the punit access, we want to
> minimise the number of synchronous requests by performing one for the
> whole punit sequence rather than around individual accesses. The
> sideband lock is used for this, so push the pm_qos into the sideband
> lock acquisition and release, moving it from the lowlevel punit rw
> routine to the callers. In the first step, we move the punit magic into
> the common sideband lock so that we can acquire a bunch of ports
> simultaneously, and if need be extend the workaround protection later.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 124 +++++++++++++++++++++---
> drivers/gpu/drm/i915/intel_cdclk.c | 6 +-
> drivers/gpu/drm/i915/intel_display.c | 37 +++----
> drivers/gpu/drm/i915/intel_dp.c | 4 +-
> drivers/gpu/drm/i915/intel_dpio_phy.c | 37 +++----
> drivers/gpu/drm/i915/intel_dsi_vbt.c | 8 +-
> drivers/gpu/drm/i915/intel_hdmi.c | 4 +-
> drivers/gpu/drm/i915/intel_pm.c | 4 +-
> drivers/gpu/drm/i915/intel_runtime_pm.c | 8 +-
> drivers/gpu/drm/i915/intel_sideband.c | 45 ++++++---
> drivers/gpu/drm/i915/vlv_dsi.c | 8 +-
> drivers/gpu/drm/i915/vlv_dsi_pll.c | 14 +--
> 12 files changed, 206 insertions(+), 93 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index afb979ff416f..162d988dbceb 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3449,25 +3449,119 @@ int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
> u32 reply_mask, u32 reply, int timeout_base_ms);
>
> /* intel_sideband.c */
Introduce intel_sideband.h maybe?
> -u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
> -int vlv_punit_write(struct drm_i915_private *dev_priv, u32 addr, u32 val);
> -u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr);
> -u32 vlv_iosf_sb_read(struct drm_i915_private *dev_priv, u8 port, u32 reg);
> -void vlv_iosf_sb_write(struct drm_i915_private *dev_priv, u8 port, u32 reg, u32 val);
> -u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> -u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> -u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
> -u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg);
> -void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val);
> +
> +enum {
> + VLV_IOSF_SB_BUNIT,
> + VLV_IOSF_SB_CCK,
> + VLV_IOSF_SB_CCU,
> + VLV_IOSF_SB_DPIO,
> + VLV_IOSF_SB_FLISDSI,
> + VLV_IOSF_SB_GPIO,
> + VLV_IOSF_SB_NC,
> + VLV_IOSF_SB_PUNIT,
> +};
Hopefully no one will confuse these with the IOSF SB port numbers.
> +
> +void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
> +u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
> +void vlv_iosf_sb_write(struct drm_i915_private *i915,
> + u8 port, u32 reg, u32 val);
> +void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
> +
> +static inline void vlv_bunit_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
> +}
> +
> +u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
> +void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
> +
> +static inline void vlv_bunit_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
> +}
> +
> +static inline void vlv_cck_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
> +}
> +
> +u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
> +void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
> +
> +static inline void vlv_cck_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
> +}
> +
> +static inline void vlv_ccu_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
> +}
> +
> +u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
> +void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
> +
> +static inline void vlv_ccu_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
> +}
> +
> +static inline void vlv_dpio_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
> +}
> +
> +u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
> +void vlv_dpio_write(struct drm_i915_private *i915,
> + enum pipe pipe, int reg, u32 val);
> +
> +static inline void vlv_dpio_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
> +}
> +
> +static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
> +}
> +
> +u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
> +void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
> +
> +static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
> +}
> +
> +static inline void vlv_nc_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
> +}
> +
> +u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
> +
> +static inline void vlv_nc_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
> +}
> +
> +static inline void vlv_punit_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
> +}
> +
> +u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
> +int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
> +
> +static inline void vlv_punit_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
> +}
> +
> u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> enum intel_sbi_destination destination);
> void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> enum intel_sbi_destination destination);
> -u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg);
> -void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val);
>
> /* intel_dpio_phy.c */
> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index ae40a8679314..5845d0a37599 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -557,7 +557,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> }
> mutex_unlock(&dev_priv->pcu_lock);
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_iosf_sb_get(dev_priv,
> + BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));
>
> if (cdclk == 400000) {
> u32 divider;
> @@ -591,7 +592,8 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> val |= 3000 / 250; /* 3.0 usec */
> vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_iosf_sb_put(dev_priv,
> + BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));
>
> intel_update_cdclk(dev_priv);
>
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 3bd40a4a6739..11bb07650f87 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -153,10 +153,10 @@ int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
> int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
>
> /* Obtain SKU information */
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_cck_get(dev_priv);
> hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
> CCK_FUSE_HPLL_FREQ_MASK;
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_cck_put(dev_priv);
>
> return vco_freq[hpll_freq] * 1000;
> }
> @@ -167,9 +167,9 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
> u32 val;
> int divider;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_cck_get(dev_priv);
> val = vlv_cck_read(dev_priv, reg);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_cck_put(dev_priv);
>
> divider = val & CCK_FREQUENCY_VALUES;
>
> @@ -1080,9 +1080,9 @@ void assert_dsi_pll(struct drm_i915_private *dev_priv, bool state)
> u32 val;
> bool cur_state;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_cck_get(dev_priv);
> val = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_cck_put(dev_priv);
>
> cur_state = val & DSI_PLL_VCO_EN;
> I915_STATE_WARN(cur_state != state,
> @@ -1392,14 +1392,14 @@ static void _chv_enable_pll(struct intel_crtc *crtc,
> enum dpio_channel port = vlv_pipe_to_channel(pipe);
> u32 tmp;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* Enable back the 10bit clock to display controller */
> tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
> tmp |= DPIO_DCLKP_EN;
> vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
>
> /*
> * Need to wait > 100ns between dclkp clock enable bit and PLL enable.
> @@ -1556,14 +1556,14 @@ static void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
> I915_WRITE(DPLL(pipe), val);
> POSTING_READ(DPLL(pipe));
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* Disable 10bit clock to display controller */
> val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port));
> val &= ~DPIO_DCLKP_EN;
> vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
> }
>
> void vlv_wait_port_ready(struct drm_i915_private *dev_priv,
> @@ -7225,7 +7225,7 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> return;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> bestn = pipe_config->dpll.n;
> bestm1 = pipe_config->dpll.m1;
> @@ -7302,7 +7302,8 @@ static void vlv_prepare_pll(struct intel_crtc *crtc,
> vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk);
>
> vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000);
> - mutex_unlock(&dev_priv->sb_lock);
> +
> + vlv_dpio_put(dev_priv);
> }
>
> static void chv_prepare_pll(struct intel_crtc *crtc,
> @@ -7335,7 +7336,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> dpio_val = 0;
> loopfilter = 0;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* p1 and p2 divider */
> vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port),
> @@ -7407,7 +7408,7 @@ static void chv_prepare_pll(struct intel_crtc *crtc,
> vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) |
> DPIO_AFC_RECAL);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
> }
>
> /**
> @@ -8033,9 +8034,9 @@ static void vlv_crtc_clock_get(struct intel_crtc *crtc,
> if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> return;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
> mdiv = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW3(pipe));
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
>
> clock.m1 = (mdiv >> DPIO_M1DIV_SHIFT) & 7;
> clock.m2 = mdiv & DPIO_M2DIV_MASK;
> @@ -8144,13 +8145,13 @@ static void chv_crtc_clock_get(struct intel_crtc *crtc,
> if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0)
> return;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
> cmn_dw13 = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW13(port));
> pll_dw0 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW0(port));
> pll_dw1 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW1(port));
> pll_dw2 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW2(port));
> pll_dw3 = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port));
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
>
> clock.m1 = (pll_dw1 & 0x7) == DPIO_CHV_M1_DIV_BY_2 ? 2 : 0;
> clock.m2 = (pll_dw0 & 0xff) << 22;
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 560274d1c50b..4fc25dcc97d4 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -3148,12 +3148,12 @@ static void chv_post_disable_dp(struct intel_encoder *encoder,
>
> intel_dp_link_down(encoder, old_crtc_state);
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* Assert data lane reset */
> chv_data_lane_soft_reset(encoder, old_crtc_state, true);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
> }
>
> static void
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index ab4ac7158b79..c784f3daaf51 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -648,7 +648,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
> u32 val;
> int i;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* Clear calc init */
> val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
> @@ -729,8 +729,7 @@ void chv_set_phy_signal_level(struct intel_encoder *encoder,
> vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
> }
>
> - mutex_unlock(&dev_priv->sb_lock);
> -
> + vlv_dpio_put(dev_priv);
> }
>
> void chv_data_lane_soft_reset(struct intel_encoder *encoder,
> @@ -800,7 +799,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
>
> chv_phy_powergate_lanes(encoder, true, lane_mask);
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* Assert data lane reset */
> chv_data_lane_soft_reset(encoder, crtc_state, true);
> @@ -855,7 +854,7 @@ void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
> val |= CHV_CMN_USEDCLKCHANNEL;
> vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
> }
>
> void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> @@ -870,7 +869,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> int data, i, stagger;
> u32 val;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* allow hardware to manage TX FIFO reset source */
> val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
> @@ -935,7 +934,7 @@ void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> /* Deassert data lane reset */
> chv_data_lane_soft_reset(encoder, crtc_state, false);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
> }
>
> void chv_phy_release_cl2_override(struct intel_encoder *encoder)
> @@ -956,7 +955,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
> enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
> u32 val;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* disable left/right clock distribution */
> if (pipe != PIPE_B) {
> @@ -969,7 +968,7 @@ void chv_phy_post_pll_disable(struct intel_encoder *encoder,
> vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
> }
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
>
> /*
> * Leave the power down bit cleared for at least one
> @@ -993,7 +992,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> enum dpio_channel port = vlv_dport_to_channel(dport);
> enum pipe pipe = intel_crtc->pipe;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
> +
> vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
> vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
> vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
> @@ -1006,7 +1006,8 @@ void vlv_set_phy_signal_level(struct intel_encoder *encoder,
> vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
> vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
> vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
> - mutex_unlock(&dev_priv->sb_lock);
> +
> + vlv_dpio_put(dev_priv);
> }
>
> void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
> @@ -1019,7 +1020,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
> enum pipe pipe = crtc->pipe;
>
> /* Program Tx lane resets to default */
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
> +
> vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
> DPIO_PCS_TX_LANE2_RESET |
> DPIO_PCS_TX_LANE1_RESET);
> @@ -1033,7 +1035,8 @@ void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
> vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
> vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
> vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
> - mutex_unlock(&dev_priv->sb_lock);
> +
> + vlv_dpio_put(dev_priv);
> }
>
> void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> @@ -1047,7 +1050,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> enum pipe pipe = crtc->pipe;
> u32 val;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* Enable clock channels for this port */
> val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
> @@ -1063,7 +1066,7 @@ void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
> vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
> vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
> }
>
> void vlv_phy_reset_lanes(struct intel_encoder *encoder,
> @@ -1075,8 +1078,8 @@ void vlv_phy_reset_lanes(struct intel_encoder *encoder,
> enum dpio_channel port = vlv_dport_to_channel(dport);
> enum pipe pipe = crtc->pipe;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
> vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
> vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
> }
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 3074448446bc..2304488f2d35 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -248,7 +248,7 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
> pconf0 = VLV_GPIO_PCONF0(map->base_offset);
> padval = VLV_GPIO_PAD_VAL(map->base_offset);
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
> if (!map->init) {
> /* FIXME: remove constant below */
> vlv_iosf_sb_write(dev_priv, port, pconf0, 0x2000CC00);
> @@ -257,7 +257,7 @@ static void vlv_exec_gpio(struct drm_i915_private *dev_priv,
>
> tmp = 0x4 | value;
> vlv_iosf_sb_write(dev_priv, port, padval, tmp);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
> }
>
> static void chv_exec_gpio(struct drm_i915_private *dev_priv,
> @@ -303,12 +303,12 @@ static void chv_exec_gpio(struct drm_i915_private *dev_priv,
> cfg0 = CHV_GPIO_PAD_CFG0(family_num, gpio_index);
> cfg1 = CHV_GPIO_PAD_CFG1(family_num, gpio_index);
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_iosf_sb_get(dev_priv, BIT(VLV_IOSF_SB_GPIO));
> vlv_iosf_sb_write(dev_priv, port, cfg1, 0);
> vlv_iosf_sb_write(dev_priv, port, cfg0,
> CHV_GPIO_GPIOEN | CHV_GPIO_GPIOCFG_GPO |
> CHV_GPIO_GPIOTXSTATE(value));
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_iosf_sb_put(dev_priv, BIT(VLV_IOSF_SB_GPIO));
> }
>
> static void bxt_exec_gpio(struct drm_i915_private *dev_priv,
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index e1005d7b75fd..8b72365f9309 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -2630,12 +2630,12 @@ static void chv_hdmi_post_disable(struct intel_encoder *encoder,
> struct drm_device *dev = encoder->base.dev;
> struct drm_i915_private *dev_priv = to_i915(dev);
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* Assert data lane reset */
> chv_data_lane_soft_reset(encoder, old_crtc_state, true);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
> }
>
> static void chv_hdmi_pre_enable(struct intel_encoder *encoder,
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 7aa9a8c12b54..6c2f416b95a6 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -7803,9 +7803,9 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
>
> vlv_init_gpll_ref_freq(dev_priv);
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_cck_get(dev_priv);
> val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_cck_put(dev_priv);
>
> switch ((val >> 2) & 0x7) {
> case 3:
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index d4f4262d0fee..9c1294c29566 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1569,7 +1569,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> 1))
> DRM_ERROR("Display PHY %d is not power up\n", phy);
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
>
> /* Enable dynamic power down */
> tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
> @@ -1592,7 +1592,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
> vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
> }
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
>
> dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
> I915_WRITE(DISPLAY_PHY_CONTROL, dev_priv->chv_phy_control);
> @@ -1655,9 +1655,9 @@ static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpi
> else
> reg = _CHV_CMN_DW6_CH1;
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_dpio_get(dev_priv);
> val = vlv_dpio_read(dev_priv, pipe, reg);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_dpio_put(dev_priv);
>
> /*
> * This assumes !override is only used when the port is disabled.
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index fc8913461622..b2fc605e2e29 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -73,6 +73,22 @@ static void __vlv_punit_put(struct drm_i915_private *i915)
> iosf_mbi_punit_release();
> }
>
> +void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports)
> +{
> + if (ports & BIT(VLV_IOSF_SB_PUNIT))
> + __vlv_punit_get(i915);
Should this be after the lock? Hmm, I guess we have the pcu_lock
already held for the punit access. Oh and __vlv_punut_get() itself
grabs the iosf_mbi lock.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> +
> + mutex_lock(&i915->sb_lock);
> +}
> +
> +void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports)
> +{
> + mutex_unlock(&i915->sb_lock);
> +
> + if (ports & BIT(VLV_IOSF_SB_PUNIT))
> + __vlv_punit_put(i915);
> +}
> +
> static int vlv_sideband_rw(struct drm_i915_private *i915,
> u32 devfn, u32 port, u32 opcode,
> u32 addr, u32 *val)
> @@ -82,6 +98,8 @@ static int vlv_sideband_rw(struct drm_i915_private *i915,
> int err;
>
> lockdep_assert_held(&i915->sb_lock);
> + if (port == IOSF_PORT_PUNIT)
> + iosf_mbi_assert_punit_acquired();
>
> /* Flush the previous comms, just in case it failed last time. */
> if (intel_wait_for_register(uncore,
> @@ -125,16 +143,14 @@ u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
> {
> u32 val = 0;
>
> - WARN_ON(!mutex_is_locked(&i915->pcu_lock));
> + lockdep_assert_held(&i915->pcu_lock);
>
> - mutex_lock(&i915->sb_lock);
> - __vlv_punit_get(i915);
> + vlv_punit_get(i915);
>
> vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> SB_CRRDDA_NP, addr, &val);
>
> - __vlv_punit_put(i915);
> - mutex_unlock(&i915->sb_lock);
> + vlv_punit_put(i915);
>
> return val;
> }
> @@ -143,16 +159,14 @@ int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
> {
> int err;
>
> - WARN_ON(!mutex_is_locked(&i915->pcu_lock));
> + lockdep_assert_held(&i915->pcu_lock);
>
> - mutex_lock(&i915->sb_lock);
> - __vlv_punit_get(i915);
> + vlv_punit_get(i915);
>
> err = vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> SB_CRWRDA_NP, addr, &val);
>
> - __vlv_punit_put(i915);
> - mutex_unlock(&i915->sb_lock);
> + vlv_punit_put(i915);
>
> return err;
> }
> @@ -177,12 +191,10 @@ u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
> {
> u32 val = 0;
>
> - WARN_ON(!mutex_is_locked(&i915->pcu_lock));
> -
> - mutex_lock(&i915->sb_lock);
> + vlv_nc_get(i915);
> vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
> SB_CRRDDA_NP, addr, &val);
> - mutex_unlock(&i915->sb_lock);
> + vlv_nc_put(i915);
>
> return val;
> }
> @@ -281,7 +293,8 @@ u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> enum intel_sbi_destination destination)
> {
> u32 value = 0;
> - WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
> +
> + lockdep_assert_held(&dev_priv->sb_lock);
>
> if (intel_wait_for_register(&dev_priv->uncore,
> SBI_CTL_STAT, SBI_BUSY, 0,
> @@ -321,7 +334,7 @@ void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> {
> u32 tmp;
>
> - WARN_ON(!mutex_is_locked(&dev_priv->sb_lock));
> + lockdep_assert_held(&dev_priv->sb_lock);
>
> if (intel_wait_for_register(&dev_priv->uncore,
> SBI_CTL_STAT, SBI_BUSY, 0,
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index e0b1ec821960..dc1839bfde3e 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -248,7 +248,7 @@ static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs,
>
> static void band_gap_reset(struct drm_i915_private *dev_priv)
> {
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_flisdsi_get(dev_priv);
>
> vlv_flisdsi_write(dev_priv, 0x08, 0x0001);
> vlv_flisdsi_write(dev_priv, 0x0F, 0x0005);
> @@ -257,7 +257,7 @@ static void band_gap_reset(struct drm_i915_private *dev_priv)
> vlv_flisdsi_write(dev_priv, 0x0F, 0x0000);
> vlv_flisdsi_write(dev_priv, 0x08, 0x0000);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_flisdsi_put(dev_priv);
> }
>
> static int bdw_get_pipemisc_bpp(struct intel_crtc *crtc)
> @@ -515,11 +515,11 @@ static void vlv_dsi_device_ready(struct intel_encoder *encoder)
>
> DRM_DEBUG_KMS("\n");
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_flisdsi_get(dev_priv);
> /* program rcomp for compliance, reduce from 50 ohms to 45 ohms
> * needed everytime after power gate */
> vlv_flisdsi_write(dev_priv, 0x04, 0x0004);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_flisdsi_put(dev_priv);
>
> /* bandgap reset is needed after everytime we do power gate */
> band_gap_reset(dev_priv);
> diff --git a/drivers/gpu/drm/i915/vlv_dsi_pll.c b/drivers/gpu/drm/i915/vlv_dsi_pll.c
> index 5e7b1fb2db5d..25b811174f5c 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi_pll.c
> @@ -149,7 +149,7 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder,
>
> DRM_DEBUG_KMS("\n");
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_cck_get(dev_priv);
>
> vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, 0);
> vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_DIVIDER, config->dsi_pll.div);
> @@ -166,11 +166,11 @@ void vlv_dsi_pll_enable(struct intel_encoder *encoder,
> if (wait_for(vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL) &
> DSI_PLL_LOCK, 20)) {
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_cck_put(dev_priv);
> DRM_ERROR("DSI PLL lock failed\n");
> return;
> }
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_cck_put(dev_priv);
>
> DRM_DEBUG_KMS("DSI PLL locked\n");
> }
> @@ -182,14 +182,14 @@ void vlv_dsi_pll_disable(struct intel_encoder *encoder)
>
> DRM_DEBUG_KMS("\n");
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_cck_get(dev_priv);
>
> tmp = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
> tmp &= ~DSI_PLL_VCO_EN;
> tmp |= DSI_PLL_LDO_GATE;
> vlv_cck_write(dev_priv, CCK_REG_DSI_PLL_CONTROL, tmp);
>
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_cck_put(dev_priv);
> }
>
> bool bxt_dsi_pll_is_enabled(struct drm_i915_private *dev_priv)
> @@ -266,10 +266,10 @@ u32 vlv_dsi_get_pclk(struct intel_encoder *encoder,
>
> DRM_DEBUG_KMS("\n");
>
> - mutex_lock(&dev_priv->sb_lock);
> + vlv_cck_get(dev_priv);
> pll_ctl = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_CONTROL);
> pll_div = vlv_cck_read(dev_priv, CCK_REG_DSI_PLL_DIVIDER);
> - mutex_unlock(&dev_priv->sb_lock);
> + vlv_cck_put(dev_priv);
>
> config->dsi_pll.ctrl = pll_ctl & ~DSI_PLL_LOCK;
> config->dsi_pll.div = pll_div;
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 03/10] drm/i915: Lift sideband locking for vlv_punit_(read|write)
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
2019-04-19 17:13 ` [PATCH 01/10] drm/i915: Disable preemption and sleeping while using the punit sideband Chris Wilson
2019-04-19 17:13 ` [PATCH 02/10] drm/i915: Lift acquiring the vlv punit magic to a common sb-get Chris Wilson
@ 2019-04-19 17:13 ` Chris Wilson
2019-04-23 17:14 ` Ville Syrjälä
2019-04-19 17:13 ` [PATCH 04/10] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview Chris Wilson
` (10 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:13 UTC (permalink / raw)
To: intel-gfx
Lift the sideband acquisition for vlv_punit_read and vlv_punit_write
into their callers, so that we can lock the sideband once for a sequence
of operations, rather than perform the heavyweight acquisition on each
request.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_debugfs.c | 5 +++
drivers/gpu/drm/i915/i915_sysfs.c | 14 ++++----
drivers/gpu/drm/i915/intel_cdclk.c | 23 ++++++++++---
drivers/gpu/drm/i915/intel_display.c | 16 +++++----
drivers/gpu/drm/i915/intel_pm.c | 46 ++++++++++++++++++++-----
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++
drivers/gpu/drm/i915/intel_sideband.c | 18 ++--------
7 files changed, 89 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 5823ffb17821..83253928e69d 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1056,7 +1056,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
GEN6_RP_MEDIA_SW_MODE));
+ vlv_punit_get(dev_priv);
freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(dev_priv);
+
seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
@@ -2029,8 +2032,10 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
act_freq = vlv_punit_read(dev_priv,
PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(dev_priv);
act_freq = (act_freq >> 8) & 0xff;
mutex_unlock(&dev_priv->pcu_lock);
} else {
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 41313005af42..bfabb3de4808 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -259,25 +259,25 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
{
struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
intel_wakeref_t wakeref;
- int ret;
+ u32 freq;
wakeref = intel_runtime_pm_get(dev_priv);
mutex_lock(&dev_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- u32 freq;
+ vlv_punit_get(dev_priv);
freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
- ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
+ vlv_punit_put(dev_priv);
+
+ freq = (freq >> 8) & 0xff;
} else {
- ret = intel_gpu_freq(dev_priv,
- intel_get_cagf(dev_priv,
- I915_READ(GEN6_RPSTAT1)));
+ freq = intel_get_cagf(dev_priv, I915_READ(GEN6_RPSTAT1));
}
mutex_unlock(&dev_priv->pcu_lock);
intel_runtime_pm_put(dev_priv, wakeref);
- return snprintf(buf, PAGE_SIZE, "%d\n", ret);
+ return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq));
}
static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 5845d0a37599..9dd22203a7e8 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -464,13 +464,19 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
{
u32 val;
+ mutex_lock(&dev_priv->pcu_lock);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
+
cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
CCK_DISPLAY_CLOCK_CONTROL,
cdclk_state->vco);
- mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
+
+ vlv_iosf_sb_put(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
mutex_unlock(&dev_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv))
@@ -545,6 +551,11 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_CCK) |
+ BIT(VLV_IOSF_SB_BUNIT) |
+ BIT(VLV_IOSF_SB_PUNIT));
+
mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
val &= ~DSPFREQGUAR_MASK;
@@ -557,9 +568,6 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
}
mutex_unlock(&dev_priv->pcu_lock);
- vlv_iosf_sb_get(dev_priv,
- BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));
-
if (cdclk == 400000) {
u32 divider;
@@ -593,7 +601,9 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
vlv_iosf_sb_put(dev_priv,
- BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));
+ BIT(VLV_IOSF_SB_CCK) |
+ BIT(VLV_IOSF_SB_BUNIT) |
+ BIT(VLV_IOSF_SB_PUNIT));
intel_update_cdclk(dev_priv);
@@ -630,6 +640,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
val &= ~DSPFREQGUAR_MASK_CHV;
val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
@@ -639,6 +650,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
50)) {
DRM_ERROR("timed out waiting for CDclk change\n");
}
+
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 11bb07650f87..68822f02dfc6 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -153,10 +153,8 @@ int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
/* Obtain SKU information */
- vlv_cck_get(dev_priv);
hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
CCK_FUSE_HPLL_FREQ_MASK;
- vlv_cck_put(dev_priv);
return vco_freq[hpll_freq] * 1000;
}
@@ -167,10 +165,7 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
u32 val;
int divider;
- vlv_cck_get(dev_priv);
val = vlv_cck_read(dev_priv, reg);
- vlv_cck_put(dev_priv);
-
divider = val & CCK_FREQUENCY_VALUES;
WARN((val & CCK_FREQUENCY_STATUS) !=
@@ -183,11 +178,18 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
const char *name, u32 reg)
{
+ int hpll;
+
+ vlv_cck_get(dev_priv);
+
if (dev_priv->hpll_freq == 0)
dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
- return vlv_get_cck_clock(dev_priv, name, reg,
- dev_priv->hpll_freq);
+ hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
+
+ vlv_cck_put(dev_priv);
+
+ return hpll;
}
static void intel_update_czclk(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 6c2f416b95a6..9db39ea9bd83 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -318,6 +318,7 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
u32 val;
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
if (enable)
@@ -332,6 +333,7 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
}
@@ -340,6 +342,7 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
u32 val;
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
if (enable)
@@ -348,6 +351,7 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
val &= ~DSP_MAXFIFO_PM5_ENABLE;
vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
}
@@ -6140,6 +6144,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
if (IS_CHERRYVIEW(dev_priv)) {
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
if (val & DSP_MAXFIFO_PM5_ENABLE)
@@ -6169,6 +6174,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
wm->level = VLV_WM_LEVEL_DDR_DVFS;
}
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
}
@@ -6743,7 +6749,9 @@ static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
if (val != dev_priv->gt_pm.rps.cur_freq) {
+ vlv_punit_get(dev_priv);
err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
+ vlv_punit_put(dev_priv);
if (err)
return err;
@@ -7755,6 +7763,11 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
valleyview_setup_pctx(dev_priv);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_PUNIT) |
+ BIT(VLV_IOSF_SB_NC) |
+ BIT(VLV_IOSF_SB_CCK));
+
vlv_init_gpll_ref_freq(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
@@ -7792,6 +7805,11 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
intel_gpu_freq(dev_priv, rps->min_freq),
rps->min_freq);
+
+ vlv_iosf_sb_put(dev_priv,
+ BIT(VLV_IOSF_SB_PUNIT) |
+ BIT(VLV_IOSF_SB_NC) |
+ BIT(VLV_IOSF_SB_CCK));
}
static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
@@ -7801,11 +7819,14 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
cherryview_setup_pctx(dev_priv);
+ vlv_iosf_sb_get(dev_priv,
+ BIT(VLV_IOSF_SB_PUNIT) |
+ BIT(VLV_IOSF_SB_NC) |
+ BIT(VLV_IOSF_SB_CCK));
+
vlv_init_gpll_ref_freq(dev_priv);
- vlv_cck_get(dev_priv);
val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
- vlv_cck_put(dev_priv);
switch ((val >> 2) & 0x7) {
case 3:
@@ -7838,6 +7859,11 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
intel_gpu_freq(dev_priv, rps->min_freq),
rps->min_freq);
+ vlv_iosf_sb_put(dev_priv,
+ BIT(VLV_IOSF_SB_PUNIT) |
+ BIT(VLV_IOSF_SB_NC) |
+ BIT(VLV_IOSF_SB_CCK));
+
WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
rps->min_freq) & 1,
"Odd GPU freq values\n");
@@ -7925,13 +7951,15 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
GEN6_RP_DOWN_IDLE_AVG);
/* Setting Fixed Bias */
- val = VLV_OVERRIDE_EN |
- VLV_SOC_TDP_EN |
- CHV_BIAS_CPU_50_SOC_50;
+ vlv_punit_get(dev_priv);
+
+ val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50;
vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(dev_priv);
+
/* RPS code assumes GPLL is used */
WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
@@ -8008,14 +8036,16 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_CONT);
+ vlv_punit_get(dev_priv);
+
/* Setting Fixed Bias */
- val = VLV_OVERRIDE_EN |
- VLV_SOC_TDP_EN |
- VLV_BIAS_CPU_125_SOC_875;
+ val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875;
vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
+ vlv_punit_put(dev_priv);
+
/* RPS code assumes GPLL is used */
WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index 9c1294c29566..ac8bc5baef40 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1212,6 +1212,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
PUNIT_PWRGT_PWR_GATE(pw_idx);
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
#define COND \
((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
@@ -1232,6 +1233,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
#undef COND
out:
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
}
@@ -1260,6 +1262,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
/*
@@ -1278,6 +1281,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
WARN_ON(ctrl != state);
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
return enabled;
@@ -1765,6 +1769,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
u32 state, ctrl;
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
/*
@@ -1781,6 +1786,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
WARN_ON(ctrl << 16 != state);
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
return enabled;
@@ -1797,6 +1803,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
#define COND \
((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
@@ -1817,6 +1824,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
#undef COND
out:
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
}
@@ -4012,7 +4020,9 @@ static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0
bool ret;
mutex_lock(&dev_priv->pcu_lock);
+ vlv_punit_get(dev_priv);
ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
+ vlv_punit_put(dev_priv);
mutex_unlock(&dev_priv->pcu_lock);
return ret;
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index b2fc605e2e29..7c33925f52f9 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -145,30 +145,18 @@ u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
lockdep_assert_held(&i915->pcu_lock);
- vlv_punit_get(i915);
-
vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRRDDA_NP, addr, &val);
- vlv_punit_put(i915);
-
return val;
}
int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
{
- int err;
-
lockdep_assert_held(&i915->pcu_lock);
- vlv_punit_get(i915);
-
- err = vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
- SB_CRWRDA_NP, addr, &val);
-
- vlv_punit_put(i915);
-
- return err;
+ return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
+ SB_CRWRDA_NP, addr, &val);
}
u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
@@ -191,10 +179,8 @@ u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
{
u32 val = 0;
- vlv_nc_get(i915);
vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
SB_CRRDDA_NP, addr, &val);
- vlv_nc_put(i915);
return val;
}
--
2.20.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 03/10] drm/i915: Lift sideband locking for vlv_punit_(read|write)
2019-04-19 17:13 ` [PATCH 03/10] drm/i915: Lift sideband locking for vlv_punit_(read|write) Chris Wilson
@ 2019-04-23 17:14 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2019-04-23 17:14 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Apr 19, 2019 at 06:13:55PM +0100, Chris Wilson wrote:
> Lift the sideband acquisition for vlv_punit_read and vlv_punit_write
> into their callers, so that we can lock the sideband once for a sequence
> of operations, rather than perform the heavyweight acquisition on each
> request.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_debugfs.c | 5 +++
> drivers/gpu/drm/i915/i915_sysfs.c | 14 ++++----
> drivers/gpu/drm/i915/intel_cdclk.c | 23 ++++++++++---
> drivers/gpu/drm/i915/intel_display.c | 16 +++++----
> drivers/gpu/drm/i915/intel_pm.c | 46 ++++++++++++++++++++-----
> drivers/gpu/drm/i915/intel_runtime_pm.c | 10 ++++++
> drivers/gpu/drm/i915/intel_sideband.c | 18 ++--------
> 7 files changed, 89 insertions(+), 43 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 5823ffb17821..83253928e69d 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -1056,7 +1056,10 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
> yesno((rpmodectl & GEN6_RP_MEDIA_MODE_MASK) ==
> GEN6_RP_MEDIA_SW_MODE));
>
> + vlv_punit_get(dev_priv);
> freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> + vlv_punit_put(dev_priv);
> +
> seq_printf(m, "PUNIT_REG_GPU_FREQ_STS: 0x%08x\n", freq_sts);
> seq_printf(m, "DDR freq: %d MHz\n", dev_priv->mem_freq);
>
> @@ -2029,8 +2032,10 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
> with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
> act_freq = vlv_punit_read(dev_priv,
> PUNIT_REG_GPU_FREQ_STS);
> + vlv_punit_put(dev_priv);
> act_freq = (act_freq >> 8) & 0xff;
> mutex_unlock(&dev_priv->pcu_lock);
> } else {
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 41313005af42..bfabb3de4808 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -259,25 +259,25 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
> {
> struct drm_i915_private *dev_priv = kdev_minor_to_i915(kdev);
> intel_wakeref_t wakeref;
> - int ret;
> + u32 freq;
>
> wakeref = intel_runtime_pm_get(dev_priv);
>
> mutex_lock(&dev_priv->pcu_lock);
> if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
> - u32 freq;
> + vlv_punit_get(dev_priv);
> freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> - ret = intel_gpu_freq(dev_priv, (freq >> 8) & 0xff);
> + vlv_punit_put(dev_priv);
> +
> + freq = (freq >> 8) & 0xff;
> } else {
> - ret = intel_gpu_freq(dev_priv,
> - intel_get_cagf(dev_priv,
> - I915_READ(GEN6_RPSTAT1)));
> + freq = intel_get_cagf(dev_priv, I915_READ(GEN6_RPSTAT1));
> }
> mutex_unlock(&dev_priv->pcu_lock);
>
> intel_runtime_pm_put(dev_priv, wakeref);
>
> - return snprintf(buf, PAGE_SIZE, "%d\n", ret);
> + return snprintf(buf, PAGE_SIZE, "%d\n", intel_gpu_freq(dev_priv, freq));
> }
>
> static ssize_t gt_cur_freq_mhz_show(struct device *kdev,
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 5845d0a37599..9dd22203a7e8 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -464,13 +464,19 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
> {
> u32 val;
>
> + mutex_lock(&dev_priv->pcu_lock);
> + vlv_iosf_sb_get(dev_priv,
> + BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
> +
> cdclk_state->vco = vlv_get_hpll_vco(dev_priv);
> cdclk_state->cdclk = vlv_get_cck_clock(dev_priv, "cdclk",
> CCK_DISPLAY_CLOCK_CONTROL,
> cdclk_state->vco);
>
> - mutex_lock(&dev_priv->pcu_lock);
> val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> +
> + vlv_iosf_sb_put(dev_priv,
> + BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
> mutex_unlock(&dev_priv->pcu_lock);
>
> if (IS_VALLEYVIEW(dev_priv))
> @@ -545,6 +551,11 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> */
> wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>
> + vlv_iosf_sb_get(dev_priv,
> + BIT(VLV_IOSF_SB_CCK) |
> + BIT(VLV_IOSF_SB_BUNIT) |
> + BIT(VLV_IOSF_SB_PUNIT));
> +
> mutex_lock(&dev_priv->pcu_lock);
> val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> val &= ~DSPFREQGUAR_MASK;
> @@ -557,9 +568,6 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> }
> mutex_unlock(&dev_priv->pcu_lock);
>
> - vlv_iosf_sb_get(dev_priv,
> - BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));
> -
> if (cdclk == 400000) {
> u32 divider;
>
> @@ -593,7 +601,9 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
> vlv_bunit_write(dev_priv, BUNIT_REG_BISOC, val);
>
> vlv_iosf_sb_put(dev_priv,
> - BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_BUNIT));
> + BIT(VLV_IOSF_SB_CCK) |
> + BIT(VLV_IOSF_SB_BUNIT) |
> + BIT(VLV_IOSF_SB_PUNIT));
>
> intel_update_cdclk(dev_priv);
>
> @@ -630,6 +640,7 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
> wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
>
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
> val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> val &= ~DSPFREQGUAR_MASK_CHV;
> val |= (cmd << DSPFREQGUAR_SHIFT_CHV);
> @@ -639,6 +650,8 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
> 50)) {
> DRM_ERROR("timed out waiting for CDclk change\n");
> }
> +
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
>
> intel_update_cdclk(dev_priv);
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 11bb07650f87..68822f02dfc6 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -153,10 +153,8 @@ int vlv_get_hpll_vco(struct drm_i915_private *dev_priv)
> int hpll_freq, vco_freq[] = { 800, 1600, 2000, 2400 };
>
> /* Obtain SKU information */
> - vlv_cck_get(dev_priv);
> hpll_freq = vlv_cck_read(dev_priv, CCK_FUSE_REG) &
> CCK_FUSE_HPLL_FREQ_MASK;
> - vlv_cck_put(dev_priv);
>
> return vco_freq[hpll_freq] * 1000;
> }
> @@ -167,10 +165,7 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
> u32 val;
> int divider;
>
> - vlv_cck_get(dev_priv);
> val = vlv_cck_read(dev_priv, reg);
> - vlv_cck_put(dev_priv);
> -
> divider = val & CCK_FREQUENCY_VALUES;
>
> WARN((val & CCK_FREQUENCY_STATUS) !=
> @@ -183,11 +178,18 @@ int vlv_get_cck_clock(struct drm_i915_private *dev_priv,
> int vlv_get_cck_clock_hpll(struct drm_i915_private *dev_priv,
> const char *name, u32 reg)
> {
> + int hpll;
> +
> + vlv_cck_get(dev_priv);
> +
> if (dev_priv->hpll_freq == 0)
> dev_priv->hpll_freq = vlv_get_hpll_vco(dev_priv);
>
> - return vlv_get_cck_clock(dev_priv, name, reg,
> - dev_priv->hpll_freq);
> + hpll = vlv_get_cck_clock(dev_priv, name, reg, dev_priv->hpll_freq);
> +
> + vlv_cck_put(dev_priv);
> +
> + return hpll;
> }
>
> static void intel_update_czclk(struct drm_i915_private *dev_priv)
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 6c2f416b95a6..9db39ea9bd83 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -318,6 +318,7 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
> u32 val;
>
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
> if (enable)
> @@ -332,6 +333,7 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
> FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
> DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
>
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
> }
>
> @@ -340,6 +342,7 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
> u32 val;
>
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> if (enable)
> @@ -348,6 +351,7 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
> val &= ~DSP_MAXFIFO_PM5_ENABLE;
> vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
>
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
> }
>
> @@ -6140,6 +6144,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
>
> if (IS_CHERRYVIEW(dev_priv)) {
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> if (val & DSP_MAXFIFO_PM5_ENABLE)
> @@ -6169,6 +6174,7 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
> wm->level = VLV_WM_LEVEL_DDR_DVFS;
> }
>
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
> }
>
> @@ -6743,7 +6749,9 @@ static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
> I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
>
> if (val != dev_priv->gt_pm.rps.cur_freq) {
> + vlv_punit_get(dev_priv);
> err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
> + vlv_punit_put(dev_priv);
> if (err)
> return err;
>
> @@ -7755,6 +7763,11 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
>
> valleyview_setup_pctx(dev_priv);
>
> + vlv_iosf_sb_get(dev_priv,
> + BIT(VLV_IOSF_SB_PUNIT) |
> + BIT(VLV_IOSF_SB_NC) |
> + BIT(VLV_IOSF_SB_CCK));
These are now rather far from the actual sideband accesses. Should we
store the bitmask somewhere and sprinkle in some asserts into the
sideband access funcs to cross check the two? Not that it really matters
since only the punit bit has a special meaning, at least for now.
> +
> vlv_init_gpll_ref_freq(dev_priv);
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
> @@ -7792,6 +7805,11 @@ static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
> DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
> intel_gpu_freq(dev_priv, rps->min_freq),
> rps->min_freq);
> +
> + vlv_iosf_sb_put(dev_priv,
> + BIT(VLV_IOSF_SB_PUNIT) |
> + BIT(VLV_IOSF_SB_NC) |
> + BIT(VLV_IOSF_SB_CCK));
> }
>
> static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
> @@ -7801,11 +7819,14 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
>
> cherryview_setup_pctx(dev_priv);
>
> + vlv_iosf_sb_get(dev_priv,
> + BIT(VLV_IOSF_SB_PUNIT) |
> + BIT(VLV_IOSF_SB_NC) |
IIRC CHV doesn't access NC here.
With that sorted
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> + BIT(VLV_IOSF_SB_CCK));
> +
> vlv_init_gpll_ref_freq(dev_priv);
>
> - vlv_cck_get(dev_priv);
> val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
> - vlv_cck_put(dev_priv);
>
> switch ((val >> 2) & 0x7) {
> case 3:
> @@ -7838,6 +7859,11 @@ static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
> intel_gpu_freq(dev_priv, rps->min_freq),
> rps->min_freq);
>
> + vlv_iosf_sb_put(dev_priv,
> + BIT(VLV_IOSF_SB_PUNIT) |
> + BIT(VLV_IOSF_SB_NC) |
> + BIT(VLV_IOSF_SB_CCK));
> +
> WARN_ONCE((rps->max_freq | rps->efficient_freq | rps->rp1_freq |
> rps->min_freq) & 1,
> "Odd GPU freq values\n");
> @@ -7925,13 +7951,15 @@ static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
> GEN6_RP_DOWN_IDLE_AVG);
>
> /* Setting Fixed Bias */
> - val = VLV_OVERRIDE_EN |
> - VLV_SOC_TDP_EN |
> - CHV_BIAS_CPU_50_SOC_50;
> + vlv_punit_get(dev_priv);
> +
> + val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | CHV_BIAS_CPU_50_SOC_50;
> vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>
> + vlv_punit_put(dev_priv);
> +
> /* RPS code assumes GPLL is used */
> WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
>
> @@ -8008,14 +8036,16 @@ static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
> GEN6_RP_UP_BUSY_AVG |
> GEN6_RP_DOWN_IDLE_CONT);
>
> + vlv_punit_get(dev_priv);
> +
> /* Setting Fixed Bias */
> - val = VLV_OVERRIDE_EN |
> - VLV_SOC_TDP_EN |
> - VLV_BIAS_CPU_125_SOC_875;
> + val = VLV_OVERRIDE_EN | VLV_SOC_TDP_EN | VLV_BIAS_CPU_125_SOC_875;
> vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
>
> val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
>
> + vlv_punit_put(dev_priv);
> +
> /* RPS code assumes GPLL is used */
> WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
>
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index 9c1294c29566..ac8bc5baef40 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -1212,6 +1212,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
> PUNIT_PWRGT_PWR_GATE(pw_idx);
>
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
>
> #define COND \
> ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
> @@ -1232,6 +1233,7 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
> #undef COND
>
> out:
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
> }
>
> @@ -1260,6 +1262,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
> ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
>
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
>
> state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
> /*
> @@ -1278,6 +1281,7 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
> ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
> WARN_ON(ctrl != state);
>
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
>
> return enabled;
> @@ -1765,6 +1769,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
> u32 state, ctrl;
>
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
>
> state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
> /*
> @@ -1781,6 +1786,7 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
> ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
> WARN_ON(ctrl << 16 != state);
>
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
>
> return enabled;
> @@ -1797,6 +1803,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
> state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
>
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
>
> #define COND \
> ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
> @@ -1817,6 +1824,7 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
> #undef COND
>
> out:
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
> }
>
> @@ -4012,7 +4020,9 @@ static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0
> bool ret;
>
> mutex_lock(&dev_priv->pcu_lock);
> + vlv_punit_get(dev_priv);
> ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
> + vlv_punit_put(dev_priv);
> mutex_unlock(&dev_priv->pcu_lock);
>
> return ret;
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index b2fc605e2e29..7c33925f52f9 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -145,30 +145,18 @@ u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
>
> lockdep_assert_held(&i915->pcu_lock);
>
> - vlv_punit_get(i915);
> -
> vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> SB_CRRDDA_NP, addr, &val);
>
> - vlv_punit_put(i915);
> -
> return val;
> }
>
> int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
> {
> - int err;
> -
> lockdep_assert_held(&i915->pcu_lock);
>
> - vlv_punit_get(i915);
> -
> - err = vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> - SB_CRWRDA_NP, addr, &val);
> -
> - vlv_punit_put(i915);
> -
> - return err;
> + return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
> + SB_CRWRDA_NP, addr, &val);
> }
>
> u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg)
> @@ -191,10 +179,8 @@ u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr)
> {
> u32 val = 0;
>
> - vlv_nc_get(i915);
> vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_NC,
> SB_CRRDDA_NP, addr, &val);
> - vlv_nc_put(i915);
>
> return val;
> }
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 04/10] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (2 preceding siblings ...)
2019-04-19 17:13 ` [PATCH 03/10] drm/i915: Lift sideband locking for vlv_punit_(read|write) Chris Wilson
@ 2019-04-19 17:13 ` Chris Wilson
2019-04-23 17:15 ` Ville Syrjälä
2019-04-19 17:13 ` [PATCH 05/10] Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3" Chris Wilson
` (9 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:13 UTC (permalink / raw)
To: intel-gfx
Valleyview and Cherryview update the GPU frequency via the punit, which
is very expensive as we have to ensure the cores do not sleep during the
comms. If we perform frequent RPS evaluations, the frequent punit
requests cause measurable system overhead for little benefit, so
increase the evaluation intervals to reduce the number of times we try
and change frequency.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
1 file changed, 13 insertions(+)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9db39ea9bd83..ba6d3d1adf6c 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6593,6 +6593,19 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
break;
}
+ if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
+ /*
+ * Baytrail and Braswell control the gpu frequency via the
+ * punit, which is very slow and expensive to communicate with,
+ * as we synchronously force the package to C0. If we try and
+ * update the gpufreq too often we cause measurable system
+ * load for little benefit (effectively stealing CPU time for
+ * the GPU, negatively impacting overall throughput).
+ */
+ ei_up <<= 2;
+ ei_down <<= 2;
+ }
+
/* When byt can survive without system hang with dynamic
* sw freq adjustments, this restriction can be lifted.
*/
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 04/10] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
2019-04-19 17:13 ` [PATCH 04/10] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview Chris Wilson
@ 2019-04-23 17:15 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2019-04-23 17:15 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Apr 19, 2019 at 06:13:56PM +0100, Chris Wilson wrote:
> Valleyview and Cherryview update the GPU frequency via the punit, which
> is very expensive as we have to ensure the cores do not sleep during the
> comms. If we perform frequent RPS evaluations, the frequent punit
> requests cause measurable system overhead for little benefit, so
> increase the evaluation intervals to reduce the number of times we try
> and change frequency.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/intel_pm.c | 13 +++++++++++++
> 1 file changed, 13 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index 9db39ea9bd83..ba6d3d1adf6c 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -6593,6 +6593,19 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
> break;
> }
>
> + if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Since you added the qos only for vlv do we still want to keep chv here?
> + /*
> + * Baytrail and Braswell control the gpu frequency via the
> + * punit, which is very slow and expensive to communicate with,
> + * as we synchronously force the package to C0. If we try and
> + * update the gpufreq too often we cause measurable system
> + * load for little benefit (effectively stealing CPU time for
> + * the GPU, negatively impacting overall throughput).
> + */
> + ei_up <<= 2;
> + ei_down <<= 2;
> + }
> +
> /* When byt can survive without system hang with dynamic
> * sw freq adjustments, this restriction can be lifted.
> */
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 05/10] Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (3 preceding siblings ...)
2019-04-19 17:13 ` [PATCH 04/10] drm/i915: Reduce RPS update frequency on Valleyview/Cherryview Chris Wilson
@ 2019-04-19 17:13 ` Chris Wilson
2019-04-19 17:13 ` [PATCH 06/10] drm/i915: Replace pcu_lock with sb_lock Chris Wilson
` (8 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:13 UTC (permalink / raw)
To: intel-gfx; +Cc: Len Brown, Jani Nikula, Daniel Vetter, fritsch
With the vlv sideband fixed to avoid sleeping while we talk to the
punit, the system should be much more stable and be able to utilise the
punit without risk.
This reverts commit 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation
thresholds on Baytrail v3")
References: 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3")
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Cc: Len Brown <len.brown@intel.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Jani Nikula <jani.nikula@intel.com>
Cc: fritsch@xbmc.org
---
drivers/gpu/drm/i915/intel_pm.c | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index ba6d3d1adf6c..df33555b8053 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -6606,12 +6606,6 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
ei_down <<= 2;
}
- /* When byt can survive without system hang with dynamic
- * sw freq adjustments, this restriction can be lifted.
- */
- if (IS_VALLEYVIEW(dev_priv))
- goto skip_hw_write;
-
I915_WRITE(GEN6_RP_UP_EI,
GT_INTERVAL_FROM_US(dev_priv, ei_up));
I915_WRITE(GEN6_RP_UP_THRESHOLD,
@@ -6632,7 +6626,6 @@ static void rps_set_power(struct drm_i915_private *dev_priv, int new_power)
GEN6_RP_UP_BUSY_AVG |
GEN6_RP_DOWN_IDLE_AVG);
-skip_hw_write:
rps->power.mode = new_power;
rps->power.up_threshold = threshold_up;
rps->power.down_threshold = threshold_down;
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 06/10] drm/i915: Replace pcu_lock with sb_lock
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (4 preceding siblings ...)
2019-04-19 17:13 ` [PATCH 05/10] Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3" Chris Wilson
@ 2019-04-19 17:13 ` Chris Wilson
2019-04-19 17:13 ` [PATCH 07/10] drm/i915: Separate sideband declarations to intel_sideband.h Chris Wilson
` (7 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:13 UTC (permalink / raw)
To: intel-gfx; +Cc: Sagar Arun Kamble
We now have two locks for sideband access. The general one covering
sideband access across all generation, sb_lock, and a specific one
covering sideband access via the punit on vlv/chv. After lifting the
sb_lock around the punit into the callers, the pcu_lock is now redudant
and can be separated from its other use to regulate RPS (essentially
giving RPS a lock all of its own).
v2: Extract a couple of minor bug fixes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Sagar Arun Kamble <sagar.a.kamble@intel.com>
---
drivers/gpu/drm/i915/i915_debugfs.c | 25 +----
drivers/gpu/drm/i915/i915_drv.h | 10 +-
drivers/gpu/drm/i915/i915_irq.c | 4 +-
drivers/gpu/drm/i915/i915_sysfs.c | 32 +++---
drivers/gpu/drm/i915/intel_cdclk.c | 28 ------
drivers/gpu/drm/i915/intel_display.c | 6 --
drivers/gpu/drm/i915/intel_hdcp.c | 2 -
drivers/gpu/drm/i915/intel_pm.c | 128 ++++++++++++------------
drivers/gpu/drm/i915/intel_runtime_pm.c | 10 --
drivers/gpu/drm/i915/intel_sideband.c | 4 -
10 files changed, 83 insertions(+), 166 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 83253928e69d..93fd82a6ac2b 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -1045,8 +1045,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
} else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
u32 rpmodectl, freq_sts;
- mutex_lock(&dev_priv->pcu_lock);
-
rpmodectl = I915_READ(GEN6_RP_CONTROL);
seq_printf(m, "Video Turbo Mode: %s\n",
yesno(rpmodectl & GEN6_RP_MEDIA_TURBO));
@@ -1081,7 +1079,6 @@ static int i915_frequency_info(struct seq_file *m, void *unused)
seq_printf(m,
"efficient (RPe) frequency: %d MHz\n",
intel_gpu_freq(dev_priv, rps->efficient_freq));
- mutex_unlock(&dev_priv->pcu_lock);
} else if (INTEL_GEN(dev_priv) >= 6) {
u32 rp_state_limits;
u32 gt_perf_status;
@@ -1486,12 +1483,9 @@ static int gen6_drpc_info(struct seq_file *m)
gen9_powergate_status = I915_READ(GEN9_PWRGT_DOMAIN_STATUS);
}
- if (INTEL_GEN(dev_priv) <= 7) {
- mutex_lock(&dev_priv->pcu_lock);
+ if (INTEL_GEN(dev_priv) <= 7)
sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS,
&rc6vids);
- mutex_unlock(&dev_priv->pcu_lock);
- }
seq_printf(m, "RC1e Enabled: %s\n",
yesno(rcctl1 & GEN6_RC_CTL_RC1e_ENABLE));
@@ -1755,17 +1749,10 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
unsigned int max_gpu_freq, min_gpu_freq;
intel_wakeref_t wakeref;
int gpu_freq, ia_freq;
- int ret;
if (!HAS_LLC(dev_priv))
return -ENODEV;
- wakeref = intel_runtime_pm_get(dev_priv);
-
- ret = mutex_lock_interruptible(&dev_priv->pcu_lock);
- if (ret)
- goto out;
-
min_gpu_freq = rps->min_freq;
max_gpu_freq = rps->max_freq;
if (IS_GEN9_BC(dev_priv) || INTEL_GEN(dev_priv) >= 10) {
@@ -1776,6 +1763,7 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
seq_puts(m, "GPU freq (MHz)\tEffective CPU freq (MHz)\tEffective Ring freq (MHz)\n");
+ wakeref = intel_runtime_pm_get(dev_priv);
for (gpu_freq = min_gpu_freq; gpu_freq <= max_gpu_freq; gpu_freq++) {
ia_freq = gpu_freq;
sandybridge_pcode_read(dev_priv,
@@ -1789,12 +1777,9 @@ static int i915_ring_freq_table(struct seq_file *m, void *unused)
((ia_freq >> 0) & 0xff) * 100,
((ia_freq >> 8) & 0xff) * 100);
}
-
- mutex_unlock(&dev_priv->pcu_lock);
-
-out:
intel_runtime_pm_put(dev_priv, wakeref);
- return ret;
+
+ return 0;
}
static int i915_opregion(struct seq_file *m, void *unused)
@@ -2031,13 +2016,11 @@ static int i915_rps_boost_info(struct seq_file *m, void *data)
with_intel_runtime_pm_if_in_use(dev_priv, wakeref) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
act_freq = vlv_punit_read(dev_priv,
PUNIT_REG_GPU_FREQ_STS);
vlv_punit_put(dev_priv);
act_freq = (act_freq >> 8) & 0xff;
- mutex_unlock(&dev_priv->pcu_lock);
} else {
act_freq = intel_get_cagf(dev_priv,
I915_READ(GEN6_RPSTAT1));
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 162d988dbceb..6eb12f11ab65 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -648,6 +648,8 @@ struct intel_rps_ei {
};
struct intel_rps {
+ struct mutex lock; /* protects enabling and the worker */
+
/*
* work, interrupts_enabled and pm_iir are protected by
* dev_priv->irq_lock
@@ -1710,14 +1712,6 @@ struct drm_i915_private {
*/
u32 edram_size_mb;
- /*
- * Protects RPS/RC6 register access and PCU communication.
- * Must be taken after struct_mutex if nested. Note that
- * this lock may be held for long periods of time when
- * talking to hw - so only take it when talking to hw!
- */
- struct mutex pcu_lock;
-
/* gen6+ GT PM state */
struct intel_gen6_power_mgmt gt_pm;
diff --git a/drivers/gpu/drm/i915/i915_irq.c b/drivers/gpu/drm/i915/i915_irq.c
index b92cfd69134b..15f5415a0aa2 100644
--- a/drivers/gpu/drm/i915/i915_irq.c
+++ b/drivers/gpu/drm/i915/i915_irq.c
@@ -1301,7 +1301,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
goto out;
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&rps->lock);
pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
@@ -1367,7 +1367,7 @@ static void gen6_pm_rps_work(struct work_struct *work)
rps->last_adj = 0;
}
- mutex_unlock(&dev_priv->pcu_lock);
+ mutex_unlock(&rps->lock);
out:
/* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index bfabb3de4808..0952d6a70e1f 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -263,7 +263,6 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
wakeref = intel_runtime_pm_get(dev_priv);
- mutex_lock(&dev_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
vlv_punit_get(dev_priv);
freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
@@ -273,7 +272,6 @@ static ssize_t gt_act_freq_mhz_show(struct device *kdev,
} else {
freq = intel_get_cagf(dev_priv, I915_READ(GEN6_RPSTAT1));
}
- mutex_unlock(&dev_priv->pcu_lock);
intel_runtime_pm_put(dev_priv, wakeref);
@@ -318,12 +316,12 @@ static ssize_t gt_boost_freq_mhz_store(struct device *kdev,
if (val < rps->min_freq || val > rps->max_freq)
return -EINVAL;
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&rps->lock);
if (val != rps->boost_freq) {
rps->boost_freq = val;
boost = atomic_read(&rps->num_waiters);
}
- mutex_unlock(&dev_priv->pcu_lock);
+ mutex_unlock(&rps->lock);
if (boost)
schedule_work(&rps->work);
@@ -364,17 +362,14 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
return ret;
wakeref = intel_runtime_pm_get(dev_priv);
-
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&rps->lock);
val = intel_freq_opcode(dev_priv, val);
-
if (val < rps->min_freq ||
val > rps->max_freq ||
val < rps->min_freq_softlimit) {
- mutex_unlock(&dev_priv->pcu_lock);
- intel_runtime_pm_put(dev_priv, wakeref);
- return -EINVAL;
+ ret = -EINVAL;
+ goto unlock;
}
if (val > rps->rp0_freq)
@@ -392,8 +387,8 @@ static ssize_t gt_max_freq_mhz_store(struct device *kdev,
* frequency request may be unchanged. */
ret = intel_set_rps(dev_priv, val);
- mutex_unlock(&dev_priv->pcu_lock);
-
+unlock:
+ mutex_unlock(&rps->lock);
intel_runtime_pm_put(dev_priv, wakeref);
return ret ?: count;
@@ -423,17 +418,14 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
return ret;
wakeref = intel_runtime_pm_get(dev_priv);
-
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&rps->lock);
val = intel_freq_opcode(dev_priv, val);
-
if (val < rps->min_freq ||
val > rps->max_freq ||
val > rps->max_freq_softlimit) {
- mutex_unlock(&dev_priv->pcu_lock);
- intel_runtime_pm_put(dev_priv, wakeref);
- return -EINVAL;
+ ret = -EINVAL;
+ goto unlock;
}
rps->min_freq_softlimit = val;
@@ -447,8 +439,8 @@ static ssize_t gt_min_freq_mhz_store(struct device *kdev,
* frequency request may be unchanged. */
ret = intel_set_rps(dev_priv, val);
- mutex_unlock(&dev_priv->pcu_lock);
-
+unlock:
+ mutex_unlock(&rps->lock);
intel_runtime_pm_put(dev_priv, wakeref);
return ret ?: count;
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 9dd22203a7e8..2bc5d3227a24 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -464,7 +464,6 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
{
u32 val;
- mutex_lock(&dev_priv->pcu_lock);
vlv_iosf_sb_get(dev_priv,
BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
@@ -477,7 +476,6 @@ static void vlv_get_cdclk(struct drm_i915_private *dev_priv,
vlv_iosf_sb_put(dev_priv,
BIT(VLV_IOSF_SB_CCK) | BIT(VLV_IOSF_SB_PUNIT));
- mutex_unlock(&dev_priv->pcu_lock);
if (IS_VALLEYVIEW(dev_priv))
cdclk_state->voltage_level = (val & DSPFREQGUAR_MASK) >>
@@ -556,7 +554,6 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
BIT(VLV_IOSF_SB_BUNIT) |
BIT(VLV_IOSF_SB_PUNIT));
- mutex_lock(&dev_priv->pcu_lock);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
val &= ~DSPFREQGUAR_MASK;
val |= (cmd << DSPFREQGUAR_SHIFT);
@@ -566,7 +563,6 @@ static void vlv_set_cdclk(struct drm_i915_private *dev_priv,
50)) {
DRM_ERROR("timed out waiting for CDclk change\n");
}
- mutex_unlock(&dev_priv->pcu_lock);
if (cdclk == 400000) {
u32 divider;
@@ -639,7 +635,6 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
*/
wakeref = intel_display_power_get(dev_priv, POWER_DOMAIN_PIPE_A);
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
val &= ~DSPFREQGUAR_MASK_CHV;
@@ -652,7 +647,6 @@ static void chv_set_cdclk(struct drm_i915_private *dev_priv,
}
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
@@ -731,10 +725,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
"trying to change cdclk frequency with cdclk not enabled\n"))
return;
- mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_write(dev_priv,
BDW_PCODE_DISPLAY_FREQ_CHANGE_REQ, 0x0);
- mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
DRM_ERROR("failed to inform pcode about cdclk change\n");
return;
@@ -783,10 +775,8 @@ static void bdw_set_cdclk(struct drm_i915_private *dev_priv,
LCPLL_CD_SOURCE_FCLK_DONE) == 0, 1))
DRM_ERROR("Switching back to LCPLL failed\n");
- mutex_lock(&dev_priv->pcu_lock);
sandybridge_pcode_write(dev_priv, HSW_PCODE_DE_WRITE_FREQ_REQ,
cdclk_state->voltage_level);
- mutex_unlock(&dev_priv->pcu_lock);
I915_WRITE(CDCLK_FREQ, DIV_ROUND_CLOSEST(cdclk, 1000) - 1);
@@ -1025,12 +1015,10 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
*/
WARN_ON_ONCE(IS_SKYLAKE(dev_priv) && vco == 8640000);
- mutex_lock(&dev_priv->pcu_lock);
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
- mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
ret);
@@ -1094,10 +1082,8 @@ static void skl_set_cdclk(struct drm_i915_private *dev_priv,
POSTING_READ(CDCLK_CTL);
/* inform PCU of the change */
- mutex_lock(&dev_priv->pcu_lock);
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
cdclk_state->voltage_level);
- mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
}
@@ -1394,12 +1380,9 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
* requires us to wait up to 150usec, but that leads to timeouts;
* the 2ms used here is based on experiment.
*/
- mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_write_timeout(dev_priv,
HSW_PCODE_DE_WRITE_FREQ_REQ,
0x80000000, 150, 2);
- mutex_unlock(&dev_priv->pcu_lock);
-
if (ret) {
DRM_ERROR("PCode CDCLK freq change notify failed (err %d, freq %d)\n",
ret, cdclk);
@@ -1429,7 +1412,6 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
if (pipe != INVALID_PIPE)
intel_wait_for_vblank(dev_priv, pipe);
- mutex_lock(&dev_priv->pcu_lock);
/*
* The timeout isn't specified, the 2ms used here is based on
* experiment.
@@ -1439,8 +1421,6 @@ static void bxt_set_cdclk(struct drm_i915_private *dev_priv,
ret = sandybridge_pcode_write_timeout(dev_priv,
HSW_PCODE_DE_WRITE_FREQ_REQ,
cdclk_state->voltage_level, 150, 2);
- mutex_unlock(&dev_priv->pcu_lock);
-
if (ret) {
DRM_ERROR("PCode CDCLK freq set failed, (err %d, freq %d)\n",
ret, cdclk);
@@ -1663,12 +1643,10 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
u32 val, divider;
int ret;
- mutex_lock(&dev_priv->pcu_lock);
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
- mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
ret);
@@ -1707,10 +1685,8 @@ static void cnl_set_cdclk(struct drm_i915_private *dev_priv,
intel_wait_for_vblank(dev_priv, pipe);
/* inform PCU of the change */
- mutex_lock(&dev_priv->pcu_lock);
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
cdclk_state->voltage_level);
- mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
@@ -1849,12 +1825,10 @@ static void icl_set_cdclk(struct drm_i915_private *dev_priv,
unsigned int vco = cdclk_state->vco;
int ret;
- mutex_lock(&dev_priv->pcu_lock);
ret = skl_pcode_request(dev_priv, SKL_PCODE_CDCLK_CONTROL,
SKL_CDCLK_PREPARE_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE,
SKL_CDCLK_READY_FOR_CHANGE, 3);
- mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
DRM_ERROR("Failed to inform PCU about cdclk change (%d)\n",
ret);
@@ -1876,10 +1850,8 @@ static void icl_set_cdclk(struct drm_i915_private *dev_priv,
I915_WRITE(CDCLK_CTL, ICL_CDCLK_CD2X_PIPE_NONE |
skl_cdclk_decimal(cdclk));
- mutex_lock(&dev_priv->pcu_lock);
sandybridge_pcode_write(dev_priv, SKL_PCODE_CDCLK_CONTROL,
cdclk_state->voltage_level);
- mutex_unlock(&dev_priv->pcu_lock);
intel_update_cdclk(dev_priv);
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 68822f02dfc6..16c77d11f44b 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -5296,10 +5296,8 @@ void hsw_enable_ips(const struct intel_crtc_state *crtc_state)
WARN_ON(!(crtc_state->active_planes & ~BIT(PLANE_CURSOR)));
if (IS_BROADWELL(dev_priv)) {
- mutex_lock(&dev_priv->pcu_lock);
WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL,
IPS_ENABLE | IPS_PCODE_CONTROL));
- mutex_unlock(&dev_priv->pcu_lock);
/* Quoting Art Runyan: "its not safe to expect any particular
* value in IPS_CTL bit 31 after enabling IPS through the
* mailbox." Moreover, the mailbox may return a bogus state,
@@ -5329,9 +5327,7 @@ void hsw_disable_ips(const struct intel_crtc_state *crtc_state)
return;
if (IS_BROADWELL(dev_priv)) {
- mutex_lock(&dev_priv->pcu_lock);
WARN_ON(sandybridge_pcode_write(dev_priv, DISPLAY_IPS_CONTROL, 0));
- mutex_unlock(&dev_priv->pcu_lock);
/*
* Wait for PCODE to finish disabling IPS. The BSpec specified
* 42ms timeout value leads to occasional timeouts so use 100ms
@@ -9455,11 +9451,9 @@ static u32 hsw_read_dcomp(struct drm_i915_private *dev_priv)
static void hsw_write_dcomp(struct drm_i915_private *dev_priv, u32 val)
{
if (IS_HASWELL(dev_priv)) {
- mutex_lock(&dev_priv->pcu_lock);
if (sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_D_COMP,
val))
DRM_DEBUG_KMS("Failed to write to D_COMP\n");
- mutex_unlock(&dev_priv->pcu_lock);
} else {
I915_WRITE(D_COMP_BDW, val);
POSTING_READ(D_COMP_BDW);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 99b007169c49..2476e867981d 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -213,10 +213,8 @@ static int intel_hdcp_load_keys(struct drm_i915_private *dev_priv)
* from other platforms. So GEN9_BC uses the GT Driver Mailbox i/f.
*/
if (IS_GEN9_BC(dev_priv)) {
- mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_write(dev_priv,
SKL_PCODE_LOAD_HDCP_KEYS, 1);
- mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
DRM_ERROR("Failed to initiate HDCP key load (%d)\n",
ret);
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index df33555b8053..df2d8f916e5d 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -317,7 +317,6 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
{
u32 val;
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
@@ -334,14 +333,12 @@ static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
}
static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
{
u32 val;
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
@@ -352,7 +349,6 @@ static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, val);
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
}
#define FW_WM(value, plane) \
@@ -2821,11 +2817,9 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
/* read the first set of memory latencies[0:3] */
val = 0; /* data0 to be programmed to 0 for first set */
- mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_read(dev_priv,
GEN9_PCODE_READ_MEM_LATENCY,
&val);
- mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
DRM_ERROR("SKL Mailbox read error = %d\n", ret);
@@ -2842,11 +2836,9 @@ static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
/* read the second set of memory latencies[4:7] */
val = 1; /* data0 to be programmed to 1 for second set */
- mutex_lock(&dev_priv->pcu_lock);
ret = sandybridge_pcode_read(dev_priv,
GEN9_PCODE_READ_MEM_LATENCY,
&val);
- mutex_unlock(&dev_priv->pcu_lock);
if (ret) {
DRM_ERROR("SKL Mailbox read error = %d\n", ret);
return;
@@ -3681,13 +3673,10 @@ intel_enable_sagv(struct drm_i915_private *dev_priv)
return 0;
DRM_DEBUG_KMS("Enabling SAGV\n");
- mutex_lock(&dev_priv->pcu_lock);
-
ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_ENABLE);
/* We don't need to wait for SAGV when enabling */
- mutex_unlock(&dev_priv->pcu_lock);
/*
* Some skl systems, pre-release machines in particular,
@@ -3718,15 +3707,11 @@ intel_disable_sagv(struct drm_i915_private *dev_priv)
return 0;
DRM_DEBUG_KMS("Disabling SAGV\n");
- mutex_lock(&dev_priv->pcu_lock);
-
/* bspec says to keep retrying for at least 1 ms */
ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL,
GEN9_SAGV_DISABLE,
GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED,
1);
- mutex_unlock(&dev_priv->pcu_lock);
-
/*
* Some skl systems, pre-release machines in particular,
* don't actually have SAGV.
@@ -6143,7 +6128,6 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
wm->level = VLV_WM_LEVEL_PM2;
if (IS_CHERRYVIEW(dev_priv)) {
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
val = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
@@ -6175,7 +6159,6 @@ void vlv_wm_get_hw_state(struct drm_i915_private *dev_priv)
}
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
}
for_each_intel_crtc(&dev_priv->drm, crtc) {
@@ -6810,7 +6793,7 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&rps->lock);
if (rps->enabled) {
u8 freq;
@@ -6833,7 +6816,7 @@ void gen6_rps_busy(struct drm_i915_private *dev_priv)
rps->max_freq_softlimit)))
DRM_DEBUG_DRIVER("Failed to set idle frequency\n");
}
- mutex_unlock(&dev_priv->pcu_lock);
+ mutex_unlock(&rps->lock);
}
void gen6_rps_idle(struct drm_i915_private *dev_priv)
@@ -6847,7 +6830,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
*/
gen6_disable_rps_interrupts(dev_priv);
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&rps->lock);
if (rps->enabled) {
if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
vlv_set_rps_idle(dev_priv);
@@ -6857,7 +6840,7 @@ void gen6_rps_idle(struct drm_i915_private *dev_priv)
I915_WRITE(GEN6_PMINTRMSK,
gen6_sanitize_rps_pm_mask(dev_priv, ~0));
}
- mutex_unlock(&dev_priv->pcu_lock);
+ mutex_unlock(&rps->lock);
}
void gen6_rps_boost(struct i915_request *rq)
@@ -6897,7 +6880,7 @@ int intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
struct intel_rps *rps = &dev_priv->gt_pm.rps;
int err;
- lockdep_assert_held(&dev_priv->pcu_lock);
+ lockdep_assert_held(&rps->lock);
GEM_BUG_ON(val > rps->max_freq);
GEM_BUG_ON(val < rps->min_freq);
@@ -7470,7 +7453,7 @@ static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
unsigned int max_gpu_freq, min_gpu_freq;
struct cpufreq_policy *policy;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
+ lockdep_assert_held(&rps->lock);
if (rps->max_freq <= rps->min_freq)
return;
@@ -8555,7 +8538,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
pm_runtime_get(&dev_priv->drm.pdev->dev);
}
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&rps->lock);
/* Initialize RPS limits (for userspace) */
if (IS_CHERRYVIEW(dev_priv))
@@ -8588,7 +8571,7 @@ void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
rps->idle_freq = rps->min_freq;
rps->cur_freq = rps->idle_freq;
- mutex_unlock(&dev_priv->pcu_lock);
+ mutex_unlock(&rps->lock);
}
void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
@@ -8614,7 +8597,7 @@ void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
{
- lockdep_assert_held(&i915->pcu_lock);
+ lockdep_assert_held(&i915->gt_pm.rps.lock);
if (!i915->gt_pm.llc_pstate.enabled)
return;
@@ -8626,7 +8609,7 @@ static inline void intel_disable_llc_pstate(struct drm_i915_private *i915)
static void intel_disable_rc6(struct drm_i915_private *dev_priv)
{
- lockdep_assert_held(&dev_priv->pcu_lock);
+ lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
if (!dev_priv->gt_pm.rc6.enabled)
return;
@@ -8645,7 +8628,7 @@ static void intel_disable_rc6(struct drm_i915_private *dev_priv)
static void intel_disable_rps(struct drm_i915_private *dev_priv)
{
- lockdep_assert_held(&dev_priv->pcu_lock);
+ lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
if (!dev_priv->gt_pm.rps.enabled)
return;
@@ -8666,19 +8649,19 @@ static void intel_disable_rps(struct drm_i915_private *dev_priv)
void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
{
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&dev_priv->gt_pm.rps.lock);
intel_disable_rc6(dev_priv);
intel_disable_rps(dev_priv);
if (HAS_LLC(dev_priv))
intel_disable_llc_pstate(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
+ mutex_unlock(&dev_priv->gt_pm.rps.lock);
}
static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
{
- lockdep_assert_held(&i915->pcu_lock);
+ lockdep_assert_held(&i915->gt_pm.rps.lock);
if (i915->gt_pm.llc_pstate.enabled)
return;
@@ -8690,7 +8673,7 @@ static inline void intel_enable_llc_pstate(struct drm_i915_private *i915)
static void intel_enable_rc6(struct drm_i915_private *dev_priv)
{
- lockdep_assert_held(&dev_priv->pcu_lock);
+ lockdep_assert_held(&dev_priv->gt_pm.rps.lock);
if (dev_priv->gt_pm.rc6.enabled)
return;
@@ -8715,7 +8698,7 @@ static void intel_enable_rps(struct drm_i915_private *dev_priv)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
- lockdep_assert_held(&dev_priv->pcu_lock);
+ lockdep_assert_held(&rps->lock);
if (rps->enabled)
return;
@@ -8750,7 +8733,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
if (intel_vgpu_active(dev_priv))
return;
- mutex_lock(&dev_priv->pcu_lock);
+ mutex_lock(&dev_priv->gt_pm.rps.lock);
if (HAS_RC6(dev_priv))
intel_enable_rc6(dev_priv);
@@ -8759,7 +8742,7 @@ void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
if (HAS_LLC(dev_priv))
intel_enable_llc_pstate(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
+ mutex_unlock(&dev_priv->gt_pm.rps.lock);
}
static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
@@ -9775,22 +9758,20 @@ static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
}
}
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
+static int
+__sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
{
int status;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
+ lockdep_assert_held(&dev_priv->sb_lock);
/* GEN6_PCODE_* are outside of the forcewake domain, we can
* use te fw I915_READ variants to reduce the amount of work
* required when reading/writing.
*/
- if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
- DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n",
- mbox, __builtin_return_address(0));
+ if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
return -EAGAIN;
- }
I915_WRITE_FW(GEN6_PCODE_DATA, *val);
I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
@@ -9798,11 +9779,8 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
if (__intel_wait_for_register_fw(&dev_priv->uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
- 500, 0, NULL)) {
- DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n",
- mbox, __builtin_return_address(0));
+ 500, 0, NULL))
return -ETIMEDOUT;
- }
*val = I915_READ_FW(GEN6_PCODE_DATA);
I915_WRITE_FW(GEN6_PCODE_DATA, 0);
@@ -9812,33 +9790,40 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val
else
status = gen6_check_mailbox_status(dev_priv);
+ return status;
+}
+
+int
+sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
+{
+ int status;
+
+ mutex_lock(&dev_priv->sb_lock);
+ status = __sandybridge_pcode_read(dev_priv, mbox, val);
+ mutex_unlock(&dev_priv->sb_lock);
+
if (status) {
DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
mbox, __builtin_return_address(0), status);
- return status;
}
- return 0;
+ return status;
}
-int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
- u32 mbox, u32 val,
- int fast_timeout_us, int slow_timeout_ms)
+static int __sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
+ u32 mbox, u32 val,
+ int fast_timeout_us,
+ int slow_timeout_ms)
{
int status;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
-
/* GEN6_PCODE_* are outside of the forcewake domain, we can
* use te fw I915_READ variants to reduce the amount of work
* required when reading/writing.
*/
- if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
- DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n",
- val, mbox, __builtin_return_address(0));
+ if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
return -EAGAIN;
- }
I915_WRITE_FW(GEN6_PCODE_DATA, val);
I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
@@ -9847,11 +9832,8 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
if (__intel_wait_for_register_fw(&dev_priv->uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
fast_timeout_us, slow_timeout_ms,
- NULL)) {
- DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n",
- val, mbox, __builtin_return_address(0));
+ NULL))
return -ETIMEDOUT;
- }
I915_WRITE_FW(GEN6_PCODE_DATA, 0);
@@ -9860,13 +9842,28 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
else
status = gen6_check_mailbox_status(dev_priv);
+ return status;
+}
+
+int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
+ u32 mbox, u32 val,
+ int fast_timeout_us,
+ int slow_timeout_ms)
+{
+ int status;
+
+ mutex_lock(&dev_priv->sb_lock);
+ status = __sandybridge_pcode_write_timeout(dev_priv, mbox, val,
+ fast_timeout_us,
+ slow_timeout_ms);
+ mutex_unlock(&dev_priv->sb_lock);
+
if (status) {
DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
val, mbox, __builtin_return_address(0), status);
- return status;
}
- return 0;
+ return status;
}
static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
@@ -9875,7 +9872,7 @@ static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
{
u32 val = request;
- *status = sandybridge_pcode_read(dev_priv, mbox, &val);
+ *status = __sandybridge_pcode_read(dev_priv, mbox, &val);
return *status || ((val & reply_mask) == reply);
}
@@ -9905,7 +9902,7 @@ int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
u32 status;
int ret;
- WARN_ON(!mutex_is_locked(&dev_priv->pcu_lock));
+ mutex_lock(&dev_priv->sb_lock);
#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
&status)
@@ -9941,6 +9938,7 @@ int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
preempt_enable();
out:
+ mutex_unlock(&dev_priv->sb_lock);
return ret ? ret : status;
#undef COND
}
@@ -10010,7 +10008,7 @@ int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
void intel_pm_setup(struct drm_i915_private *dev_priv)
{
- mutex_init(&dev_priv->pcu_lock);
+ mutex_init(&dev_priv->gt_pm.rps.lock);
mutex_init(&dev_priv->gt_pm.rps.power.mutex);
atomic_set(&dev_priv->gt_pm.rps.num_waiters, 0);
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index ac8bc5baef40..a80ff35f6c81 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -1211,7 +1211,6 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
PUNIT_PWRGT_PWR_GATE(pw_idx);
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
#define COND \
@@ -1234,7 +1233,6 @@ static void vlv_set_power_well(struct drm_i915_private *dev_priv,
out:
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
}
static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
@@ -1261,7 +1259,6 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
mask = PUNIT_PWRGT_MASK(pw_idx);
ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
@@ -1282,7 +1279,6 @@ static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
WARN_ON(ctrl != state);
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
return enabled;
}
@@ -1768,7 +1764,6 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
bool enabled;
u32 state, ctrl;
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
@@ -1787,7 +1782,6 @@ static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
WARN_ON(ctrl << 16 != state);
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
return enabled;
}
@@ -1802,7 +1796,6 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
#define COND \
@@ -1825,7 +1818,6 @@ static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
out:
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
}
static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
@@ -4019,11 +4011,9 @@ static bool vlv_punit_is_power_gated(struct drm_i915_private *dev_priv, u32 reg0
{
bool ret;
- mutex_lock(&dev_priv->pcu_lock);
vlv_punit_get(dev_priv);
ret = (vlv_punit_read(dev_priv, reg0) & SSPM0_SSC_MASK) == SSPM0_SSC_PWR_GATE;
vlv_punit_put(dev_priv);
- mutex_unlock(&dev_priv->pcu_lock);
return ret;
}
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 7c33925f52f9..457b8cad5494 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -143,8 +143,6 @@ u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
{
u32 val = 0;
- lockdep_assert_held(&i915->pcu_lock);
-
vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRRDDA_NP, addr, &val);
@@ -153,8 +151,6 @@ u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr)
int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val)
{
- lockdep_assert_held(&i915->pcu_lock);
-
return vlv_sideband_rw(i915, PCI_DEVFN(0, 0), IOSF_PORT_PUNIT,
SB_CRWRDA_NP, addr, &val);
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 07/10] drm/i915: Separate sideband declarations to intel_sideband.h
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (5 preceding siblings ...)
2019-04-19 17:13 ` [PATCH 06/10] drm/i915: Replace pcu_lock with sb_lock Chris Wilson
@ 2019-04-19 17:13 ` Chris Wilson
2019-04-23 17:17 ` Ville Syrjälä
2019-04-19 17:14 ` [PATCH 08/10] drm/i915: Merge sbi read/write into a single accessor Chris Wilson
` (6 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:13 UTC (permalink / raw)
To: intel-gfx
Split the sideback declarations out of the ginormous i915_drv.h
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
| 1 +
drivers/gpu/drm/i915/i915_debugfs.c | 1 +
drivers/gpu/drm/i915/i915_drv.h | 120 --------------------
drivers/gpu/drm/i915/i915_sysfs.c | 2 +
drivers/gpu/drm/i915/intel_cdclk.c | 1 +
drivers/gpu/drm/i915/intel_display.c | 1 +
drivers/gpu/drm/i915/intel_dp.c | 2 +
drivers/gpu/drm/i915/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/intel_dsi_vbt.c | 13 ++-
drivers/gpu/drm/i915/intel_hdmi.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 1 +
drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
drivers/gpu/drm/i915/intel_sideband.c | 2 +
drivers/gpu/drm/i915/intel_sideband.h | 130 ++++++++++++++++++++++
drivers/gpu/drm/i915/vlv_dsi.c | 2 +-
drivers/gpu/drm/i915/vlv_dsi_pll.c | 4 +-
16 files changed, 157 insertions(+), 126 deletions(-)
create mode 100644 drivers/gpu/drm/i915/intel_sideband.h
--git a/drivers/gpu/drm/i915/Makefile.header-test b/drivers/gpu/drm/i915/Makefile.header-test
index c1c391816fa7..20ee9321dbb3 100644
--- a/drivers/gpu/drm/i915/Makefile.header-test
+++ b/drivers/gpu/drm/i915/Makefile.header-test
@@ -31,6 +31,7 @@ header_test := \
intel_pipe_crc.h \
intel_pm.h \
intel_psr.h \
+ intel_sideband.h \
intel_sdvo.h \
intel_sprite.h \
intel_tv.h \
diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
index 93fd82a6ac2b..850ad072d1e0 100644
--- a/drivers/gpu/drm/i915/i915_debugfs.c
+++ b/drivers/gpu/drm/i915/i915_debugfs.c
@@ -41,6 +41,7 @@
#include "intel_hdmi.h"
#include "intel_pm.h"
#include "intel_psr.h"
+#include "intel_sideband.h"
static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
{
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index 6eb12f11ab65..f4879fb41aa6 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -541,11 +541,6 @@ enum intel_pch {
PCH_ICP, /* Ice Lake PCH */
};
-enum intel_sbi_destination {
- SBI_ICLK,
- SBI_MPHY,
-};
-
#define QUIRK_LVDS_SSC_DISABLE (1<<1)
#define QUIRK_INVERT_BRIGHTNESS (1<<2)
#define QUIRK_BACKLIGHT_PRESENT (1<<3)
@@ -3442,121 +3437,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
u32 reply_mask, u32 reply, int timeout_base_ms);
-/* intel_sideband.c */
-
-enum {
- VLV_IOSF_SB_BUNIT,
- VLV_IOSF_SB_CCK,
- VLV_IOSF_SB_CCU,
- VLV_IOSF_SB_DPIO,
- VLV_IOSF_SB_FLISDSI,
- VLV_IOSF_SB_GPIO,
- VLV_IOSF_SB_NC,
- VLV_IOSF_SB_PUNIT,
-};
-
-void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
-u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
-void vlv_iosf_sb_write(struct drm_i915_private *i915,
- u8 port, u32 reg, u32 val);
-void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
-
-static inline void vlv_bunit_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
-}
-
-u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
-void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_bunit_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
-}
-
-static inline void vlv_cck_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
-}
-
-u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
-void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_cck_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
-}
-
-static inline void vlv_ccu_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
-}
-
-u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
-void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_ccu_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
-}
-
-static inline void vlv_dpio_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
-}
-
-u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
-void vlv_dpio_write(struct drm_i915_private *i915,
- enum pipe pipe, int reg, u32 val);
-
-static inline void vlv_dpio_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
-}
-
-static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
-}
-
-u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
-void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
-
-static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
-}
-
-static inline void vlv_nc_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
-}
-
-u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
-
-static inline void vlv_nc_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
-}
-
-static inline void vlv_punit_get(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
-}
-
-u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
-int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
-
-static inline void vlv_punit_put(struct drm_i915_private *i915)
-{
- vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
-}
-
-u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
- enum intel_sbi_destination destination);
-void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
- enum intel_sbi_destination destination);
-
/* intel_dpio_phy.c */
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
index 0952d6a70e1f..9bb3a15e4683 100644
--- a/drivers/gpu/drm/i915/i915_sysfs.c
+++ b/drivers/gpu/drm/i915/i915_sysfs.c
@@ -29,7 +29,9 @@
#include <linux/module.h>
#include <linux/stat.h>
#include <linux/sysfs.h>
+
#include "intel_drv.h"
+#include "intel_sideband.h"
#include "i915_drv.h"
static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
index 2bc5d3227a24..cf9c916e8d49 100644
--- a/drivers/gpu/drm/i915/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/intel_cdclk.c
@@ -23,6 +23,7 @@
#include "intel_cdclk.h"
#include "intel_drv.h"
+#include "intel_sideband.h"
/**
* DOC: CDCLK / RAWCLK
diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 16c77d11f44b..035506417bdd 100644
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -67,6 +67,7 @@
#include "intel_pm.h"
#include "intel_psr.h"
#include "intel_sdvo.h"
+#include "intel_sideband.h"
#include "intel_sprite.h"
#include "intel_tv.h"
diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
index 4fc25dcc97d4..08d92570f17f 100644
--- a/drivers/gpu/drm/i915/intel_dp.c
+++ b/drivers/gpu/drm/i915/intel_dp.c
@@ -31,6 +31,7 @@
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/types.h>
+
#include <asm/byteorder.h>
#include <drm/drm_atomic_helper.h>
@@ -53,6 +54,7 @@
#include "intel_lvds.h"
#include "intel_panel.h"
#include "intel_psr.h"
+#include "intel_sideband.h"
#define DP_DPRX_ESI_LEN 14
diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
index c784f3daaf51..d80887b5e234 100644
--- a/drivers/gpu/drm/i915/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
@@ -23,6 +23,7 @@
#include "intel_dp.h"
#include "intel_drv.h"
+#include "intel_sideband.h"
/**
* DOC: DPIO
diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
index 2304488f2d35..fbed9064ac7e 100644
--- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
+++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
@@ -24,18 +24,23 @@
*
*/
-#include <drm/drm_crtc.h>
-#include <drm/drm_edid.h>
-#include <drm/i915_drm.h>
#include <linux/gpio/consumer.h>
#include <linux/mfd/intel_soc_pmic.h>
#include <linux/slab.h>
-#include <video/mipi_display.h>
+
#include <asm/intel-mid.h>
#include <asm/unaligned.h>
+
+#include <drm/drm_crtc.h>
+#include <drm/drm_edid.h>
+#include <drm/i915_drm.h>
+
+#include <video/mipi_display.h>
+
#include "i915_drv.h"
#include "intel_drv.h"
#include "intel_dsi.h"
+#include "intel_sideband.h"
#define MIPI_TRANSFER_MODE_SHIFT 0
#define MIPI_VIRTUAL_CHANNEL_SHIFT 1
diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
index 8b72365f9309..d2b3b32ea159 100644
--- a/drivers/gpu/drm/i915/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/intel_hdmi.c
@@ -50,6 +50,7 @@
#include "intel_lspcon.h"
#include "intel_sdvo.h"
#include "intel_panel.h"
+#include "intel_sideband.h"
static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
{
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index df2d8f916e5d..9a810d0683f7 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -38,6 +38,7 @@
#include "intel_fbc.h"
#include "intel_pm.h"
#include "intel_sprite.h"
+#include "intel_sideband.h"
#include "../../../platform/x86/intel_ips.h"
/**
diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
index a80ff35f6c81..166f162a7d51 100644
--- a/drivers/gpu/drm/i915/intel_runtime_pm.c
+++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
@@ -37,6 +37,7 @@
#include "intel_csr.h"
#include "intel_dp.h"
#include "intel_drv.h"
+#include "intel_sideband.h"
/**
* DOC: runtime pm
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 457b8cad5494..5c3ae5185a01 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -24,6 +24,8 @@
#include <asm/iosf_mbi.h>
+#include "intel_sideband.h"
+
#include "i915_drv.h"
#include "intel_drv.h"
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
new file mode 100644
index 000000000000..9d36bdc17955
--- /dev/null
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: MIT */
+
+#ifndef _INTEL_SIDEBAND_H_
+#define _INTEL_SIDEBAND_H_
+
+#include <linux/bitops.h>
+#include <linux/types.h>
+
+struct drm_i915_private;
+enum pipe;
+
+enum intel_sbi_destination {
+ SBI_ICLK,
+ SBI_MPHY,
+};
+
+enum {
+ VLV_IOSF_SB_BUNIT,
+ VLV_IOSF_SB_CCK,
+ VLV_IOSF_SB_CCU,
+ VLV_IOSF_SB_DPIO,
+ VLV_IOSF_SB_FLISDSI,
+ VLV_IOSF_SB_GPIO,
+ VLV_IOSF_SB_NC,
+ VLV_IOSF_SB_PUNIT,
+};
+
+void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
+u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
+void vlv_iosf_sb_write(struct drm_i915_private *i915,
+ u8 port, u32 reg, u32 val);
+void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
+
+static inline void vlv_bunit_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
+}
+
+u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
+void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_bunit_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
+}
+
+static inline void vlv_cck_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
+}
+
+u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
+void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_cck_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
+}
+
+static inline void vlv_ccu_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
+}
+
+u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
+void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_ccu_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
+}
+
+static inline void vlv_dpio_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
+}
+
+u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
+void vlv_dpio_write(struct drm_i915_private *i915,
+ enum pipe pipe, int reg, u32 val);
+
+static inline void vlv_dpio_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
+}
+
+static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
+}
+
+u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
+void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
+
+static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
+}
+
+static inline void vlv_nc_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
+}
+
+u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
+
+static inline void vlv_nc_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
+}
+
+static inline void vlv_punit_get(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
+}
+
+u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
+int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
+
+static inline void vlv_punit_put(struct drm_i915_private *i915)
+{
+ vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
+}
+
+u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
+ enum intel_sbi_destination destination);
+void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
+ enum intel_sbi_destination destination);
+
+#endif /* _INTEL_SIDEBAND_H */
diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
index dc1839bfde3e..b4c658334d04 100644
--- a/drivers/gpu/drm/i915/vlv_dsi.c
+++ b/drivers/gpu/drm/i915/vlv_dsi.c
@@ -30,13 +30,13 @@
#include <drm/drm_crtc.h>
#include <drm/drm_edid.h>
#include <drm/drm_mipi_dsi.h>
-#include <drm/i915_drm.h>
#include "i915_drv.h"
#include "intel_connector.h"
#include "intel_drv.h"
#include "intel_dsi.h"
#include "intel_panel.h"
+#include "intel_sideband.h"
/* return pixels in terms of txbyteclkhs */
static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
diff --git a/drivers/gpu/drm/i915/vlv_dsi_pll.c b/drivers/gpu/drm/i915/vlv_dsi_pll.c
index 25b811174f5c..99cc3e2e9c2c 100644
--- a/drivers/gpu/drm/i915/vlv_dsi_pll.c
+++ b/drivers/gpu/drm/i915/vlv_dsi_pll.c
@@ -26,9 +26,11 @@
*/
#include <linux/kernel.h>
-#include "intel_drv.h"
+
#include "i915_drv.h"
+#include "intel_drv.h"
#include "intel_dsi.h"
+#include "intel_sideband.h"
static const u16 lfsr_converts[] = {
426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 07/10] drm/i915: Separate sideband declarations to intel_sideband.h
2019-04-19 17:13 ` [PATCH 07/10] drm/i915: Separate sideband declarations to intel_sideband.h Chris Wilson
@ 2019-04-23 17:17 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2019-04-23 17:17 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Apr 19, 2019 at 06:13:59PM +0100, Chris Wilson wrote:
> Split the sideback declarations out of the ginormous i915_drv.h
Ah, it was here all along :)
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/Makefile.header-test | 1 +
> drivers/gpu/drm/i915/i915_debugfs.c | 1 +
> drivers/gpu/drm/i915/i915_drv.h | 120 --------------------
> drivers/gpu/drm/i915/i915_sysfs.c | 2 +
> drivers/gpu/drm/i915/intel_cdclk.c | 1 +
> drivers/gpu/drm/i915/intel_display.c | 1 +
> drivers/gpu/drm/i915/intel_dp.c | 2 +
> drivers/gpu/drm/i915/intel_dpio_phy.c | 1 +
> drivers/gpu/drm/i915/intel_dsi_vbt.c | 13 ++-
> drivers/gpu/drm/i915/intel_hdmi.c | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 1 +
> drivers/gpu/drm/i915/intel_runtime_pm.c | 1 +
> drivers/gpu/drm/i915/intel_sideband.c | 2 +
> drivers/gpu/drm/i915/intel_sideband.h | 130 ++++++++++++++++++++++
> drivers/gpu/drm/i915/vlv_dsi.c | 2 +-
> drivers/gpu/drm/i915/vlv_dsi_pll.c | 4 +-
> 16 files changed, 157 insertions(+), 126 deletions(-)
> create mode 100644 drivers/gpu/drm/i915/intel_sideband.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile.header-test b/drivers/gpu/drm/i915/Makefile.header-test
> index c1c391816fa7..20ee9321dbb3 100644
> --- a/drivers/gpu/drm/i915/Makefile.header-test
> +++ b/drivers/gpu/drm/i915/Makefile.header-test
> @@ -31,6 +31,7 @@ header_test := \
> intel_pipe_crc.h \
> intel_pm.h \
> intel_psr.h \
> + intel_sideband.h \
> intel_sdvo.h \
> intel_sprite.h \
> intel_tv.h \
> diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c
> index 93fd82a6ac2b..850ad072d1e0 100644
> --- a/drivers/gpu/drm/i915/i915_debugfs.c
> +++ b/drivers/gpu/drm/i915/i915_debugfs.c
> @@ -41,6 +41,7 @@
> #include "intel_hdmi.h"
> #include "intel_pm.h"
> #include "intel_psr.h"
> +#include "intel_sideband.h"
>
> static inline struct drm_i915_private *node_to_i915(struct drm_info_node *node)
> {
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index 6eb12f11ab65..f4879fb41aa6 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -541,11 +541,6 @@ enum intel_pch {
> PCH_ICP, /* Ice Lake PCH */
> };
>
> -enum intel_sbi_destination {
> - SBI_ICLK,
> - SBI_MPHY,
> -};
> -
> #define QUIRK_LVDS_SSC_DISABLE (1<<1)
> #define QUIRK_INVERT_BRIGHTNESS (1<<2)
> #define QUIRK_BACKLIGHT_PRESENT (1<<3)
> @@ -3442,121 +3437,6 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
> int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
> u32 reply_mask, u32 reply, int timeout_base_ms);
>
> -/* intel_sideband.c */
> -
> -enum {
> - VLV_IOSF_SB_BUNIT,
> - VLV_IOSF_SB_CCK,
> - VLV_IOSF_SB_CCU,
> - VLV_IOSF_SB_DPIO,
> - VLV_IOSF_SB_FLISDSI,
> - VLV_IOSF_SB_GPIO,
> - VLV_IOSF_SB_NC,
> - VLV_IOSF_SB_PUNIT,
> -};
> -
> -void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
> -u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
> -void vlv_iosf_sb_write(struct drm_i915_private *i915,
> - u8 port, u32 reg, u32 val);
> -void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
> -
> -static inline void vlv_bunit_get(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
> -}
> -
> -u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
> -void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
> -
> -static inline void vlv_bunit_put(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
> -}
> -
> -static inline void vlv_cck_get(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
> -}
> -
> -u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
> -void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
> -
> -static inline void vlv_cck_put(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
> -}
> -
> -static inline void vlv_ccu_get(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
> -}
> -
> -u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
> -void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
> -
> -static inline void vlv_ccu_put(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
> -}
> -
> -static inline void vlv_dpio_get(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
> -}
> -
> -u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
> -void vlv_dpio_write(struct drm_i915_private *i915,
> - enum pipe pipe, int reg, u32 val);
> -
> -static inline void vlv_dpio_put(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
> -}
> -
> -static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
> -}
> -
> -u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
> -void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
> -
> -static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
> -}
> -
> -static inline void vlv_nc_get(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
> -}
> -
> -u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
> -
> -static inline void vlv_nc_put(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
> -}
> -
> -static inline void vlv_punit_get(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
> -}
> -
> -u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
> -int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
> -
> -static inline void vlv_punit_put(struct drm_i915_private *i915)
> -{
> - vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
> -}
> -
> -u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> - enum intel_sbi_destination destination);
> -void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> - enum intel_sbi_destination destination);
> -
> /* intel_dpio_phy.c */
> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> enum dpio_phy *phy, enum dpio_channel *ch);
> diff --git a/drivers/gpu/drm/i915/i915_sysfs.c b/drivers/gpu/drm/i915/i915_sysfs.c
> index 0952d6a70e1f..9bb3a15e4683 100644
> --- a/drivers/gpu/drm/i915/i915_sysfs.c
> +++ b/drivers/gpu/drm/i915/i915_sysfs.c
> @@ -29,7 +29,9 @@
> #include <linux/module.h>
> #include <linux/stat.h>
> #include <linux/sysfs.h>
> +
> #include "intel_drv.h"
> +#include "intel_sideband.h"
> #include "i915_drv.h"
>
> static inline struct drm_i915_private *kdev_minor_to_i915(struct device *kdev)
> diff --git a/drivers/gpu/drm/i915/intel_cdclk.c b/drivers/gpu/drm/i915/intel_cdclk.c
> index 2bc5d3227a24..cf9c916e8d49 100644
> --- a/drivers/gpu/drm/i915/intel_cdclk.c
> +++ b/drivers/gpu/drm/i915/intel_cdclk.c
> @@ -23,6 +23,7 @@
>
> #include "intel_cdclk.h"
> #include "intel_drv.h"
> +#include "intel_sideband.h"
>
> /**
> * DOC: CDCLK / RAWCLK
> diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
> index 16c77d11f44b..035506417bdd 100644
> --- a/drivers/gpu/drm/i915/intel_display.c
> +++ b/drivers/gpu/drm/i915/intel_display.c
> @@ -67,6 +67,7 @@
> #include "intel_pm.h"
> #include "intel_psr.h"
> #include "intel_sdvo.h"
> +#include "intel_sideband.h"
> #include "intel_sprite.h"
> #include "intel_tv.h"
>
> diff --git a/drivers/gpu/drm/i915/intel_dp.c b/drivers/gpu/drm/i915/intel_dp.c
> index 4fc25dcc97d4..08d92570f17f 100644
> --- a/drivers/gpu/drm/i915/intel_dp.c
> +++ b/drivers/gpu/drm/i915/intel_dp.c
> @@ -31,6 +31,7 @@
> #include <linux/reboot.h>
> #include <linux/slab.h>
> #include <linux/types.h>
> +
> #include <asm/byteorder.h>
>
> #include <drm/drm_atomic_helper.h>
> @@ -53,6 +54,7 @@
> #include "intel_lvds.h"
> #include "intel_panel.h"
> #include "intel_psr.h"
> +#include "intel_sideband.h"
>
> #define DP_DPRX_ESI_LEN 14
>
> diff --git a/drivers/gpu/drm/i915/intel_dpio_phy.c b/drivers/gpu/drm/i915/intel_dpio_phy.c
> index c784f3daaf51..d80887b5e234 100644
> --- a/drivers/gpu/drm/i915/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/intel_dpio_phy.c
> @@ -23,6 +23,7 @@
>
> #include "intel_dp.h"
> #include "intel_drv.h"
> +#include "intel_sideband.h"
>
> /**
> * DOC: DPIO
> diff --git a/drivers/gpu/drm/i915/intel_dsi_vbt.c b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> index 2304488f2d35..fbed9064ac7e 100644
> --- a/drivers/gpu/drm/i915/intel_dsi_vbt.c
> +++ b/drivers/gpu/drm/i915/intel_dsi_vbt.c
> @@ -24,18 +24,23 @@
> *
> */
>
> -#include <drm/drm_crtc.h>
> -#include <drm/drm_edid.h>
> -#include <drm/i915_drm.h>
> #include <linux/gpio/consumer.h>
> #include <linux/mfd/intel_soc_pmic.h>
> #include <linux/slab.h>
> -#include <video/mipi_display.h>
> +
> #include <asm/intel-mid.h>
> #include <asm/unaligned.h>
> +
> +#include <drm/drm_crtc.h>
> +#include <drm/drm_edid.h>
> +#include <drm/i915_drm.h>
> +
> +#include <video/mipi_display.h>
> +
> #include "i915_drv.h"
> #include "intel_drv.h"
> #include "intel_dsi.h"
> +#include "intel_sideband.h"
>
> #define MIPI_TRANSFER_MODE_SHIFT 0
> #define MIPI_VIRTUAL_CHANNEL_SHIFT 1
> diff --git a/drivers/gpu/drm/i915/intel_hdmi.c b/drivers/gpu/drm/i915/intel_hdmi.c
> index 8b72365f9309..d2b3b32ea159 100644
> --- a/drivers/gpu/drm/i915/intel_hdmi.c
> +++ b/drivers/gpu/drm/i915/intel_hdmi.c
> @@ -50,6 +50,7 @@
> #include "intel_lspcon.h"
> #include "intel_sdvo.h"
> #include "intel_panel.h"
> +#include "intel_sideband.h"
>
> static struct drm_device *intel_hdmi_to_dev(struct intel_hdmi *intel_hdmi)
> {
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index df2d8f916e5d..9a810d0683f7 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -38,6 +38,7 @@
> #include "intel_fbc.h"
> #include "intel_pm.h"
> #include "intel_sprite.h"
> +#include "intel_sideband.h"
> #include "../../../platform/x86/intel_ips.h"
>
> /**
> diff --git a/drivers/gpu/drm/i915/intel_runtime_pm.c b/drivers/gpu/drm/i915/intel_runtime_pm.c
> index a80ff35f6c81..166f162a7d51 100644
> --- a/drivers/gpu/drm/i915/intel_runtime_pm.c
> +++ b/drivers/gpu/drm/i915/intel_runtime_pm.c
> @@ -37,6 +37,7 @@
> #include "intel_csr.h"
> #include "intel_dp.h"
> #include "intel_drv.h"
> +#include "intel_sideband.h"
>
> /**
> * DOC: runtime pm
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 457b8cad5494..5c3ae5185a01 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -24,6 +24,8 @@
>
> #include <asm/iosf_mbi.h>
>
> +#include "intel_sideband.h"
> +
> #include "i915_drv.h"
> #include "intel_drv.h"
>
> diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
> new file mode 100644
> index 000000000000..9d36bdc17955
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/intel_sideband.h
> @@ -0,0 +1,130 @@
> +/* SPDX-License-Identifier: MIT */
> +
> +#ifndef _INTEL_SIDEBAND_H_
> +#define _INTEL_SIDEBAND_H_
> +
> +#include <linux/bitops.h>
> +#include <linux/types.h>
> +
> +struct drm_i915_private;
> +enum pipe;
> +
> +enum intel_sbi_destination {
> + SBI_ICLK,
> + SBI_MPHY,
> +};
> +
> +enum {
> + VLV_IOSF_SB_BUNIT,
> + VLV_IOSF_SB_CCK,
> + VLV_IOSF_SB_CCU,
> + VLV_IOSF_SB_DPIO,
> + VLV_IOSF_SB_FLISDSI,
> + VLV_IOSF_SB_GPIO,
> + VLV_IOSF_SB_NC,
> + VLV_IOSF_SB_PUNIT,
> +};
> +
> +void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports);
> +u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg);
> +void vlv_iosf_sb_write(struct drm_i915_private *i915,
> + u8 port, u32 reg, u32 val);
> +void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports);
> +
> +static inline void vlv_bunit_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT));
> +}
> +
> +u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg);
> +void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val);
> +
> +static inline void vlv_bunit_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT));
> +}
> +
> +static inline void vlv_cck_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK));
> +}
> +
> +u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg);
> +void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val);
> +
> +static inline void vlv_cck_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK));
> +}
> +
> +static inline void vlv_ccu_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU));
> +}
> +
> +u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg);
> +void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val);
> +
> +static inline void vlv_ccu_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU));
> +}
> +
> +static inline void vlv_dpio_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO));
> +}
> +
> +u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg);
> +void vlv_dpio_write(struct drm_i915_private *i915,
> + enum pipe pipe, int reg, u32 val);
> +
> +static inline void vlv_dpio_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO));
> +}
> +
> +static inline void vlv_flisdsi_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI));
> +}
> +
> +u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg);
> +void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val);
> +
> +static inline void vlv_flisdsi_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI));
> +}
> +
> +static inline void vlv_nc_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC));
> +}
> +
> +u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr);
> +
> +static inline void vlv_nc_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC));
> +}
> +
> +static inline void vlv_punit_get(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT));
> +}
> +
> +u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr);
> +int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val);
> +
> +static inline void vlv_punit_put(struct drm_i915_private *i915)
> +{
> + vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT));
> +}
> +
> +u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
> + enum intel_sbi_destination destination);
> +void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
> + enum intel_sbi_destination destination);
> +
> +#endif /* _INTEL_SIDEBAND_H */
> diff --git a/drivers/gpu/drm/i915/vlv_dsi.c b/drivers/gpu/drm/i915/vlv_dsi.c
> index dc1839bfde3e..b4c658334d04 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi.c
> @@ -30,13 +30,13 @@
> #include <drm/drm_crtc.h>
> #include <drm/drm_edid.h>
> #include <drm/drm_mipi_dsi.h>
> -#include <drm/i915_drm.h>
>
> #include "i915_drv.h"
> #include "intel_connector.h"
> #include "intel_drv.h"
> #include "intel_dsi.h"
> #include "intel_panel.h"
> +#include "intel_sideband.h"
>
> /* return pixels in terms of txbyteclkhs */
> static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count,
> diff --git a/drivers/gpu/drm/i915/vlv_dsi_pll.c b/drivers/gpu/drm/i915/vlv_dsi_pll.c
> index 25b811174f5c..99cc3e2e9c2c 100644
> --- a/drivers/gpu/drm/i915/vlv_dsi_pll.c
> +++ b/drivers/gpu/drm/i915/vlv_dsi_pll.c
> @@ -26,9 +26,11 @@
> */
>
> #include <linux/kernel.h>
> -#include "intel_drv.h"
> +
> #include "i915_drv.h"
> +#include "intel_drv.h"
> #include "intel_dsi.h"
> +#include "intel_sideband.h"
>
> static const u16 lfsr_converts[] = {
> 426, 469, 234, 373, 442, 221, 110, 311, 411, /* 62 - 70 */
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 08/10] drm/i915: Merge sbi read/write into a single accessor
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (6 preceding siblings ...)
2019-04-19 17:13 ` [PATCH 07/10] drm/i915: Separate sideband declarations to intel_sideband.h Chris Wilson
@ 2019-04-19 17:14 ` Chris Wilson
2019-04-23 17:21 ` Ville Syrjälä
2019-04-19 17:14 ` [PATCH 09/10] drm/i915: Merge sandybridge_pcode_(read|write) Chris Wilson
` (5 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:14 UTC (permalink / raw)
To: intel-gfx
Since intel_sideband_read and intel_sideband_write differ by only a
couple of lines (depending on whether we feed the value in or out),
merge the two into a single common accessor.
v2: Restore vlv_flisdsi_read() lost during rebasing.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/intel_sideband.c | 94 +++++++++++----------------
1 file changed, 38 insertions(+), 56 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 5c3ae5185a01..7113fb8850d6 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -273,81 +273,63 @@ void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
}
/* SBI access */
-u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
- enum intel_sbi_destination destination)
+static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
+ enum intel_sbi_destination destination,
+ u32 *val, bool is_read)
{
- u32 value = 0;
+ struct intel_uncore *uncore = &i915->uncore;
+ u32 cmd;
- lockdep_assert_held(&dev_priv->sb_lock);
+ lockdep_assert_held(&i915->sb_lock);
- if (intel_wait_for_register(&dev_priv->uncore,
- SBI_CTL_STAT, SBI_BUSY, 0,
- 100)) {
+ if (intel_wait_for_register_fw(uncore,
+ SBI_CTL_STAT, SBI_BUSY, 0,
+ 100)) {
DRM_ERROR("timeout waiting for SBI to become ready\n");
- return 0;
+ return -EBUSY;
}
- I915_WRITE(SBI_ADDR, (reg << 16));
- I915_WRITE(SBI_DATA, 0);
+ intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
+ intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
if (destination == SBI_ICLK)
- value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
+ cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
else
- value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
- I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
-
- if (intel_wait_for_register(&dev_priv->uncore,
- SBI_CTL_STAT,
- SBI_BUSY,
- 0,
- 100)) {
+ cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
+ if (!is_read)
+ cmd |= BIT(8);
+ intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
+
+ if (__intel_wait_for_register_fw(uncore,
+ SBI_CTL_STAT, SBI_BUSY, 0,
+ 100, 100, &cmd)) {
DRM_ERROR("timeout waiting for SBI to complete read\n");
- return 0;
+ return -ETIMEDOUT;
}
- if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
+ if (cmd & SBI_RESPONSE_FAIL) {
DRM_ERROR("error during SBI read of reg %x\n", reg);
- return 0;
+ return -ENXIO;
}
- return I915_READ(SBI_DATA);
+ if (is_read)
+ *val = intel_uncore_read_fw(uncore, SBI_DATA);
+
+ return 0;
}
-void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
- enum intel_sbi_destination destination)
+u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
+ enum intel_sbi_destination destination)
{
- u32 tmp;
+ u32 result = 0;
- lockdep_assert_held(&dev_priv->sb_lock);
+ intel_sbi_rw(i915, reg, destination, &result, true);
- if (intel_wait_for_register(&dev_priv->uncore,
- SBI_CTL_STAT, SBI_BUSY, 0,
- 100)) {
- DRM_ERROR("timeout waiting for SBI to become ready\n");
- return;
- }
-
- I915_WRITE(SBI_ADDR, (reg << 16));
- I915_WRITE(SBI_DATA, value);
-
- if (destination == SBI_ICLK)
- tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
- else
- tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
- I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
-
- if (intel_wait_for_register(&dev_priv->uncore,
- SBI_CTL_STAT,
- SBI_BUSY,
- 0,
- 100)) {
- DRM_ERROR("timeout waiting for SBI to complete write\n");
- return;
- }
+ return result;
+}
- if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
- DRM_ERROR("error during SBI write of %x to reg %x\n",
- value, reg);
- return;
- }
+void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
+ enum intel_sbi_destination destination)
+{
+ intel_sbi_rw(i915, reg, destination, &value, false);
}
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 08/10] drm/i915: Merge sbi read/write into a single accessor
2019-04-19 17:14 ` [PATCH 08/10] drm/i915: Merge sbi read/write into a single accessor Chris Wilson
@ 2019-04-23 17:21 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2019-04-23 17:21 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Apr 19, 2019 at 06:14:00PM +0100, Chris Wilson wrote:
> Since intel_sideband_read and intel_sideband_write differ by only a
> couple of lines (depending on whether we feed the value in or out),
> merge the two into a single common accessor.
>
> v2: Restore vlv_flisdsi_read() lost during rebasing.
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Looks equivalent
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/intel_sideband.c | 94 +++++++++++----------------
> 1 file changed, 38 insertions(+), 56 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 5c3ae5185a01..7113fb8850d6 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -273,81 +273,63 @@ void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val)
> }
>
> /* SBI access */
> -u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
> - enum intel_sbi_destination destination)
> +static int intel_sbi_rw(struct drm_i915_private *i915, u16 reg,
> + enum intel_sbi_destination destination,
> + u32 *val, bool is_read)
> {
> - u32 value = 0;
> + struct intel_uncore *uncore = &i915->uncore;
> + u32 cmd;
>
> - lockdep_assert_held(&dev_priv->sb_lock);
> + lockdep_assert_held(&i915->sb_lock);
>
> - if (intel_wait_for_register(&dev_priv->uncore,
> - SBI_CTL_STAT, SBI_BUSY, 0,
> - 100)) {
> + if (intel_wait_for_register_fw(uncore,
> + SBI_CTL_STAT, SBI_BUSY, 0,
> + 100)) {
> DRM_ERROR("timeout waiting for SBI to become ready\n");
> - return 0;
> + return -EBUSY;
> }
>
> - I915_WRITE(SBI_ADDR, (reg << 16));
> - I915_WRITE(SBI_DATA, 0);
> + intel_uncore_write_fw(uncore, SBI_ADDR, (u32)reg << 16);
> + intel_uncore_write_fw(uncore, SBI_DATA, is_read ? 0 : *val);
>
> if (destination == SBI_ICLK)
> - value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
> + cmd = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
> else
> - value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
> - I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
> -
> - if (intel_wait_for_register(&dev_priv->uncore,
> - SBI_CTL_STAT,
> - SBI_BUSY,
> - 0,
> - 100)) {
> + cmd = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
> + if (!is_read)
> + cmd |= BIT(8);
> + intel_uncore_write_fw(uncore, SBI_CTL_STAT, cmd | SBI_BUSY);
> +
> + if (__intel_wait_for_register_fw(uncore,
> + SBI_CTL_STAT, SBI_BUSY, 0,
> + 100, 100, &cmd)) {
> DRM_ERROR("timeout waiting for SBI to complete read\n");
> - return 0;
> + return -ETIMEDOUT;
> }
>
> - if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
> + if (cmd & SBI_RESPONSE_FAIL) {
> DRM_ERROR("error during SBI read of reg %x\n", reg);
> - return 0;
> + return -ENXIO;
> }
>
> - return I915_READ(SBI_DATA);
> + if (is_read)
> + *val = intel_uncore_read_fw(uncore, SBI_DATA);
> +
> + return 0;
> }
>
> -void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
> - enum intel_sbi_destination destination)
> +u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
> + enum intel_sbi_destination destination)
> {
> - u32 tmp;
> + u32 result = 0;
>
> - lockdep_assert_held(&dev_priv->sb_lock);
> + intel_sbi_rw(i915, reg, destination, &result, true);
>
> - if (intel_wait_for_register(&dev_priv->uncore,
> - SBI_CTL_STAT, SBI_BUSY, 0,
> - 100)) {
> - DRM_ERROR("timeout waiting for SBI to become ready\n");
> - return;
> - }
> -
> - I915_WRITE(SBI_ADDR, (reg << 16));
> - I915_WRITE(SBI_DATA, value);
> -
> - if (destination == SBI_ICLK)
> - tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
> - else
> - tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
> - I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
> -
> - if (intel_wait_for_register(&dev_priv->uncore,
> - SBI_CTL_STAT,
> - SBI_BUSY,
> - 0,
> - 100)) {
> - DRM_ERROR("timeout waiting for SBI to complete write\n");
> - return;
> - }
> + return result;
> +}
>
> - if (I915_READ(SBI_CTL_STAT) & SBI_RESPONSE_FAIL) {
> - DRM_ERROR("error during SBI write of %x to reg %x\n",
> - value, reg);
> - return;
> - }
> +void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
> + enum intel_sbi_destination destination)
> +{
> + intel_sbi_rw(i915, reg, destination, &value, false);
> }
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH 09/10] drm/i915: Merge sandybridge_pcode_(read|write)
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (7 preceding siblings ...)
2019-04-19 17:14 ` [PATCH 08/10] drm/i915: Merge sbi read/write into a single accessor Chris Wilson
@ 2019-04-19 17:14 ` Chris Wilson
2019-04-19 17:14 ` [PATCH 10/10] drm/i915: Move sandybride pcode access to intel_sideband.c Chris Wilson
` (4 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:14 UTC (permalink / raw)
To: intel-gfx
These routines are identical except in the nature of the value parameter.
For writes it is a pure in-param, but for a read, we need an out-param.
Since they differ in a single line, merge the two routines into one.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/intel_pm.c | 115 +++++++++++---------------------
1 file changed, 40 insertions(+), 75 deletions(-)
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 9a810d0683f7..c9a321aa5d26 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9714,12 +9714,10 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
}
-static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
+static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv,
+ u32 mbox)
{
- u32 flags =
- I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
-
- switch (flags) {
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
case GEN6_PCODE_SUCCESS:
return 0;
case GEN6_PCODE_UNIMPLEMENTED_CMD:
@@ -9732,17 +9730,15 @@ static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
case GEN6_PCODE_TIMEOUT:
return -ETIMEDOUT;
default:
- MISSING_CASE(flags);
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
return 0;
}
}
-static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
+static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv,
+ u32 mbox)
{
- u32 flags =
- I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
-
- switch (flags) {
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
case GEN6_PCODE_SUCCESS:
return 0;
case GEN6_PCODE_ILLEGAL_CMD:
@@ -9754,19 +9750,21 @@ static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
return -EOVERFLOW;
default:
- MISSING_CASE(flags);
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
return 0;
}
}
-static int
-__sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
+static int __sandybridge_pcode_rw(struct drm_i915_private *dev_priv,
+ u32 mbox, u32 *val,
+ int fast_timeout_us,
+ int slow_timeout_ms,
+ bool is_read)
{
- int status;
-
lockdep_assert_held(&dev_priv->sb_lock);
- /* GEN6_PCODE_* are outside of the forcewake domain, we can
+ /*
+ * GEN6_PCODE_* are outside of the forcewake domain, we can
* use te fw I915_READ variants to reduce the amount of work
* required when reading/writing.
*/
@@ -9780,70 +9778,37 @@ __sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
if (__intel_wait_for_register_fw(&dev_priv->uncore,
GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
- 500, 0, NULL))
+ fast_timeout_us,
+ slow_timeout_ms,
+ &mbox))
return -ETIMEDOUT;
- *val = I915_READ_FW(GEN6_PCODE_DATA);
- I915_WRITE_FW(GEN6_PCODE_DATA, 0);
+ if (is_read)
+ *val = I915_READ_FW(GEN6_PCODE_DATA);
if (INTEL_GEN(dev_priv) > 6)
- status = gen7_check_mailbox_status(dev_priv);
+ return gen7_check_mailbox_status(dev_priv, mbox);
else
- status = gen6_check_mailbox_status(dev_priv);
-
- return status;
+ return gen6_check_mailbox_status(dev_priv, mbox);
}
int
sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
{
- int status;
+ int err;
mutex_lock(&dev_priv->sb_lock);
- status = __sandybridge_pcode_read(dev_priv, mbox, val);
+ err = __sandybridge_pcode_rw(dev_priv, mbox, val,
+ 500, 0,
+ true);
mutex_unlock(&dev_priv->sb_lock);
- if (status) {
+ if (err) {
DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
- mbox, __builtin_return_address(0), status);
+ mbox, __builtin_return_address(0), err);
}
- return status;
-}
-
-static int __sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
- u32 mbox, u32 val,
- int fast_timeout_us,
- int slow_timeout_ms)
-{
- int status;
-
- /* GEN6_PCODE_* are outside of the forcewake domain, we can
- * use te fw I915_READ variants to reduce the amount of work
- * required when reading/writing.
- */
-
- if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
- return -EAGAIN;
-
- I915_WRITE_FW(GEN6_PCODE_DATA, val);
- I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
- I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
-
- if (__intel_wait_for_register_fw(&dev_priv->uncore,
- GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
- fast_timeout_us, slow_timeout_ms,
- NULL))
- return -ETIMEDOUT;
-
- I915_WRITE_FW(GEN6_PCODE_DATA, 0);
-
- if (INTEL_GEN(dev_priv) > 6)
- status = gen7_check_mailbox_status(dev_priv);
- else
- status = gen6_check_mailbox_status(dev_priv);
-
- return status;
+ return err;
}
int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
@@ -9851,31 +9816,31 @@ int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
int fast_timeout_us,
int slow_timeout_ms)
{
- int status;
+ int err;
mutex_lock(&dev_priv->sb_lock);
- status = __sandybridge_pcode_write_timeout(dev_priv, mbox, val,
- fast_timeout_us,
- slow_timeout_ms);
+ err = __sandybridge_pcode_rw(dev_priv, mbox, &val,
+ fast_timeout_us, slow_timeout_ms,
+ false);
mutex_unlock(&dev_priv->sb_lock);
- if (status) {
+ if (err) {
DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
- val, mbox, __builtin_return_address(0), status);
+ val, mbox, __builtin_return_address(0), err);
}
- return status;
+ return err;
}
static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
u32 request, u32 reply_mask, u32 reply,
u32 *status)
{
- u32 val = request;
-
- *status = __sandybridge_pcode_read(dev_priv, mbox, &val);
+ *status = __sandybridge_pcode_rw(dev_priv, mbox, &request,
+ 500, 0,
+ true);
- return *status || ((val & reply_mask) == reply);
+ return *status || ((request & reply_mask) == reply);
}
/**
--
2.20.1
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply related [flat|nested] 23+ messages in thread* [PATCH 10/10] drm/i915: Move sandybride pcode access to intel_sideband.c
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (8 preceding siblings ...)
2019-04-19 17:14 ` [PATCH 09/10] drm/i915: Merge sandybridge_pcode_(read|write) Chris Wilson
@ 2019-04-19 17:14 ` Chris Wilson
2019-04-23 17:22 ` Ville Syrjälä
2019-04-19 17:39 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband Patchwork
` (3 subsequent siblings)
13 siblings, 1 reply; 23+ messages in thread
From: Chris Wilson @ 2019-04-19 17:14 UTC (permalink / raw)
To: intel-gfx
sandybride_pcode is another sideband, so move it to their new home.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
---
drivers/gpu/drm/i915/i915_drv.h | 10 --
drivers/gpu/drm/i915/intel_hdcp.c | 1 +
drivers/gpu/drm/i915/intel_pm.c | 195 -------------------------
drivers/gpu/drm/i915/intel_sideband.c | 196 ++++++++++++++++++++++++++
drivers/gpu/drm/i915/intel_sideband.h | 10 ++
5 files changed, 207 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index f4879fb41aa6..45c998870b87 100644
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -3427,16 +3427,6 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv);
extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
struct intel_display_error_state *error);
-int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
-int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
- u32 val, int fast_timeout_us,
- int slow_timeout_ms);
-#define sandybridge_pcode_write(dev_priv, mbox, val) \
- sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
-
-int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
- u32 reply_mask, u32 reply, int timeout_base_ms);
-
/* intel_dpio_phy.c */
void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
enum dpio_phy *phy, enum dpio_channel *ch);
diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
index 2476e867981d..ca5982e45e3e 100644
--- a/drivers/gpu/drm/i915/intel_hdcp.c
+++ b/drivers/gpu/drm/i915/intel_hdcp.c
@@ -16,6 +16,7 @@
#include "i915_reg.h"
#include "intel_drv.h"
#include "intel_hdcp.h"
+#include "intel_sideband.h"
#define KEY_LOAD_TRIES 5
#define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index c9a321aa5d26..0904f5ff2deb 100644
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -9714,201 +9714,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
}
}
-static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv,
- u32 mbox)
-{
- switch (mbox & GEN6_PCODE_ERROR_MASK) {
- case GEN6_PCODE_SUCCESS:
- return 0;
- case GEN6_PCODE_UNIMPLEMENTED_CMD:
- return -ENODEV;
- case GEN6_PCODE_ILLEGAL_CMD:
- return -ENXIO;
- case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- return -EOVERFLOW;
- case GEN6_PCODE_TIMEOUT:
- return -ETIMEDOUT;
- default:
- MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
- return 0;
- }
-}
-
-static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv,
- u32 mbox)
-{
- switch (mbox & GEN6_PCODE_ERROR_MASK) {
- case GEN6_PCODE_SUCCESS:
- return 0;
- case GEN6_PCODE_ILLEGAL_CMD:
- return -ENXIO;
- case GEN7_PCODE_TIMEOUT:
- return -ETIMEDOUT;
- case GEN7_PCODE_ILLEGAL_DATA:
- return -EINVAL;
- case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
- return -EOVERFLOW;
- default:
- MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
- return 0;
- }
-}
-
-static int __sandybridge_pcode_rw(struct drm_i915_private *dev_priv,
- u32 mbox, u32 *val,
- int fast_timeout_us,
- int slow_timeout_ms,
- bool is_read)
-{
- lockdep_assert_held(&dev_priv->sb_lock);
-
- /*
- * GEN6_PCODE_* are outside of the forcewake domain, we can
- * use te fw I915_READ variants to reduce the amount of work
- * required when reading/writing.
- */
-
- if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
- return -EAGAIN;
-
- I915_WRITE_FW(GEN6_PCODE_DATA, *val);
- I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
- I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
-
- if (__intel_wait_for_register_fw(&dev_priv->uncore,
- GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
- fast_timeout_us,
- slow_timeout_ms,
- &mbox))
- return -ETIMEDOUT;
-
- if (is_read)
- *val = I915_READ_FW(GEN6_PCODE_DATA);
-
- if (INTEL_GEN(dev_priv) > 6)
- return gen7_check_mailbox_status(dev_priv, mbox);
- else
- return gen6_check_mailbox_status(dev_priv, mbox);
-}
-
-int
-sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
-{
- int err;
-
- mutex_lock(&dev_priv->sb_lock);
- err = __sandybridge_pcode_rw(dev_priv, mbox, val,
- 500, 0,
- true);
- mutex_unlock(&dev_priv->sb_lock);
-
- if (err) {
- DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
- mbox, __builtin_return_address(0), err);
- }
-
- return err;
-}
-
-int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
- u32 mbox, u32 val,
- int fast_timeout_us,
- int slow_timeout_ms)
-{
- int err;
-
- mutex_lock(&dev_priv->sb_lock);
- err = __sandybridge_pcode_rw(dev_priv, mbox, &val,
- fast_timeout_us, slow_timeout_ms,
- false);
- mutex_unlock(&dev_priv->sb_lock);
-
- if (err) {
- DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
- val, mbox, __builtin_return_address(0), err);
- }
-
- return err;
-}
-
-static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
- u32 request, u32 reply_mask, u32 reply,
- u32 *status)
-{
- *status = __sandybridge_pcode_rw(dev_priv, mbox, &request,
- 500, 0,
- true);
-
- return *status || ((request & reply_mask) == reply);
-}
-
-/**
- * skl_pcode_request - send PCODE request until acknowledgment
- * @dev_priv: device private
- * @mbox: PCODE mailbox ID the request is targeted for
- * @request: request ID
- * @reply_mask: mask used to check for request acknowledgment
- * @reply: value used to check for request acknowledgment
- * @timeout_base_ms: timeout for polling with preemption enabled
- *
- * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
- * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
- * The request is acknowledged once the PCODE reply dword equals @reply after
- * applying @reply_mask. Polling is first attempted with preemption enabled
- * for @timeout_base_ms and if this times out for another 50 ms with
- * preemption disabled.
- *
- * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
- * other error as reported by PCODE.
- */
-int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
- u32 reply_mask, u32 reply, int timeout_base_ms)
-{
- u32 status;
- int ret;
-
- mutex_lock(&dev_priv->sb_lock);
-
-#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
- &status)
-
- /*
- * Prime the PCODE by doing a request first. Normally it guarantees
- * that a subsequent request, at most @timeout_base_ms later, succeeds.
- * _wait_for() doesn't guarantee when its passed condition is evaluated
- * first, so send the first request explicitly.
- */
- if (COND) {
- ret = 0;
- goto out;
- }
- ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
- if (!ret)
- goto out;
-
- /*
- * The above can time out if the number of requests was low (2 in the
- * worst case) _and_ PCODE was busy for some reason even after a
- * (queued) request and @timeout_base_ms delay. As a workaround retry
- * the poll with preemption disabled to maximize the number of
- * requests. Increase the timeout from @timeout_base_ms to 50ms to
- * account for interrupts that could reduce the number of these
- * requests, and for any quirks of the PCODE firmware that delays
- * the request completion.
- */
- DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
- WARN_ON_ONCE(timeout_base_ms > 3);
- preempt_disable();
- ret = wait_for_atomic(COND, 50);
- preempt_enable();
-
-out:
- mutex_unlock(&dev_priv->sb_lock);
- return ret ? ret : status;
-#undef COND
-}
-
static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
{
struct intel_rps *rps = &dev_priv->gt_pm.rps;
diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
index 7113fb8850d6..87b5a14c7ca8 100644
--- a/drivers/gpu/drm/i915/intel_sideband.c
+++ b/drivers/gpu/drm/i915/intel_sideband.c
@@ -333,3 +333,199 @@ void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
{
intel_sbi_rw(i915, reg, destination, &value, false);
}
+
+static inline int gen6_check_mailbox_status(u32 mbox)
+{
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
+ case GEN6_PCODE_SUCCESS:
+ return 0;
+ case GEN6_PCODE_UNIMPLEMENTED_CMD:
+ return -ENODEV;
+ case GEN6_PCODE_ILLEGAL_CMD:
+ return -ENXIO;
+ case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+ case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+ return -EOVERFLOW;
+ case GEN6_PCODE_TIMEOUT:
+ return -ETIMEDOUT;
+ default:
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
+ return 0;
+ }
+}
+
+static inline int gen7_check_mailbox_status(u32 mbox)
+{
+ switch (mbox & GEN6_PCODE_ERROR_MASK) {
+ case GEN6_PCODE_SUCCESS:
+ return 0;
+ case GEN6_PCODE_ILLEGAL_CMD:
+ return -ENXIO;
+ case GEN7_PCODE_TIMEOUT:
+ return -ETIMEDOUT;
+ case GEN7_PCODE_ILLEGAL_DATA:
+ return -EINVAL;
+ case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
+ return -EOVERFLOW;
+ default:
+ MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
+ return 0;
+ }
+}
+
+static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
+ u32 mbox, u32 *val,
+ int fast_timeout_us,
+ int slow_timeout_ms,
+ bool is_read)
+{
+ struct intel_uncore *uncore = &i915->uncore;
+
+ lockdep_assert_held(&i915->sb_lock);
+
+ /*
+ * GEN6_PCODE_* are outside of the forcewake domain, we can
+ * use te fw I915_READ variants to reduce the amount of work
+ * required when reading/writing.
+ */
+
+ if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
+ return -EAGAIN;
+
+ intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
+ intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, 0);
+ intel_uncore_write_fw(uncore,
+ GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
+
+ if (__intel_wait_for_register_fw(uncore,
+ GEN6_PCODE_MAILBOX,
+ GEN6_PCODE_READY, 0,
+ fast_timeout_us,
+ slow_timeout_ms,
+ &mbox))
+ return -ETIMEDOUT;
+
+ if (is_read)
+ *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
+
+ if (INTEL_GEN(i915) > 6)
+ return gen7_check_mailbox_status(mbox);
+ else
+ return gen6_check_mailbox_status(mbox);
+}
+
+int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val)
+{
+ int err;
+
+ mutex_lock(&i915->sb_lock);
+ err = __sandybridge_pcode_rw(i915, mbox, val,
+ 500, 0,
+ true);
+ mutex_unlock(&i915->sb_lock);
+
+ if (err) {
+ DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
+ mbox, __builtin_return_address(0), err);
+ }
+
+ return err;
+}
+
+int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
+ u32 mbox, u32 val,
+ int fast_timeout_us,
+ int slow_timeout_ms)
+{
+ int err;
+
+ mutex_lock(&i915->sb_lock);
+ err = __sandybridge_pcode_rw(i915, mbox, &val,
+ fast_timeout_us, slow_timeout_ms,
+ false);
+ mutex_unlock(&i915->sb_lock);
+
+ if (err) {
+ DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
+ val, mbox, __builtin_return_address(0), err);
+ }
+
+ return err;
+}
+
+static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
+ u32 request, u32 reply_mask, u32 reply,
+ u32 *status)
+{
+ *status = __sandybridge_pcode_rw(i915, mbox, &request,
+ 500, 0,
+ true);
+
+ return *status || ((request & reply_mask) == reply);
+}
+
+/**
+ * skl_pcode_request - send PCODE request until acknowledgment
+ * @i915: device private
+ * @mbox: PCODE mailbox ID the request is targeted for
+ * @request: request ID
+ * @reply_mask: mask used to check for request acknowledgment
+ * @reply: value used to check for request acknowledgment
+ * @timeout_base_ms: timeout for polling with preemption enabled
+ *
+ * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
+ * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
+ * The request is acknowledged once the PCODE reply dword equals @reply after
+ * applying @reply_mask. Polling is first attempted with preemption enabled
+ * for @timeout_base_ms and if this times out for another 50 ms with
+ * preemption disabled.
+ *
+ * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
+ * other error as reported by PCODE.
+ */
+int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
+ u32 reply_mask, u32 reply, int timeout_base_ms)
+{
+ u32 status;
+ int ret;
+
+ mutex_lock(&i915->sb_lock);
+
+#define COND \
+ skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
+
+ /*
+ * Prime the PCODE by doing a request first. Normally it guarantees
+ * that a subsequent request, at most @timeout_base_ms later, succeeds.
+ * _wait_for() doesn't guarantee when its passed condition is evaluated
+ * first, so send the first request explicitly.
+ */
+ if (COND) {
+ ret = 0;
+ goto out;
+ }
+ ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
+ if (!ret)
+ goto out;
+
+ /*
+ * The above can time out if the number of requests was low (2 in the
+ * worst case) _and_ PCODE was busy for some reason even after a
+ * (queued) request and @timeout_base_ms delay. As a workaround retry
+ * the poll with preemption disabled to maximize the number of
+ * requests. Increase the timeout from @timeout_base_ms to 50ms to
+ * account for interrupts that could reduce the number of these
+ * requests, and for any quirks of the PCODE firmware that delays
+ * the request completion.
+ */
+ DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
+ WARN_ON_ONCE(timeout_base_ms > 3);
+ preempt_disable();
+ ret = wait_for_atomic(COND, 50);
+ preempt_enable();
+
+out:
+ mutex_unlock(&i915->sb_lock);
+ return ret ? ret : status;
+#undef COND
+}
diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
index 9d36bdc17955..a0907e2c4992 100644
--- a/drivers/gpu/drm/i915/intel_sideband.h
+++ b/drivers/gpu/drm/i915/intel_sideband.h
@@ -127,4 +127,14 @@ u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
enum intel_sbi_destination destination);
+int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val);
+int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
+ u32 val, int fast_timeout_us,
+ int slow_timeout_ms);
+#define sandybridge_pcode_write(i915, mbox, val) \
+ sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
+
+int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
+ u32 reply_mask, u32 reply, int timeout_base_ms);
+
#endif /* _INTEL_SIDEBAND_H */
--
2.20.1
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^ permalink raw reply related [flat|nested] 23+ messages in thread* Re: [PATCH 10/10] drm/i915: Move sandybride pcode access to intel_sideband.c
2019-04-19 17:14 ` [PATCH 10/10] drm/i915: Move sandybride pcode access to intel_sideband.c Chris Wilson
@ 2019-04-23 17:22 ` Ville Syrjälä
0 siblings, 0 replies; 23+ messages in thread
From: Ville Syrjälä @ 2019-04-23 17:22 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
On Fri, Apr 19, 2019 at 06:14:02PM +0100, Chris Wilson wrote:
> sandybride_pcode is another sideband, so move it to their new home.
Close enough.
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
> ---
> drivers/gpu/drm/i915/i915_drv.h | 10 --
> drivers/gpu/drm/i915/intel_hdcp.c | 1 +
> drivers/gpu/drm/i915/intel_pm.c | 195 -------------------------
> drivers/gpu/drm/i915/intel_sideband.c | 196 ++++++++++++++++++++++++++
> drivers/gpu/drm/i915/intel_sideband.h | 10 ++
> 5 files changed, 207 insertions(+), 205 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
> index f4879fb41aa6..45c998870b87 100644
> --- a/drivers/gpu/drm/i915/i915_drv.h
> +++ b/drivers/gpu/drm/i915/i915_drv.h
> @@ -3427,16 +3427,6 @@ intel_display_capture_error_state(struct drm_i915_private *dev_priv);
> extern void intel_display_print_error_state(struct drm_i915_error_state_buf *e,
> struct intel_display_error_state *error);
>
> -int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
> -int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv, u32 mbox,
> - u32 val, int fast_timeout_us,
> - int slow_timeout_ms);
> -#define sandybridge_pcode_write(dev_priv, mbox, val) \
> - sandybridge_pcode_write_timeout(dev_priv, mbox, val, 500, 0)
> -
> -int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
> - u32 reply_mask, u32 reply, int timeout_base_ms);
> -
> /* intel_dpio_phy.c */
> void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
> enum dpio_phy *phy, enum dpio_channel *ch);
> diff --git a/drivers/gpu/drm/i915/intel_hdcp.c b/drivers/gpu/drm/i915/intel_hdcp.c
> index 2476e867981d..ca5982e45e3e 100644
> --- a/drivers/gpu/drm/i915/intel_hdcp.c
> +++ b/drivers/gpu/drm/i915/intel_hdcp.c
> @@ -16,6 +16,7 @@
> #include "i915_reg.h"
> #include "intel_drv.h"
> #include "intel_hdcp.h"
> +#include "intel_sideband.h"
>
> #define KEY_LOAD_TRIES 5
> #define ENCRYPT_STATUS_CHANGE_TIMEOUT_MS 50
> diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
> index c9a321aa5d26..0904f5ff2deb 100644
> --- a/drivers/gpu/drm/i915/intel_pm.c
> +++ b/drivers/gpu/drm/i915/intel_pm.c
> @@ -9714,201 +9714,6 @@ void intel_init_pm(struct drm_i915_private *dev_priv)
> }
> }
>
> -static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv,
> - u32 mbox)
> -{
> - switch (mbox & GEN6_PCODE_ERROR_MASK) {
> - case GEN6_PCODE_SUCCESS:
> - return 0;
> - case GEN6_PCODE_UNIMPLEMENTED_CMD:
> - return -ENODEV;
> - case GEN6_PCODE_ILLEGAL_CMD:
> - return -ENXIO;
> - case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> - case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> - return -EOVERFLOW;
> - case GEN6_PCODE_TIMEOUT:
> - return -ETIMEDOUT;
> - default:
> - MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> - return 0;
> - }
> -}
> -
> -static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv,
> - u32 mbox)
> -{
> - switch (mbox & GEN6_PCODE_ERROR_MASK) {
> - case GEN6_PCODE_SUCCESS:
> - return 0;
> - case GEN6_PCODE_ILLEGAL_CMD:
> - return -ENXIO;
> - case GEN7_PCODE_TIMEOUT:
> - return -ETIMEDOUT;
> - case GEN7_PCODE_ILLEGAL_DATA:
> - return -EINVAL;
> - case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> - return -EOVERFLOW;
> - default:
> - MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> - return 0;
> - }
> -}
> -
> -static int __sandybridge_pcode_rw(struct drm_i915_private *dev_priv,
> - u32 mbox, u32 *val,
> - int fast_timeout_us,
> - int slow_timeout_ms,
> - bool is_read)
> -{
> - lockdep_assert_held(&dev_priv->sb_lock);
> -
> - /*
> - * GEN6_PCODE_* are outside of the forcewake domain, we can
> - * use te fw I915_READ variants to reduce the amount of work
> - * required when reading/writing.
> - */
> -
> - if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
> - return -EAGAIN;
> -
> - I915_WRITE_FW(GEN6_PCODE_DATA, *val);
> - I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
> - I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
> -
> - if (__intel_wait_for_register_fw(&dev_priv->uncore,
> - GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
> - fast_timeout_us,
> - slow_timeout_ms,
> - &mbox))
> - return -ETIMEDOUT;
> -
> - if (is_read)
> - *val = I915_READ_FW(GEN6_PCODE_DATA);
> -
> - if (INTEL_GEN(dev_priv) > 6)
> - return gen7_check_mailbox_status(dev_priv, mbox);
> - else
> - return gen6_check_mailbox_status(dev_priv, mbox);
> -}
> -
> -int
> -sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
> -{
> - int err;
> -
> - mutex_lock(&dev_priv->sb_lock);
> - err = __sandybridge_pcode_rw(dev_priv, mbox, val,
> - 500, 0,
> - true);
> - mutex_unlock(&dev_priv->sb_lock);
> -
> - if (err) {
> - DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
> - mbox, __builtin_return_address(0), err);
> - }
> -
> - return err;
> -}
> -
> -int sandybridge_pcode_write_timeout(struct drm_i915_private *dev_priv,
> - u32 mbox, u32 val,
> - int fast_timeout_us,
> - int slow_timeout_ms)
> -{
> - int err;
> -
> - mutex_lock(&dev_priv->sb_lock);
> - err = __sandybridge_pcode_rw(dev_priv, mbox, &val,
> - fast_timeout_us, slow_timeout_ms,
> - false);
> - mutex_unlock(&dev_priv->sb_lock);
> -
> - if (err) {
> - DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
> - val, mbox, __builtin_return_address(0), err);
> - }
> -
> - return err;
> -}
> -
> -static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox,
> - u32 request, u32 reply_mask, u32 reply,
> - u32 *status)
> -{
> - *status = __sandybridge_pcode_rw(dev_priv, mbox, &request,
> - 500, 0,
> - true);
> -
> - return *status || ((request & reply_mask) == reply);
> -}
> -
> -/**
> - * skl_pcode_request - send PCODE request until acknowledgment
> - * @dev_priv: device private
> - * @mbox: PCODE mailbox ID the request is targeted for
> - * @request: request ID
> - * @reply_mask: mask used to check for request acknowledgment
> - * @reply: value used to check for request acknowledgment
> - * @timeout_base_ms: timeout for polling with preemption enabled
> - *
> - * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
> - * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
> - * The request is acknowledged once the PCODE reply dword equals @reply after
> - * applying @reply_mask. Polling is first attempted with preemption enabled
> - * for @timeout_base_ms and if this times out for another 50 ms with
> - * preemption disabled.
> - *
> - * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
> - * other error as reported by PCODE.
> - */
> -int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request,
> - u32 reply_mask, u32 reply, int timeout_base_ms)
> -{
> - u32 status;
> - int ret;
> -
> - mutex_lock(&dev_priv->sb_lock);
> -
> -#define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \
> - &status)
> -
> - /*
> - * Prime the PCODE by doing a request first. Normally it guarantees
> - * that a subsequent request, at most @timeout_base_ms later, succeeds.
> - * _wait_for() doesn't guarantee when its passed condition is evaluated
> - * first, so send the first request explicitly.
> - */
> - if (COND) {
> - ret = 0;
> - goto out;
> - }
> - ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
> - if (!ret)
> - goto out;
> -
> - /*
> - * The above can time out if the number of requests was low (2 in the
> - * worst case) _and_ PCODE was busy for some reason even after a
> - * (queued) request and @timeout_base_ms delay. As a workaround retry
> - * the poll with preemption disabled to maximize the number of
> - * requests. Increase the timeout from @timeout_base_ms to 50ms to
> - * account for interrupts that could reduce the number of these
> - * requests, and for any quirks of the PCODE firmware that delays
> - * the request completion.
> - */
> - DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
> - WARN_ON_ONCE(timeout_base_ms > 3);
> - preempt_disable();
> - ret = wait_for_atomic(COND, 50);
> - preempt_enable();
> -
> -out:
> - mutex_unlock(&dev_priv->sb_lock);
> - return ret ? ret : status;
> -#undef COND
> -}
> -
> static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
> {
> struct intel_rps *rps = &dev_priv->gt_pm.rps;
> diff --git a/drivers/gpu/drm/i915/intel_sideband.c b/drivers/gpu/drm/i915/intel_sideband.c
> index 7113fb8850d6..87b5a14c7ca8 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.c
> +++ b/drivers/gpu/drm/i915/intel_sideband.c
> @@ -333,3 +333,199 @@ void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
> {
> intel_sbi_rw(i915, reg, destination, &value, false);
> }
> +
> +static inline int gen6_check_mailbox_status(u32 mbox)
> +{
> + switch (mbox & GEN6_PCODE_ERROR_MASK) {
> + case GEN6_PCODE_SUCCESS:
> + return 0;
> + case GEN6_PCODE_UNIMPLEMENTED_CMD:
> + return -ENODEV;
> + case GEN6_PCODE_ILLEGAL_CMD:
> + return -ENXIO;
> + case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> + case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> + return -EOVERFLOW;
> + case GEN6_PCODE_TIMEOUT:
> + return -ETIMEDOUT;
> + default:
> + MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> + return 0;
> + }
> +}
> +
> +static inline int gen7_check_mailbox_status(u32 mbox)
> +{
> + switch (mbox & GEN6_PCODE_ERROR_MASK) {
> + case GEN6_PCODE_SUCCESS:
> + return 0;
> + case GEN6_PCODE_ILLEGAL_CMD:
> + return -ENXIO;
> + case GEN7_PCODE_TIMEOUT:
> + return -ETIMEDOUT;
> + case GEN7_PCODE_ILLEGAL_DATA:
> + return -EINVAL;
> + case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
> + return -EOVERFLOW;
> + default:
> + MISSING_CASE(mbox & GEN6_PCODE_ERROR_MASK);
> + return 0;
> + }
> +}
> +
> +static int __sandybridge_pcode_rw(struct drm_i915_private *i915,
> + u32 mbox, u32 *val,
> + int fast_timeout_us,
> + int slow_timeout_ms,
> + bool is_read)
> +{
> + struct intel_uncore *uncore = &i915->uncore;
> +
> + lockdep_assert_held(&i915->sb_lock);
> +
> + /*
> + * GEN6_PCODE_* are outside of the forcewake domain, we can
> + * use te fw I915_READ variants to reduce the amount of work
> + * required when reading/writing.
> + */
> +
> + if (intel_uncore_read_fw(uncore, GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY)
> + return -EAGAIN;
> +
> + intel_uncore_write_fw(uncore, GEN6_PCODE_DATA, *val);
> + intel_uncore_write_fw(uncore, GEN6_PCODE_DATA1, 0);
> + intel_uncore_write_fw(uncore,
> + GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
> +
> + if (__intel_wait_for_register_fw(uncore,
> + GEN6_PCODE_MAILBOX,
> + GEN6_PCODE_READY, 0,
> + fast_timeout_us,
> + slow_timeout_ms,
> + &mbox))
> + return -ETIMEDOUT;
> +
> + if (is_read)
> + *val = intel_uncore_read_fw(uncore, GEN6_PCODE_DATA);
> +
> + if (INTEL_GEN(i915) > 6)
> + return gen7_check_mailbox_status(mbox);
> + else
> + return gen6_check_mailbox_status(mbox);
> +}
> +
> +int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val)
> +{
> + int err;
> +
> + mutex_lock(&i915->sb_lock);
> + err = __sandybridge_pcode_rw(i915, mbox, val,
> + 500, 0,
> + true);
> + mutex_unlock(&i915->sb_lock);
> +
> + if (err) {
> + DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n",
> + mbox, __builtin_return_address(0), err);
> + }
> +
> + return err;
> +}
> +
> +int sandybridge_pcode_write_timeout(struct drm_i915_private *i915,
> + u32 mbox, u32 val,
> + int fast_timeout_us,
> + int slow_timeout_ms)
> +{
> + int err;
> +
> + mutex_lock(&i915->sb_lock);
> + err = __sandybridge_pcode_rw(i915, mbox, &val,
> + fast_timeout_us, slow_timeout_ms,
> + false);
> + mutex_unlock(&i915->sb_lock);
> +
> + if (err) {
> + DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n",
> + val, mbox, __builtin_return_address(0), err);
> + }
> +
> + return err;
> +}
> +
> +static bool skl_pcode_try_request(struct drm_i915_private *i915, u32 mbox,
> + u32 request, u32 reply_mask, u32 reply,
> + u32 *status)
> +{
> + *status = __sandybridge_pcode_rw(i915, mbox, &request,
> + 500, 0,
> + true);
> +
> + return *status || ((request & reply_mask) == reply);
> +}
> +
> +/**
> + * skl_pcode_request - send PCODE request until acknowledgment
> + * @i915: device private
> + * @mbox: PCODE mailbox ID the request is targeted for
> + * @request: request ID
> + * @reply_mask: mask used to check for request acknowledgment
> + * @reply: value used to check for request acknowledgment
> + * @timeout_base_ms: timeout for polling with preemption enabled
> + *
> + * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE
> + * reports an error or an overall timeout of @timeout_base_ms+50 ms expires.
> + * The request is acknowledged once the PCODE reply dword equals @reply after
> + * applying @reply_mask. Polling is first attempted with preemption enabled
> + * for @timeout_base_ms and if this times out for another 50 ms with
> + * preemption disabled.
> + *
> + * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some
> + * other error as reported by PCODE.
> + */
> +int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply, int timeout_base_ms)
> +{
> + u32 status;
> + int ret;
> +
> + mutex_lock(&i915->sb_lock);
> +
> +#define COND \
> + skl_pcode_try_request(i915, mbox, request, reply_mask, reply, &status)
> +
> + /*
> + * Prime the PCODE by doing a request first. Normally it guarantees
> + * that a subsequent request, at most @timeout_base_ms later, succeeds.
> + * _wait_for() doesn't guarantee when its passed condition is evaluated
> + * first, so send the first request explicitly.
> + */
> + if (COND) {
> + ret = 0;
> + goto out;
> + }
> + ret = _wait_for(COND, timeout_base_ms * 1000, 10, 10);
> + if (!ret)
> + goto out;
> +
> + /*
> + * The above can time out if the number of requests was low (2 in the
> + * worst case) _and_ PCODE was busy for some reason even after a
> + * (queued) request and @timeout_base_ms delay. As a workaround retry
> + * the poll with preemption disabled to maximize the number of
> + * requests. Increase the timeout from @timeout_base_ms to 50ms to
> + * account for interrupts that could reduce the number of these
> + * requests, and for any quirks of the PCODE firmware that delays
> + * the request completion.
> + */
> + DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n");
> + WARN_ON_ONCE(timeout_base_ms > 3);
> + preempt_disable();
> + ret = wait_for_atomic(COND, 50);
> + preempt_enable();
> +
> +out:
> + mutex_unlock(&i915->sb_lock);
> + return ret ? ret : status;
> +#undef COND
> +}
> diff --git a/drivers/gpu/drm/i915/intel_sideband.h b/drivers/gpu/drm/i915/intel_sideband.h
> index 9d36bdc17955..a0907e2c4992 100644
> --- a/drivers/gpu/drm/i915/intel_sideband.h
> +++ b/drivers/gpu/drm/i915/intel_sideband.h
> @@ -127,4 +127,14 @@ u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg,
> void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value,
> enum intel_sbi_destination destination);
>
> +int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, u32 *val);
> +int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox,
> + u32 val, int fast_timeout_us,
> + int slow_timeout_ms);
> +#define sandybridge_pcode_write(i915, mbox, val) \
> + sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0)
> +
> +int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request,
> + u32 reply_mask, u32 reply, int timeout_base_ms);
> +
> #endif /* _INTEL_SIDEBAND_H */
> --
> 2.20.1
>
> _______________________________________________
> Intel-gfx mailing list
> Intel-gfx@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/intel-gfx
--
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread
* ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (9 preceding siblings ...)
2019-04-19 17:14 ` [PATCH 10/10] drm/i915: Move sandybride pcode access to intel_sideband.c Chris Wilson
@ 2019-04-19 17:39 ` Patchwork
2019-04-19 17:43 ` ✗ Fi.CI.SPARSE: " Patchwork
` (2 subsequent siblings)
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-04-19 17:39 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59761/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
9a0358d2f0eb drm/i915: Disable preemption and sleeping while using the punit sideband
ac0bbbdf8ffd drm/i915: Lift acquiring the vlv punit magic to a common sb-get
996c149bc68c drm/i915: Lift sideband locking for vlv_punit_(read|write)
17d443c65fc8 drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
5158724f31b4 Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
-:17: WARNING:COMMIT_LOG_LONG_LINE: Possible unwrapped commit description (prefer a maximum 75 chars per line)
#17:
References: 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3")
-:17: ERROR:GIT_COMMIT_ID: Please use git commit description style 'commit <12+ chars of sha1> ("<title line>")' - ie: 'commit 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3")'
#17:
References: 6067a27d1f01 ("drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3")
total: 1 errors, 1 warnings, 0 checks, 19 lines checked
9e3f2a44bd33 drm/i915: Replace pcu_lock with sb_lock
cbd87000b066 drm/i915: Separate sideband declarations to intel_sideband.h
-:324: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#324:
new file mode 100644
total: 0 errors, 1 warnings, 0 checks, 402 lines checked
0cc59105d0b5 drm/i915: Merge sbi read/write into a single accessor
ce383cc80b7e drm/i915: Merge sandybridge_pcode_(read|write)
07ec1cc6ae6f drm/i915: Move sandybride pcode access to intel_sideband.c
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* ✗ Fi.CI.SPARSE: warning for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (10 preceding siblings ...)
2019-04-19 17:39 ` ✗ Fi.CI.CHECKPATCH: warning for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband Patchwork
@ 2019-04-19 17:43 ` Patchwork
2019-04-19 17:59 ` ✓ Fi.CI.BAT: success " Patchwork
2019-04-19 19:44 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-04-19 17:43 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59761/
State : warning
== Summary ==
$ dim sparse origin/drm-tip
Sparse version: v0.5.2
Commit: drm/i915: Disable preemption and sleeping while using the punit sideband
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3618:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3619:16: warning: expression using sizeof(void)
Commit: drm/i915: Lift acquiring the vlv punit magic to a common sb-get
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3619:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3713:16: warning: expression using sizeof(void)
Commit: drm/i915: Lift sideband locking for vlv_punit_(read|write)
Okay!
Commit: drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
Okay!
Commit: Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
Okay!
Commit: drm/i915: Replace pcu_lock with sb_lock
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3713:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void)
Commit: drm/i915: Separate sideband declarations to intel_sideband.h
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3707:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3587:16: warning: expression using sizeof(void)
Commit: drm/i915: Merge sbi read/write into a single accessor
Okay!
Commit: drm/i915: Merge sandybridge_pcode_(read|write)
Okay!
Commit: drm/i915: Move sandybride pcode access to intel_sideband.c
-drivers/gpu/drm/i915/selftests/../i915_drv.h:3587:16: warning: expression using sizeof(void)
+drivers/gpu/drm/i915/selftests/../i915_drv.h:3577:16: warning: expression using sizeof(void)
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread* ✓ Fi.CI.BAT: success for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (11 preceding siblings ...)
2019-04-19 17:43 ` ✗ Fi.CI.SPARSE: " Patchwork
@ 2019-04-19 17:59 ` Patchwork
2019-04-19 19:44 ` ✓ Fi.CI.IGT: " Patchwork
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-04-19 17:59 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59761/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5958 -> Patchwork_12844
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://patchwork.freedesktop.org/api/1.0/series/59761/revisions/1/mbox/
Known issues
------------
Here are the changes found in Patchwork_12844 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] +50
* igt@amdgpu/amd_cs_nop@fork-compute0:
- fi-icl-y: NOTRUN -> SKIP [fdo#109315] +17
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109315] +17
* igt@gem_exec_basic@basic-bsd2:
- fi-icl-y: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_basic@gtt-bsd:
- fi-bwr-2160: NOTRUN -> SKIP [fdo#109271] +98
* igt@gem_exec_basic@gtt-bsd2:
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] +52
* igt@gem_exec_basic@readonly-bsd1:
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] +52
- fi-icl-u2: NOTRUN -> SKIP [fdo#109276] +7
* igt@gem_exec_parse@basic-allowed:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_exec_parse@basic-rejected:
- fi-icl-y: NOTRUN -> SKIP [fdo#109289] +1
* igt@gem_exec_store@basic-bsd2:
- fi-hsw-4770: NOTRUN -> SKIP [fdo#109271] +41
- fi-bxt-dsi: NOTRUN -> SKIP [fdo#109271] +47
* igt@i915_selftest@live_execlists:
- fi-apl-guc: NOTRUN -> INCOMPLETE [fdo#103927] / [fdo#109720]
* igt@kms_busy@basic-flip-c:
- fi-bwr-2160: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-byt-clapper: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-bsw-kefka: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
- fi-snb-2520m: NOTRUN -> SKIP [fdo#109271] / [fdo#109278]
* igt@kms_chamelium@dp-crc-fast:
- fi-icl-y: NOTRUN -> SKIP [fdo#109284] +8
* igt@kms_chamelium@dp-edid-read:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109316] +2
* igt@kms_chamelium@hdmi-crc-fast:
- fi-byt-j1900: NOTRUN -> SKIP [fdo#109271] +47
* igt@kms_chamelium@vga-hpd-fast:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109309] +1
* igt@kms_force_connector_basic@force-load-detect:
- fi-icl-y: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_force_connector_basic@prune-stale-modes:
- fi-icl-u2: NOTRUN -> SKIP [fdo#109285] +3
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-byt-clapper: NOTRUN -> FAIL [fdo#103191]
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-glk-dsi: PASS -> FAIL [fdo#103191]
* igt@kms_psr@primary_mmap_gtt:
- fi-icl-y: NOTRUN -> SKIP [fdo#110189] +3
* igt@kms_psr@primary_page_flip:
- fi-apl-guc: NOTRUN -> SKIP [fdo#109271] +48
* igt@prime_vgem@basic-fence-flip:
- fi-icl-y: NOTRUN -> SKIP [fdo#109294]
* igt@runner@aborted:
- fi-apl-guc: NOTRUN -> FAIL [fdo#108622] / [fdo#109720]
#### Possible fixes ####
* igt@kms_pipe_crc_basic@nonblocking-crc-pipe-a:
- fi-glk-dsi: FAIL [fdo#103191] -> PASS
[fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#108622]: https://bugs.freedesktop.org/show_bug.cgi?id=108622
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109294]: https://bugs.freedesktop.org/show_bug.cgi?id=109294
[fdo#109309]: https://bugs.freedesktop.org/show_bug.cgi?id=109309
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#109316]: https://bugs.freedesktop.org/show_bug.cgi?id=109316
[fdo#109720]: https://bugs.freedesktop.org/show_bug.cgi?id=109720
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
Participating hosts (36 -> 41)
------------------------------
Additional (10): fi-bxt-dsi fi-byt-j1900 fi-icl-u2 fi-bwr-2160 fi-apl-guc fi-snb-2520m fi-byt-clapper fi-hsw-4770 fi-icl-y fi-bsw-kefka
Missing (5): fi-ilk-m540 fi-byt-squawks fi-ctg-p8600 fi-ivb-3770 fi-bdw-samus
Build changes
-------------
* Linux: CI_DRM_5958 -> Patchwork_12844
CI_DRM_5958: dabbe59fd2bb5dca3d2607c49369161ec7160df3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4959: 504367d33b787de2ba8e007a5b620cfd6f0b3074 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12844: 07ec1cc6ae6f4330a9e394632893e3418c7c211f @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
07ec1cc6ae6f drm/i915: Move sandybride pcode access to intel_sideband.c
ce383cc80b7e drm/i915: Merge sandybridge_pcode_(read|write)
0cc59105d0b5 drm/i915: Merge sbi read/write into a single accessor
cbd87000b066 drm/i915: Separate sideband declarations to intel_sideband.h
9e3f2a44bd33 drm/i915: Replace pcu_lock with sb_lock
5158724f31b4 Revert "drm/i915: Avoid tweaking evaluation thresholds on Baytrail v3"
17d443c65fc8 drm/i915: Reduce RPS update frequency on Valleyview/Cherryview
996c149bc68c drm/i915: Lift sideband locking for vlv_punit_(read|write)
ac0bbbdf8ffd drm/i915: Lift acquiring the vlv punit magic to a common sb-get
9a0358d2f0eb drm/i915: Disable preemption and sleeping while using the punit sideband
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12844/
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^ permalink raw reply [flat|nested] 23+ messages in thread* ✓ Fi.CI.IGT: success for series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
2019-04-19 17:13 Nefarious Baytrail Chris Wilson
` (12 preceding siblings ...)
2019-04-19 17:59 ` ✓ Fi.CI.BAT: success " Patchwork
@ 2019-04-19 19:44 ` Patchwork
13 siblings, 0 replies; 23+ messages in thread
From: Patchwork @ 2019-04-19 19:44 UTC (permalink / raw)
To: Chris Wilson; +Cc: intel-gfx
== Series Details ==
Series: series starting with [01/10] drm/i915: Disable preemption and sleeping while using the punit sideband
URL : https://patchwork.freedesktop.org/series/59761/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_5958_full -> Patchwork_12844_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_12844_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* {igt@audio@hdmi-integrity}:
- shard-skl: NOTRUN -> FAIL
Known issues
------------
Here are the changes found in Patchwork_12844_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_eio@reset-stress:
- shard-snb: PASS -> FAIL [fdo#109661]
* igt@gem_exec_schedule@preempt-self-bsd2:
- shard-iclb: NOTRUN -> SKIP [fdo#109276] +3
* igt@i915_pm_rpm@universal-planes:
- shard-skl: PASS -> INCOMPLETE [fdo#107807]
* igt@kms_busy@extended-modeset-hang-oldfb-render-b:
- shard-apl: PASS -> INCOMPLETE [fdo#103927]
* igt@kms_chamelium@hdmi-crc-fast:
- shard-iclb: NOTRUN -> SKIP [fdo#109284] +2
* igt@kms_cursor_legacy@2x-long-nonblocking-modeset-vs-cursor-atomic:
- shard-glk: PASS -> FAIL [fdo#106509] / [fdo#107409]
* igt@kms_cursor_legacy@cursorb-vs-flipa-atomic-transitions:
- shard-iclb: NOTRUN -> SKIP [fdo#109274]
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-move:
- shard-iclb: PASS -> FAIL [fdo#103167] +2
* igt@kms_frontbuffer_tracking@fbc-2p-primscrn-spr-indfb-onoff:
- shard-iclb: NOTRUN -> SKIP [fdo#109280] +5
* igt@kms_frontbuffer_tracking@fbc-rgb565-draw-pwrite:
- shard-glk: PASS -> FAIL [fdo#103167]
* igt@kms_pipe_b_c_ivb@enable-pipe-c-while-b-has-3-lanes:
- shard-iclb: NOTRUN -> SKIP [fdo#109289]
* igt@kms_pipe_crc_basic@read-crc-pipe-e:
- shard-iclb: NOTRUN -> SKIP [fdo#109278] +2
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-f:
- shard-skl: NOTRUN -> SKIP [fdo#109271] / [fdo#109278] +14
* igt@kms_plane@pixel-format-pipe-b-planes-source-clamping:
- shard-glk: PASS -> SKIP [fdo#109271]
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes:
- shard-apl: PASS -> DMESG-WARN [fdo#108566] +1
* igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
- shard-skl: NOTRUN -> FAIL [fdo#108145] +3
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: PASS -> FAIL [fdo#108145] / [fdo#110403]
* igt@kms_plane_lowres@pipe-a-tiling-x:
- shard-iclb: PASS -> FAIL [fdo#103166]
* igt@kms_psr@no_drrs:
- shard-iclb: PASS -> FAIL [fdo#108341]
* igt@kms_psr@psr2_cursor_plane_onoff:
- shard-iclb: PASS -> SKIP [fdo#109441] +2
* igt@kms_psr@psr2_cursor_render:
- shard-iclb: NOTRUN -> SKIP [fdo#109441] +1
* igt@kms_rotation_crc@multiplane-rotation:
- shard-kbl: PASS -> DMESG-FAIL [fdo#105763]
* igt@kms_setmode@basic:
- shard-skl: NOTRUN -> FAIL [fdo#99912]
* igt@kms_vrr@flip-suspend:
- shard-skl: NOTRUN -> SKIP [fdo#109271] +162
* igt@prime_vgem@fence-write-hang:
- shard-iclb: NOTRUN -> SKIP [fdo#109295]
* igt@tools_test@sysfs_l3_parity:
- shard-iclb: NOTRUN -> SKIP [fdo#109307]
#### Possible fixes ####
* igt@gem_tiled_swapping@non-threaded:
- shard-iclb: DMESG-WARN [fdo#108686] -> PASS
* igt@i915_pm_rpm@gem-execbuf:
- shard-skl: INCOMPLETE [fdo#107803] / [fdo#107807] -> PASS
* igt@i915_suspend@fence-restore-tiled2untiled:
- shard-apl: DMESG-WARN [fdo#108566] -> PASS +1
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-xtiled:
- shard-skl: FAIL [fdo#103184] -> PASS
* igt@kms_flip@flip-vs-suspend:
- shard-skl: INCOMPLETE [fdo#109507] -> PASS
* igt@kms_frontbuffer_tracking@fbc-1p-primscrn-cur-indfb-draw-blt:
- shard-iclb: FAIL [fdo#103167] -> PASS +3
* igt@kms_plane@pixel-format-pipe-a-planes-source-clamping:
- shard-glk: SKIP [fdo#109271] -> PASS +1
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes:
- shard-skl: INCOMPLETE [fdo#104108] / [fdo#107773] -> PASS +1
* igt@kms_plane_scaling@pipe-a-scaler-with-rotation:
- shard-glk: SKIP [fdo#109271] / [fdo#109278] -> PASS
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: SKIP [fdo#109441] -> PASS +1
* igt@kms_sysfs_edid_timing:
- shard-iclb: FAIL [fdo#100047] -> PASS
* igt@prime_busy@hang-default:
- shard-snb: FAIL [fdo#108807] -> PASS
#### Warnings ####
* igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
- shard-apl: DMESG-WARN [fdo#108566] -> INCOMPLETE [fdo#103927]
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#100047]: https://bugs.freedesktop.org/show_bug.cgi?id=100047
[fdo#103166]: https://bugs.freedesktop.org/show_bug.cgi?id=103166
[fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
[fdo#103184]: https://bugs.freedesktop.org/show_bug.cgi?id=103184
[fdo#103927]: https://bugs.freedesktop.org/show_bug.cgi?id=103927
[fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
[fdo#105763]: https://bugs.freedesktop.org/show_bug.cgi?id=105763
[fdo#106509]: https://bugs.freedesktop.org/show_bug.cgi?id=106509
[fdo#107409]: https://bugs.freedesktop.org/show_bug.cgi?id=107409
[fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
[fdo#107803]: https://bugs.freedesktop.org/show_bug.cgi?id=107803
[fdo#107807]: https://bugs.freedesktop.org/show_bug.cgi?id=107807
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#108341]: https://bugs.freedesktop.org/show_bug.cgi?id=108341
[fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
[fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
[fdo#108807]: https://bugs.freedesktop.org/show_bug.cgi?id=108807
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295
[fdo#109307]: https://bugs.freedesktop.org/show_bug.cgi?id=109307
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109507]: https://bugs.freedesktop.org/show_bug.cgi?id=109507
[fdo#109661]: https://bugs.freedesktop.org/show_bug.cgi?id=109661
[fdo#110403]: https://bugs.freedesktop.org/show_bug.cgi?id=110403
[fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-hsw
Build changes
-------------
* Linux: CI_DRM_5958 -> Patchwork_12844
CI_DRM_5958: dabbe59fd2bb5dca3d2607c49369161ec7160df3 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_4959: 504367d33b787de2ba8e007a5b620cfd6f0b3074 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
Patchwork_12844: 07ec1cc6ae6f4330a9e394632893e3418c7c211f @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_12844/
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx
^ permalink raw reply [flat|nested] 23+ messages in thread