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From: Jernej Skrabec <jernej.skrabec@siol.net>
To: maxime.ripard@bootlin.com, wens@csie.org
Cc: airlied@linux.ie, linux-kernel@vger.kernel.org,
	dri-devel@lists.freedesktop.org, linux-sunxi@googlegroups.com,
	stable@vger.kernel.org, daniel@ffwll.ch,
	linux-arm-kernel@lists.infradead.org
Subject: [PATCH 2/2] drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 MHz
Date: Tue, 14 May 2019 22:43:37 +0200	[thread overview]
Message-ID: <20190514204337.11068-3-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20190514204337.11068-1-jernej.skrabec@siol.net>

Vendor provided documentation says that EMP bits should be set to 3 for
pixel clocks greater than 148.5 MHz.

Fix that.

Cc: stable@vger.kernel.org # 4.17+
Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index afc6d4a9c20b..43643ad31730 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -293,7 +293,8 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
 				 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
 				 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
 		ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
-				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13);
+				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |
+				 SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);
 	}
 
 	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
-- 
2.21.0


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WARNING: multiple messages have this Message-ID (diff)
From: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
To: maxime.ripard-LDxbnhwyfcJBDgjK7y7TUQ@public.gmane.org,
	wens-jdAy2FN1RRM@public.gmane.org
Cc: airlied-cv59FeDIM0c@public.gmane.org,
	daniel-/w4YWyX8dFk@public.gmane.org,
	dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org,
	linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org,
	linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org,
	linux-sunxi-/JYPxA39Uh5TLH3MbocFFw@public.gmane.org,
	stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org
Subject: [PATCH 2/2] drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 MHz
Date: Tue, 14 May 2019 22:43:37 +0200	[thread overview]
Message-ID: <20190514204337.11068-3-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20190514204337.11068-1-jernej.skrabec-gGgVlfcn5nU@public.gmane.org>

Vendor provided documentation says that EMP bits should be set to 3 for
pixel clocks greater than 148.5 MHz.

Fix that.

Cc: stable-u79uwXL29TY76Z2rM5mHXA@public.gmane.org # 4.17+
Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant")
Signed-off-by: Jernej Skrabec <jernej.skrabec-gGgVlfcn5nU@public.gmane.org>
---
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index afc6d4a9c20b..43643ad31730 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -293,7 +293,8 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
 				 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
 				 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
 		ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
-				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13);
+				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |
+				 SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);
 	}
 
 	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
-- 
2.21.0

WARNING: multiple messages have this Message-ID (diff)
From: Jernej Skrabec <jernej.skrabec@siol.net>
To: maxime.ripard@bootlin.com, wens@csie.org
Cc: airlied@linux.ie, daniel@ffwll.ch,
	dri-devel@lists.freedesktop.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com,
	stable@vger.kernel.org
Subject: [PATCH 2/2] drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 MHz
Date: Tue, 14 May 2019 22:43:37 +0200	[thread overview]
Message-ID: <20190514204337.11068-3-jernej.skrabec@siol.net> (raw)
In-Reply-To: <20190514204337.11068-1-jernej.skrabec@siol.net>

Vendor provided documentation says that EMP bits should be set to 3 for
pixel clocks greater than 148.5 MHz.

Fix that.

Cc: stable@vger.kernel.org # 4.17+
Fixes: 4f86e81748fe ("drm/sun4i: Add support for H3 HDMI PHY variant")
Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
---
 drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
index afc6d4a9c20b..43643ad31730 100644
--- a/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
+++ b/drivers/gpu/drm/sun4i/sun8i_hdmi_phy.c
@@ -293,7 +293,8 @@ static int sun8i_hdmi_phy_config_h3(struct dw_hdmi *hdmi,
 				 SUN8I_HDMI_PHY_ANA_CFG2_REG_BIGSW |
 				 SUN8I_HDMI_PHY_ANA_CFG2_REG_SLV(4);
 		ana_cfg3_init |= SUN8I_HDMI_PHY_ANA_CFG3_REG_AMPCK(9) |
-				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13);
+				 SUN8I_HDMI_PHY_ANA_CFG3_REG_AMP(13) |
+				 SUN8I_HDMI_PHY_ANA_CFG3_REG_EMP(3);
 	}
 
 	regmap_update_bits(phy->regs, SUN8I_HDMI_PHY_ANA_CFG1_REG,
-- 
2.21.0


  parent reply	other threads:[~2019-05-14 20:44 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-05-14 20:43 [PATCH 0/2] drm/sun4i: Fix sun8i HDMI PHY initialization Jernej Skrabec
2019-05-14 20:43 ` Jernej Skrabec
2019-05-14 20:43 ` [PATCH 1/2] drm/sun4i: Fix sun8i HDMI PHY clock initialization Jernej Skrabec
2019-05-14 20:43   ` Jernej Skrabec
2019-05-14 20:43   ` Jernej Skrabec
2019-05-14 20:43 ` Jernej Skrabec [this message]
2019-05-14 20:43   ` [PATCH 2/2] drm/sun4i: Fix sun8i HDMI PHY configuration for > 148.5 MHz Jernej Skrabec
2019-05-14 20:43   ` Jernej Skrabec
2019-05-16  8:31 ` [PATCH 0/2] drm/sun4i: Fix sun8i HDMI PHY initialization Maxime Ripard
2019-05-16  8:31   ` Maxime Ripard
2019-05-16  8:31   ` Maxime Ripard

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