[Qemu-devel] [PATCH 0/2] Implement PowerPC FPSCR flag Fraction Rounded

[Qemu-devel] [PATCH 0/2] Implement PowerPC FPSCR flag Fraction Rounded

[John Arbuckle]

In IEEE 754 math, the arithmetic, rounding, and conversion instructions produce an intermediate result that can be regarded as having infinite precision and unbounded exponent range. When the final result has its fraction part incremented is when the Fraction Rounded bit is set.

This patch implements the PowerPC FPSCR flag Fraction Rounded.

Note: there are still functions in softfloat that need to be adjusted so that float_flag_rounded is fully supported. These include round_to_int(), and all legacy roundAndPack* functions. So basically anywhere that sets the float_flag_inexact.

John Arbuckle (2):
  Implement Floating Point flag Fraction Rounded
  Implement the PowerPC Floating Point Status and Control Register
    Fraction Rounded bit

 fpu/softfloat.c               | 15 ++++++++++++---
 include/fpu/softfloat-types.h |  1 +
 target/ppc/fpu_helper.c       |  4 ++++
 3 files changed, 17 insertions(+), 3 deletions(-)

-- 
2.14.3 (Apple Git-98)

[Qemu-devel] [PATCH 1/2] Implement Floating Point flag Fraction Rounded

[John Arbuckle]

Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
---
 fpu/softfloat.c               | 15 ++++++++++++---
 include/fpu/softfloat-types.h |  1 +
 2 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index 2ba36ec370..ac34f6a2de 100644
--- a/fpu/softfloat.c
+++ b/fpu/softfloat.c
@@ -702,7 +702,7 @@ static FloatParts round_canonical(FloatParts p, float_status *s,
     const uint64_t roundeven_mask = parm->roundeven_mask;
     const int exp_max = parm->exp_max;
     const int frac_shift = parm->frac_shift;
-    uint64_t frac, inc;
+    uint64_t frac, inc, rounded;
     int exp, flags = 0;
     bool overflow_norm;
 
@@ -744,7 +744,12 @@ static FloatParts round_canonical(FloatParts p, float_status *s,
         if (likely(exp > 0)) {
             if (frac & round_mask) {
                 flags |= float_flag_inexact;
-                frac += inc;
+                rounded = frac + inc;
+                if ((rounded ^ frac) & frac_lsb) {
+                    flags |= float_flag_rounded;
+                }
+                frac = rounded;
+
                 if (frac & DECOMPOSED_OVERFLOW_BIT) {
                     frac >>= 1;
                     exp++;
@@ -793,7 +798,11 @@ static FloatParts round_canonical(FloatParts p, float_status *s,
                     break;
                 }
                 flags |= float_flag_inexact;
-                frac += inc;
+                rounded = frac + inc;
+                if ((rounded ^ frac) & frac_lsb) {
+                    flags |= float_flag_rounded;
+                }
+                frac = rounded;
             }
 
             exp = (frac & DECOMPOSED_IMPLICIT_BIT ? 1 : 0);
diff --git a/include/fpu/softfloat-types.h b/include/fpu/softfloat-types.h
index 2aae6a89b1..bee576e0fd 100644
--- a/include/fpu/softfloat-types.h
+++ b/include/fpu/softfloat-types.h
@@ -147,6 +147,7 @@ enum {
 
 enum {
     float_flag_invalid   =  1,
+    float_flag_rounded   =  2,
     float_flag_divbyzero =  4,
     float_flag_overflow  =  8,
     float_flag_underflow = 16,
-- 
2.14.3 (Apple Git-98)

Re: [Qemu-devel] [PATCH 1/2] Implement Floating Point flag Fraction Rounded

[Richard Henderson]

On 5/24/19 7:20 PM, John Arbuckle wrote:
> Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
> ---
>  fpu/softfloat.c               | 15 ++++++++++++---
>  include/fpu/softfloat-types.h |  1 +
>  2 files changed, 13 insertions(+), 3 deletions(-)

There are additional places that need changing within this file, even if we
consider only float32 and float64 and ignore floatx80 and float128.

That said, merely renaming this patch to

  "softfloat: Implement float_flag_rounded in round_canonical

  Add a new flag to indicate that, when inexact, the result has
  been rounded.  That is, when the LSB of the rounded result
  differs from the same bit of the infinite precision result."

is enough to get

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

For your usage within PowerPC, you will additionally need to modify round_to_int.


r~

[Qemu-devel] [PATCH 2/2] Implement the PowerPC Floating Point Status and Control Register Fraction Rounded bit

[John Arbuckle]

Signed-off-by: John Arbuckle <programmingkidx@gmail.com>
---
 target/ppc/fpu_helper.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 0b7308f539..0baf1ce8e4 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -630,6 +630,10 @@ static void do_float_check_status(CPUPPCState *env, uintptr_t raddr)
         env->fpscr &= ~(1 << FPSCR_FI); /* clear the FPSCR[FI] bit */
     }
 
+    /* Set or clear the Fraction Rounded bit */
+    env->fpscr = deposit32(env->fpscr, FPSCR_FR, 1,
+                           (status & float_flag_rounded) != 0);
+
     if (cs->exception_index == POWERPC_EXCP_PROGRAM &&
         (env->error_code & POWERPC_EXCP_FP)) {
         /* Differred floating-point exception after target FPR update */
-- 
2.14.3 (Apple Git-98)