[PATCH 0/2] GuC messaging enable/disable tweaks

[PATCH 0/2] GuC messaging enable/disable tweaks

[Daniele Ceraolo Spurio]

Fix the order of operations and take care of late messages.
At the moment we only care about late messages if the log relay
is active, so the second patch is not essential. Since we now have
the ability of saving a bigger log with quite a bit of history, I'd
personally prefer to get rid of the relay logic entirely, but I'm
not sure if there is a good reason to keep it.

Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
 
Daniele Ceraolo Spurio (2):
  drm/i915/guc: reorder enable/disable communication steps
  drm/i915/guc: handle GuC messages received with CTB disabled

 drivers/gpu/drm/i915/intel_guc.h    |  5 ++
 drivers/gpu/drm/i915/intel_guc_ct.c | 15 +----
 drivers/gpu/drm/i915/intel_guc_ct.h |  4 ++
 drivers/gpu/drm/i915/intel_uc.c     | 90 ++++++++++++++++++++++++++++-
 4 files changed, 100 insertions(+), 14 deletions(-)

-- 
2.20.1

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[PATCH 1/2] drm/i915/guc: reorder enable/disable communication steps

[Daniele Ceraolo Spurio]

Make sure we always have CT buffers enabled when the interrupts are
enabled, so we can always handle interrupts from GuC. Also move the
setting of the guc->send and guc->handler functions to the GuC
communication control functions for consistency.

The reorder also fixes the onion unwinding of intel_uc_init_hw, because
guc_enable_communication would've left interrupts enabled when failing
to enable CTB.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110943
Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
---
 drivers/gpu/drm/i915/intel_guc_ct.c | 15 +++------------
 drivers/gpu/drm/i915/intel_guc_ct.h |  4 ++++
 drivers/gpu/drm/i915/intel_uc.c     | 19 ++++++++++++++++---
 3 files changed, 23 insertions(+), 15 deletions(-)

diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
index 3921809f812b..92eb40aadd9b 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.c
+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
@@ -529,8 +529,8 @@ static int ctch_send(struct intel_guc_ct *ct,
 /*
  * Command Transport (CT) buffer based GuC send function.
  */
-static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
-			     u32 *response_buf, u32 response_buf_size)
+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
+		      u32 *response_buf, u32 response_buf_size)
 {
 	struct intel_guc_ct *ct = &guc->ct;
 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
@@ -834,7 +834,7 @@ static void ct_process_host_channel(struct intel_guc_ct *ct)
  * When we're communicating with the GuC over CT, GuC uses events
  * to notify us about new messages being posted on the RECV buffer.
  */
-static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
 {
 	struct intel_guc_ct *ct = &guc->ct;
 
@@ -901,10 +901,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
 	if (unlikely(err))
 		return err;
 
-	/* Switch into cmd transport buffer based send() */
-	guc->send = intel_guc_send_ct;
-	guc->handler = intel_guc_to_host_event_handler_ct;
-	DRM_INFO("CT: %s\n", enableddisabled(true));
 	return 0;
 }
 
@@ -921,9 +917,4 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
 		return;
 
 	ctch_disable(guc, ctch);
-
-	/* Disable send */
-	guc->send = intel_guc_send_nop;
-	guc->handler = intel_guc_to_host_event_handler_nop;
-	DRM_INFO("CT: %s\n", enableddisabled(false));
 }
diff --git a/drivers/gpu/drm/i915/intel_guc_ct.h b/drivers/gpu/drm/i915/intel_guc_ct.h
index 41ba593a4df7..0ec17493d83b 100644
--- a/drivers/gpu/drm/i915/intel_guc_ct.h
+++ b/drivers/gpu/drm/i915/intel_guc_ct.h
@@ -101,4 +101,8 @@ static inline void intel_guc_ct_stop(struct intel_guc_ct *ct)
 	ct->host_channel.enabled = false;
 }
 
+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
+		      u32 *response_buf, u32 response_buf_size);
+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
+
 #endif /* _INTEL_GUC_CT_H_ */
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index ae45651ac73c..c7f82c944dd6 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -235,9 +235,20 @@ static void guc_disable_interrupts(struct intel_guc *guc)
 
 static int guc_enable_communication(struct intel_guc *guc)
 {
+	int ret;
+
+	ret = intel_guc_ct_enable(&guc->ct);
+	if (ret)
+		return ret;
+
+	guc->send = intel_guc_send_ct;
+	guc->handler = intel_guc_to_host_event_handler_ct;
+
 	guc_enable_interrupts(guc);
 
-	return intel_guc_ct_enable(&guc->ct);
+	DRM_INFO("GuC communication enabled\n");
+
+	return 0;
 }
 
 static void guc_stop_communication(struct intel_guc *guc)
@@ -250,12 +261,14 @@ static void guc_stop_communication(struct intel_guc *guc)
 
 static void guc_disable_communication(struct intel_guc *guc)
 {
-	intel_guc_ct_disable(&guc->ct);
-
 	guc_disable_interrupts(guc);
 
 	guc->send = intel_guc_send_nop;
 	guc->handler = intel_guc_to_host_event_handler_nop;
+
+	intel_guc_ct_disable(&guc->ct);
+
+	DRM_INFO("GuC communication disabled\n");
 }
 
 int intel_uc_init_misc(struct drm_i915_private *i915)
-- 
2.20.1

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[PATCH 2/2] drm/i915/guc: handle GuC messages received with CTB disabled

[Daniele Ceraolo Spurio]

There is a very small chance of triggering a log flush event when
enabling or disabling CT buffers. Events triggered while CT buffers
are disabled are logged in the SCRATCH_15 register using the same bits
used in the CT message payload. Since our communication channel with
GuC is turned off, we can save the message and handle it after we turn
it back on.
GuC should be idle and not generate more events in the meantime because
we're not talking to it.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
---
 drivers/gpu/drm/i915/intel_guc.h |  5 +++
 drivers/gpu/drm/i915/intel_uc.c  | 73 ++++++++++++++++++++++++++++++++
 2 files changed, 78 insertions(+)

diff --git a/drivers/gpu/drm/i915/intel_guc.h b/drivers/gpu/drm/i915/intel_guc.h
index 08c906abdfa2..d6a75bc3d7f4 100644
--- a/drivers/gpu/drm/i915/intel_guc.h
+++ b/drivers/gpu/drm/i915/intel_guc.h
@@ -88,6 +88,9 @@ struct intel_guc {
 		enum forcewake_domains fw_domains;
 	} send_regs;
 
+	/* Store msg (e.g. log flush) that we see while CTBs are disabled */
+	u32 mmio_msg;
+
 	/* To serialize the intel_guc_send actions */
 	struct mutex send_mutex;
 
@@ -181,6 +184,8 @@ static inline bool intel_guc_is_loaded(struct intel_guc *guc)
 static inline int intel_guc_sanitize(struct intel_guc *guc)
 {
 	intel_uc_fw_sanitize(&guc->fw);
+	guc->mmio_msg = 0;
+
 	return 0;
 }
 
diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
index c7f82c944dd6..38c87885aae3 100644
--- a/drivers/gpu/drm/i915/intel_uc.c
+++ b/drivers/gpu/drm/i915/intel_uc.c
@@ -218,6 +218,54 @@ static void guc_free_load_err_log(struct intel_guc *guc)
 		i915_gem_object_put(guc->load_err_log);
 }
 
+/*
+ * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
+ * register using the same bits used in the CT message payload. Since our
+ * communication channel with guc is turned off at this point, we can save the
+ * message and handle it after we turn it back on.
+ */
+static void guc_clear_mmio_msg(struct intel_guc *guc)
+{
+	intel_uncore_write(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15), 0);
+}
+
+static void guc_get_mmio_msg(struct intel_guc *guc)
+{
+	u32 val;
+
+	spin_lock_irq(&guc->irq_lock);
+
+	val = intel_uncore_read(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15));
+	guc->mmio_msg |= val & guc->msg_enabled_mask;
+
+	/*
+	 * clear all events, including the ones we're not currently servicing,
+	 * to make sure we don't try to process a stale message if we enable
+	 * handling of more events later.
+	 */
+	guc_clear_mmio_msg(guc);
+
+	spin_unlock_irq(&guc->irq_lock);
+}
+
+static void guc_handle_mmio_msg(struct intel_guc *guc)
+{
+	struct drm_i915_private *i915 = guc_to_i915(guc);
+
+	/* we need communication to be enabled to reply to GuC */
+	GEM_BUG_ON(guc->handler == intel_guc_to_host_event_handler_nop);
+
+	if (!guc->mmio_msg)
+		return;
+
+	spin_lock_irq(&i915->irq_lock);
+	intel_guc_to_host_process_recv_msg(guc, &guc->mmio_msg, 1);
+	spin_unlock_irq(&i915->irq_lock);
+
+	guc->mmio_msg = 0;
+}
+
+
 static void guc_reset_interrupts(struct intel_guc *guc)
 {
 	guc->interrupts.reset(guc_to_i915(guc));
@@ -235,6 +283,7 @@ static void guc_disable_interrupts(struct intel_guc *guc)
 
 static int guc_enable_communication(struct intel_guc *guc)
 {
+	struct drm_i915_private *i915 = guc_to_i915(guc);
 	int ret;
 
 	ret = intel_guc_ct_enable(&guc->ct);
@@ -244,8 +293,17 @@ static int guc_enable_communication(struct intel_guc *guc)
 	guc->send = intel_guc_send_ct;
 	guc->handler = intel_guc_to_host_event_handler_ct;
 
+	/* check for mmio messages received before/during the CT enable */
+	guc_get_mmio_msg(guc);
+	guc_handle_mmio_msg(guc);
+
 	guc_enable_interrupts(guc);
 
+	/* check for CT messages received before we enabled interrupts */
+	spin_lock_irq(&i915->irq_lock);
+	intel_guc_to_host_event_handler_ct(guc);
+	spin_unlock_irq(&i915->irq_lock);
+
 	DRM_INFO("GuC communication enabled\n");
 
 	return 0;
@@ -261,6 +319,13 @@ static void guc_stop_communication(struct intel_guc *guc)
 
 static void guc_disable_communication(struct intel_guc *guc)
 {
+	/*
+	 * Events generated during or after CT disable are logged by guc in
+	 * via mmio. Make sure the register is clear before disabling CT since
+	 * all events we cared about have already been processed via CT.
+	 */
+	guc_clear_mmio_msg(guc);
+
 	guc_disable_interrupts(guc);
 
 	guc->send = intel_guc_send_nop;
@@ -268,6 +333,14 @@ static void guc_disable_communication(struct intel_guc *guc)
 
 	intel_guc_ct_disable(&guc->ct);
 
+	/*
+	 * Check for messages received during/after the CT disable. We do not
+	 * expect any messages to have arrived via CT between the interrupt
+	 * disable and the CT disable because GuC should've been idle until we
+	 * triggered the CT disable protocol.
+	 */
+	guc_get_mmio_msg(guc);
+
 	DRM_INFO("GuC communication disabled\n");
 }
 
-- 
2.20.1

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✗ Fi.CI.CHECKPATCH: warning for GuC messaging enable/disable tweaks

[Patchwork]

== Series Details ==

Series: GuC messaging enable/disable tweaks
URL   : https://patchwork.freedesktop.org/series/62412/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
b1e56a188163 drm/i915/guc: reorder enable/disable communication steps
99d49d7e5f42 drm/i915/guc: handle GuC messages received with CTB disabled
-:97: CHECK:LINE_SPACING: Please don't use multiple blank lines
#97: FILE: drivers/gpu/drm/i915/intel_uc.c:268:
+
+

total: 0 errors, 0 warnings, 1 checks, 122 lines checked

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Re: [PATCH 1/2] drm/i915/guc: reorder enable/disable communication steps

[Matthew Brost]

On Wed, Jun 19, 2019 at 02:43:50PM -0700, Daniele Ceraolo Spurio wrote:
>Make sure we always have CT buffers enabled when the interrupts are
>enabled, so we can always handle interrupts from GuC. Also move the
>setting of the guc->send and guc->handler functions to the GuC
>communication control functions for consistency.
>
>The reorder also fixes the onion unwinding of intel_uc_init_hw, because
>guc_enable_communication would've left interrupts enabled when failing
>to enable CTB.
>
>Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110943
>Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
>Cc: Chris Wilson <chris@chris-wilson.co.uk>
>Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>
>---

Reviewed-by: Matthew Brost

> drivers/gpu/drm/i915/intel_guc_ct.c | 15 +++------------
> drivers/gpu/drm/i915/intel_guc_ct.h |  4 ++++
> drivers/gpu/drm/i915/intel_uc.c     | 19 ++++++++++++++++---
> 3 files changed, 23 insertions(+), 15 deletions(-)
>
>diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c b/drivers/gpu/drm/i915/intel_guc_ct.c
>index 3921809f812b..92eb40aadd9b 100644
>--- a/drivers/gpu/drm/i915/intel_guc_ct.c
>+++ b/drivers/gpu/drm/i915/intel_guc_ct.c
>@@ -529,8 +529,8 @@ static int ctch_send(struct intel_guc_ct *ct,
> /*
>  * Command Transport (CT) buffer based GuC send function.
>  */
>-static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
>-			     u32 *response_buf, u32 response_buf_size)
>+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
>+		      u32 *response_buf, u32 response_buf_size)
> {
> 	struct intel_guc_ct *ct = &guc->ct;
> 	struct intel_guc_ct_channel *ctch = &ct->host_channel;
>@@ -834,7 +834,7 @@ static void ct_process_host_channel(struct intel_guc_ct *ct)
>  * When we're communicating with the GuC over CT, GuC uses events
>  * to notify us about new messages being posted on the RECV buffer.
>  */
>-static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
>+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
> {
> 	struct intel_guc_ct *ct = &guc->ct;
>
>@@ -901,10 +901,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
> 	if (unlikely(err))
> 		return err;
>
>-	/* Switch into cmd transport buffer based send() */
>-	guc->send = intel_guc_send_ct;
>-	guc->handler = intel_guc_to_host_event_handler_ct;
>-	DRM_INFO("CT: %s\n", enableddisabled(true));
> 	return 0;
> }
>
>@@ -921,9 +917,4 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
> 		return;
>
> 	ctch_disable(guc, ctch);
>-
>-	/* Disable send */
>-	guc->send = intel_guc_send_nop;
>-	guc->handler = intel_guc_to_host_event_handler_nop;
>-	DRM_INFO("CT: %s\n", enableddisabled(false));
> }
>diff --git a/drivers/gpu/drm/i915/intel_guc_ct.h b/drivers/gpu/drm/i915/intel_guc_ct.h
>index 41ba593a4df7..0ec17493d83b 100644
>--- a/drivers/gpu/drm/i915/intel_guc_ct.h
>+++ b/drivers/gpu/drm/i915/intel_guc_ct.h
>@@ -101,4 +101,8 @@ static inline void intel_guc_ct_stop(struct intel_guc_ct *ct)
> 	ct->host_channel.enabled = false;
> }
>
>+int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
>+		      u32 *response_buf, u32 response_buf_size);
>+void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
>+
> #endif /* _INTEL_GUC_CT_H_ */
>diff --git a/drivers/gpu/drm/i915/intel_uc.c b/drivers/gpu/drm/i915/intel_uc.c
>index ae45651ac73c..c7f82c944dd6 100644
>--- a/drivers/gpu/drm/i915/intel_uc.c
>+++ b/drivers/gpu/drm/i915/intel_uc.c
>@@ -235,9 +235,20 @@ static void guc_disable_interrupts(struct intel_guc *guc)
>
> static int guc_enable_communication(struct intel_guc *guc)
> {
>+	int ret;
>+
>+	ret = intel_guc_ct_enable(&guc->ct);
>+	if (ret)
>+		return ret;
>+
>+	guc->send = intel_guc_send_ct;
>+	guc->handler = intel_guc_to_host_event_handler_ct;
>+
> 	guc_enable_interrupts(guc);
>
>-	return intel_guc_ct_enable(&guc->ct);
>+	DRM_INFO("GuC communication enabled\n");
>+
>+	return 0;
> }
>
> static void guc_stop_communication(struct intel_guc *guc)
>@@ -250,12 +261,14 @@ static void guc_stop_communication(struct intel_guc *guc)
>
> static void guc_disable_communication(struct intel_guc *guc)
> {
>-	intel_guc_ct_disable(&guc->ct);
>-
> 	guc_disable_interrupts(guc);
>
> 	guc->send = intel_guc_send_nop;
> 	guc->handler = intel_guc_to_host_event_handler_nop;
>+
>+	intel_guc_ct_disable(&guc->ct);
>+
>+	DRM_INFO("GuC communication disabled\n");
> }
>
> int intel_uc_init_misc(struct drm_i915_private *i915)
>-- 
>2.20.1
>
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✓ Fi.CI.BAT: success for GuC messaging enable/disable tweaks

[Patchwork]

== Series Details ==

Series: GuC messaging enable/disable tweaks
URL   : https://patchwork.freedesktop.org/series/62412/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6312 -> Patchwork_13354
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/

Known issues
------------

  Here are the changes found in Patchwork_13354 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_module_load@reload:
    - fi-icl-u3:          [PASS][1] -> [DMESG-WARN][2] ([fdo#107724])
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-icl-u3/igt@i915_module_load@reload.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/fi-icl-u3/igt@i915_module_load@reload.html

  
#### Possible fixes ####

  * igt@gem_exec_suspend@basic-s3:
    - fi-blb-e6850:       [INCOMPLETE][3] ([fdo#107718]) -> [PASS][4]
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/fi-blb-e6850/igt@gem_exec_suspend@basic-s3.html

  * igt@i915_selftest@live_contexts:
    - fi-skl-gvtdvm:      [DMESG-FAIL][5] ([fdo#110235]) -> [PASS][6]
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/fi-skl-gvtdvm/igt@i915_selftest@live_contexts.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][7] ([fdo#109485]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  * igt@kms_frontbuffer_tracking@basic:
    - fi-icl-u3:          [FAIL][9] ([fdo#103167]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/fi-icl-u3/igt@kms_frontbuffer_tracking@basic.html
    - fi-icl-u2:          [FAIL][11] ([fdo#103167]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/fi-icl-u2/igt@kms_frontbuffer_tracking@basic.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#107718]: https://bugs.freedesktop.org/show_bug.cgi?id=107718
  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#109485]: https://bugs.freedesktop.org/show_bug.cgi?id=109485
  [fdo#110235]: https://bugs.freedesktop.org/show_bug.cgi?id=110235


Participating hosts (49 -> 43)
------------------------------

  Additional (4): fi-cml-u2 fi-bxt-j4205 fi-gdg-551 fi-cml-u 
  Missing    (10): fi-kbl-soraka fi-ilk-m540 fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-icl-y fi-icl-guc fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * Linux: CI_DRM_6312 -> Patchwork_13354

  CI_DRM_6312: 034e3ac6a2d180d188da927388b60c7e62c5655b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5061: c88ced79a7b71aec58f1d9c5c599ac2f431bcf7a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13354: 99d49d7e5f42e6cfdc78d74d7006705ab044bcb5 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

99d49d7e5f42 drm/i915/guc: handle GuC messages received with CTB disabled
b1e56a188163 drm/i915/guc: reorder enable/disable communication steps

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/
_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

Re: [PATCH 1/2] drm/i915/guc: reorder enable/disable communication steps

[Michal Wajdeczko]

On Wed, 19 Jun 2019 23:43:50 +0200, Daniele Ceraolo Spurio  
<daniele.ceraolospurio@intel.com> wrote:

> Make sure we always have CT buffers enabled when the interrupts are
> enabled, so we can always handle interrupts from GuC. Also move the
> setting of the guc->send and guc->handler functions to the GuC
> communication control functions for consistency.
>
> The reorder also fixes the onion unwinding of intel_uc_init_hw, because
> guc_enable_communication would've left interrupts enabled when failing
> to enable CTB.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110943
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com>

Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com>

with some nit below

> ---
>  drivers/gpu/drm/i915/intel_guc_ct.c | 15 +++------------
>  drivers/gpu/drm/i915/intel_guc_ct.h |  4 ++++
>  drivers/gpu/drm/i915/intel_uc.c     | 19 ++++++++++++++++---
>  3 files changed, 23 insertions(+), 15 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/intel_guc_ct.c  
> b/drivers/gpu/drm/i915/intel_guc_ct.c
> index 3921809f812b..92eb40aadd9b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ct.c
> +++ b/drivers/gpu/drm/i915/intel_guc_ct.c
> @@ -529,8 +529,8 @@ static int ctch_send(struct intel_guc_ct *ct,
>  /*
>   * Command Transport (CT) buffer based GuC send function.
>   */
> -static int intel_guc_send_ct(struct intel_guc *guc, const u32 *action,  
> u32 len,
> -			     u32 *response_buf, u32 response_buf_size)
> +int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
> +		      u32 *response_buf, u32 response_buf_size)
>  {
>  	struct intel_guc_ct *ct = &guc->ct;
>  	struct intel_guc_ct_channel *ctch = &ct->host_channel;
> @@ -834,7 +834,7 @@ static void ct_process_host_channel(struct  
> intel_guc_ct *ct)
>   * When we're communicating with the GuC over CT, GuC uses events
>   * to notify us about new messages being posted on the RECV buffer.
>   */
> -static void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
> +void intel_guc_to_host_event_handler_ct(struct intel_guc *guc)
>  {
>  	struct intel_guc_ct *ct = &guc->ct;
> @@ -901,10 +901,6 @@ int intel_guc_ct_enable(struct intel_guc_ct *ct)
>  	if (unlikely(err))
>  		return err;

now you can drop above early return and always return err;

> -	/* Switch into cmd transport buffer based send() */
> -	guc->send = intel_guc_send_ct;
> -	guc->handler = intel_guc_to_host_event_handler_ct;
> -	DRM_INFO("CT: %s\n", enableddisabled(true));
>  	return 0;
>  }
> @@ -921,9 +917,4 @@ void intel_guc_ct_disable(struct intel_guc_ct *ct)
>  		return;
> 	ctch_disable(guc, ctch);
> -
> -	/* Disable send */
> -	guc->send = intel_guc_send_nop;
> -	guc->handler = intel_guc_to_host_event_handler_nop;
> -	DRM_INFO("CT: %s\n", enableddisabled(false));
>  }
> diff --git a/drivers/gpu/drm/i915/intel_guc_ct.h  
> b/drivers/gpu/drm/i915/intel_guc_ct.h
> index 41ba593a4df7..0ec17493d83b 100644
> --- a/drivers/gpu/drm/i915/intel_guc_ct.h
> +++ b/drivers/gpu/drm/i915/intel_guc_ct.h
> @@ -101,4 +101,8 @@ static inline void intel_guc_ct_stop(struct  
> intel_guc_ct *ct)
>  	ct->host_channel.enabled = false;
>  }
> +int intel_guc_send_ct(struct intel_guc *guc, const u32 *action, u32 len,
> +		      u32 *response_buf, u32 response_buf_size);
> +void intel_guc_to_host_event_handler_ct(struct intel_guc *guc);
> +
>  #endif /* _INTEL_GUC_CT_H_ */
> diff --git a/drivers/gpu/drm/i915/intel_uc.c  
> b/drivers/gpu/drm/i915/intel_uc.c
> index ae45651ac73c..c7f82c944dd6 100644
> --- a/drivers/gpu/drm/i915/intel_uc.c
> +++ b/drivers/gpu/drm/i915/intel_uc.c
> @@ -235,9 +235,20 @@ static void guc_disable_interrupts(struct intel_guc  
> *guc)
> static int guc_enable_communication(struct intel_guc *guc)
>  {
> +	int ret;
> +
> +	ret = intel_guc_ct_enable(&guc->ct);
> +	if (ret)
> +		return ret;
> +
> +	guc->send = intel_guc_send_ct;
> +	guc->handler = intel_guc_to_host_event_handler_ct;
> +
>  	guc_enable_interrupts(guc);
> -	return intel_guc_ct_enable(&guc->ct);
> +	DRM_INFO("GuC communication enabled\n");
> +
> +	return 0;
>  }
> static void guc_stop_communication(struct intel_guc *guc)
> @@ -250,12 +261,14 @@ static void guc_stop_communication(struct  
> intel_guc *guc)
> static void guc_disable_communication(struct intel_guc *guc)
>  {
> -	intel_guc_ct_disable(&guc->ct);
> -
>  	guc_disable_interrupts(guc);
> 	guc->send = intel_guc_send_nop;
>  	guc->handler = intel_guc_to_host_event_handler_nop;
> +
> +	intel_guc_ct_disable(&guc->ct);
> +
> +	DRM_INFO("GuC communication disabled\n");
>  }
> int intel_uc_init_misc(struct drm_i915_private *i915)
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Re: [PATCH 2/2] drm/i915/guc: handle GuC messages received with CTB disabled

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2019-06-19 22:43:51)
> +/*
> + * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
> + * register using the same bits used in the CT message payload. Since our
> + * communication channel with guc is turned off at this point, we can save the
> + * message and handle it after we turn it back on.
> + */
> +static void guc_clear_mmio_msg(struct intel_guc *guc)
> +{
> +       intel_uncore_write(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15), 0);

Should the register be cleared on intel_guc_reset()? Otherwise, we would
be associating the stale msg from an earlier guc instance with the
current one.

That would mean clear_mmio_msg would want to be called from
guc_stop_communication not just guc_disable_communication.
-Chris
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✓ Fi.CI.IGT: success for GuC messaging enable/disable tweaks

[Patchwork]

== Series Details ==

Series: GuC messaging enable/disable tweaks
URL   : https://patchwork.freedesktop.org/series/62412/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_6312_full -> Patchwork_13354_full
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  

Known issues
------------

  Here are the changes found in Patchwork_13354_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_eio@in-flight-suspend:
    - shard-kbl:          [PASS][1] -> [DMESG-WARN][2] ([fdo#110913 ]) +2 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-kbl3/igt@gem_eio@in-flight-suspend.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-kbl3/igt@gem_eio@in-flight-suspend.html

  * igt@gem_persistent_relocs@forked-faulting-reloc-thrashing:
    - shard-snb:          [PASS][3] -> [DMESG-WARN][4] ([fdo#110789] / [fdo#110913 ])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-snb6/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-snb4/igt@gem_persistent_relocs@forked-faulting-reloc-thrashing.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [PASS][5] -> [INCOMPLETE][6] ([fdo#104108] / [fdo#107773])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-skl6/igt@gem_softpin@noreloc-s3.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-skl5/igt@gem_softpin@noreloc-s3.html

  * igt@gem_tiled_swapping@non-threaded:
    - shard-apl:          [PASS][7] -> [DMESG-WARN][8] ([fdo#108686])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-apl8/igt@gem_tiled_swapping@non-threaded.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-apl6/igt@gem_tiled_swapping@non-threaded.html

  * igt@i915_pm_rc6_residency@rc6-accuracy:
    - shard-snb:          [PASS][9] -> [SKIP][10] ([fdo#109271])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-snb1/igt@i915_pm_rc6_residency@rc6-accuracy.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-snb2/igt@i915_pm_rc6_residency@rc6-accuracy.html

  * igt@i915_suspend@debugfs-reader:
    - shard-apl:          [PASS][11] -> [DMESG-WARN][12] ([fdo#108566]) +3 similar issues
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-apl2/igt@i915_suspend@debugfs-reader.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-apl6/igt@i915_suspend@debugfs-reader.html

  * igt@i915_suspend@sysfs-reader:
    - shard-kbl:          [PASS][13] -> [INCOMPLETE][14] ([fdo#103665] / [fdo#108767])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-kbl4/igt@i915_suspend@sysfs-reader.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-kbl4/igt@i915_suspend@sysfs-reader.html

  * igt@kms_frontbuffer_tracking@fbc-2p-rte:
    - shard-hsw:          [PASS][15] -> [SKIP][16] ([fdo#109271]) +26 similar issues
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-hsw8/igt@kms_frontbuffer_tracking@fbc-2p-rte.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-rte.html

  * igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt:
    - shard-skl:          [PASS][17] -> [FAIL][18] ([fdo#103167])
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-skl7/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-skl2/igt@kms_frontbuffer_tracking@fbcpsr-1p-offscren-pri-indfb-draw-mmap-gtt.html

  * igt@kms_pipe_crc_basic@hang-read-crc-pipe-c:
    - shard-skl:          [PASS][19] -> [FAIL][20] ([fdo#103191])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-skl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-c.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-skl6/igt@kms_pipe_crc_basic@hang-read-crc-pipe-c.html

  * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes:
    - shard-kbl:          [PASS][21] -> [INCOMPLETE][22] ([fdo#103665])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-a-planes.html

  * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min:
    - shard-skl:          [PASS][23] -> [FAIL][24] ([fdo#108145]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-skl3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-skl6/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html

  * igt@kms_setmode@basic:
    - shard-apl:          [PASS][25] -> [FAIL][26] ([fdo#99912])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-apl6/igt@kms_setmode@basic.html
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-apl1/igt@kms_setmode@basic.html

  
#### Possible fixes ####

  * igt@gem_persistent_relocs@forked-interruptible-thrashing:
    - shard-snb:          [DMESG-WARN][27] ([fdo#110789] / [fdo#110913 ]) -> [PASS][28]
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-snb4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-snb5/igt@gem_persistent_relocs@forked-interruptible-thrashing.html

  * igt@gem_persistent_relocs@forked-thrashing:
    - shard-apl:          [DMESG-WARN][29] ([fdo#110913 ]) -> [PASS][30]
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-apl5/igt@gem_persistent_relocs@forked-thrashing.html
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-apl4/igt@gem_persistent_relocs@forked-thrashing.html

  * igt@gem_userptr_blits@map-fixed-invalidate-busy-gup:
    - shard-kbl:          [DMESG-WARN][31] ([fdo#110913 ]) -> [PASS][32] +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-kbl4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-kbl4/igt@gem_userptr_blits@map-fixed-invalidate-busy-gup.html

  * igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge:
    - shard-snb:          [SKIP][33] ([fdo#109271] / [fdo#109278]) -> [PASS][34]
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-snb2/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-snb2/igt@kms_cursor_edge_walk@pipe-b-128x128-top-edge.html

  * igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic:
    - shard-glk:          [FAIL][35] ([fdo#104873]) -> [PASS][36]
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-glk8/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-atomic.html

  * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite:
    - shard-hsw:          [SKIP][37] ([fdo#109271]) -> [PASS][38] +24 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-hsw1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-hsw7/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@fbc-suspend:
    - shard-apl:          [DMESG-WARN][39] ([fdo#108566]) -> [PASS][40]
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-apl3/igt@kms_frontbuffer_tracking@fbc-suspend.html
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-apl4/igt@kms_frontbuffer_tracking@fbc-suspend.html

  * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c:
    - shard-skl:          [INCOMPLETE][41] ([fdo#104108]) -> [PASS][42]
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-skl4/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-skl10/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-c.html

  * igt@kms_plane@plane-panning-bottom-right-pipe-b-planes:
    - shard-snb:          [SKIP][43] ([fdo#109271]) -> [PASS][44] +1 similar issue
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-snb2/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-snb2/igt@kms_plane@plane-panning-bottom-right-pipe-b-planes.html

  * igt@kms_setmode@basic:
    - shard-hsw:          [FAIL][45] ([fdo#99912]) -> [PASS][46]
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_6312/shard-hsw7/igt@kms_setmode@basic.html
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/shard-hsw1/igt@kms_setmode@basic.html

  
  [fdo#103167]: https://bugs.freedesktop.org/show_bug.cgi?id=103167
  [fdo#103191]: https://bugs.freedesktop.org/show_bug.cgi?id=103191
  [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665
  [fdo#104108]: https://bugs.freedesktop.org/show_bug.cgi?id=104108
  [fdo#104873]: https://bugs.freedesktop.org/show_bug.cgi?id=104873
  [fdo#107773]: https://bugs.freedesktop.org/show_bug.cgi?id=107773
  [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
  [fdo#108566]: https://bugs.freedesktop.org/show_bug.cgi?id=108566
  [fdo#108686]: https://bugs.freedesktop.org/show_bug.cgi?id=108686
  [fdo#108767]: https://bugs.freedesktop.org/show_bug.cgi?id=108767
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
  [fdo#110789]: https://bugs.freedesktop.org/show_bug.cgi?id=110789
  [fdo#110913 ]: https://bugs.freedesktop.org/show_bug.cgi?id=110913 
  [fdo#99912]: https://bugs.freedesktop.org/show_bug.cgi?id=99912


Participating hosts (10 -> 9)
------------------------------

  Missing    (1): shard-iclb 


Build changes
-------------

  * Linux: CI_DRM_6312 -> Patchwork_13354

  CI_DRM_6312: 034e3ac6a2d180d188da927388b60c7e62c5655b @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5061: c88ced79a7b71aec58f1d9c5c599ac2f431bcf7a @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_13354: 99d49d7e5f42e6cfdc78d74d7006705ab044bcb5 @ git://anongit.freedesktop.org/gfx-ci/linux
  piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_13354/
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Re: [PATCH 2/2] drm/i915/guc: handle GuC messages received with CTB disabled

[Daniele Ceraolo Spurio]

On 6/20/19 6:48 AM, Chris Wilson wrote:
> Quoting Daniele Ceraolo Spurio (2019-06-19 22:43:51)
>> +/*
>> + * Events triggered while CT buffers are disabled are logged in the SCRATCH_15
>> + * register using the same bits used in the CT message payload. Since our
>> + * communication channel with guc is turned off at this point, we can save the
>> + * message and handle it after we turn it back on.
>> + */
>> +static void guc_clear_mmio_msg(struct intel_guc *guc)
>> +{
>> +       intel_uncore_write(&guc_to_i915(guc)->uncore, SOFT_SCRATCH(15), 0);
> 
> Should the register be cleared on intel_guc_reset()? Otherwise, we would
> be associating the stale msg from an earlier guc instance with the
> current one.
> 
> That would mean clear_mmio_msg would want to be called from
> guc_stop_communication not just guc_disable_communication.
> -Chris
> 

The register is reset by the HW as part of GuC reset (I've verified this 
on SKL). Still, explicitly clearing it won't hurt and it'll cover us if 
HW reset fails, so no problem in adding the call in.

Daniele
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