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From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>, <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>
Cc: <kishon@ti.com>, <gustavo.pimentel@synopsys.com>,
	<digetx@gmail.com>, <mperttunen@nvidia.com>,
	<linux-pci@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-tegra@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>, <kthota@nvidia.com>,
	<mmaddireddy@nvidia.com>, <vidyas@nvidia.com>,
	<sagar.tv@gmail.com>
Subject: [PATCH 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries
Date: Mon, 26 Aug 2019 13:01:38 +0530	[thread overview]
Message-ID: <20190826073143.4582-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com>

Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin
configuration information of a particular PCIe controller.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt      | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
index 674e5adb2895..0ac1b867ac24 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
@@ -83,6 +83,11 @@ Required properties:
 - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
 
 Optional properties:
+- pinctrl-names: A list of pinctrl state names.
+  It is mandatory for C5 controller and optional for other controllers.
+  - "default": Configures PCIe I/O for proper operation.
+- pinctrl-0: phandle for the 'default' state of pin configuration.
+  It is mandatory for C5 controller and optional for other controllers.
 - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
 - nvidia,update-fc-fixup: This is a boolean property and needs to be present to
     improve performance when a platform is designed in such a way that it
@@ -120,6 +125,9 @@ Tegra194:
 		num-lanes = <8>;
 		linux,pci-domain = <0>;
 
+		pinctrl-names = "default";
+		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
 		clock-names = "core";
 
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
	robh+dt@kernel.org, thierry.reding@gmail.com,
	jonathanh@nvidia.com
Cc: kishon@ti.com, gustavo.pimentel@synopsys.com, digetx@gmail.com,
	mperttunen@nvidia.com, linux-pci@vger.kernel.org,
	devicetree@vger.kernel.org, linux-tegra@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
	mmaddireddy@nvidia.com, vidyas@nvidia.com, sagar.tv@gmail.com
Subject: [PATCH 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries
Date: Mon, 26 Aug 2019 13:01:38 +0530	[thread overview]
Message-ID: <20190826073143.4582-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com>

Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin
configuration information of a particular PCIe controller.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt      | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
index 674e5adb2895..0ac1b867ac24 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
@@ -83,6 +83,11 @@ Required properties:
 - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
 
 Optional properties:
+- pinctrl-names: A list of pinctrl state names.
+  It is mandatory for C5 controller and optional for other controllers.
+  - "default": Configures PCIe I/O for proper operation.
+- pinctrl-0: phandle for the 'default' state of pin configuration.
+  It is mandatory for C5 controller and optional for other controllers.
 - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
 - nvidia,update-fc-fixup: This is a boolean property and needs to be present to
     improve performance when a platform is designed in such a way that it
@@ -120,6 +125,9 @@ Tegra194:
 		num-lanes = <8>;
 		linux,pci-domain = <0>;
 
+		pinctrl-names = "default";
+		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
 		clock-names = "core";
 
-- 
2.17.1

WARNING: multiple messages have this Message-ID (diff)
From: Vidya Sagar <vidyas@nvidia.com>
To: <lorenzo.pieralisi@arm.com>, <bhelgaas@google.com>,
	<robh+dt@kernel.org>,  <thierry.reding@gmail.com>,
	<jonathanh@nvidia.com>
Cc: devicetree@vger.kernel.org, mmaddireddy@nvidia.com,
	kthota@nvidia.com, gustavo.pimentel@synopsys.com,
	vidyas@nvidia.com, linux-kernel@vger.kernel.org,
	mperttunen@nvidia.com, linux-pci@vger.kernel.org,
	linux-tegra@vger.kernel.org, digetx@gmail.com, kishon@ti.com,
	linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: [PATCH 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries
Date: Mon, 26 Aug 2019 13:01:38 +0530	[thread overview]
Message-ID: <20190826073143.4582-2-vidyas@nvidia.com> (raw)
In-Reply-To: <20190826073143.4582-1-vidyas@nvidia.com>

Add optional bindings "pinctrl-names" and "pinctrl-0" to describe pin
configuration information of a particular PCIe controller.

Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
---
 .../devicetree/bindings/pci/nvidia,tegra194-pcie.txt      | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
index 674e5adb2895..0ac1b867ac24 100644
--- a/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
+++ b/Documentation/devicetree/bindings/pci/nvidia,tegra194-pcie.txt
@@ -83,6 +83,11 @@ Required properties:
 - vddio-pex-ctl-supply: Regulator supply for PCIe side band signals
 
 Optional properties:
+- pinctrl-names: A list of pinctrl state names.
+  It is mandatory for C5 controller and optional for other controllers.
+  - "default": Configures PCIe I/O for proper operation.
+- pinctrl-0: phandle for the 'default' state of pin configuration.
+  It is mandatory for C5 controller and optional for other controllers.
 - supports-clkreq: Refer to Documentation/devicetree/bindings/pci/pci.txt
 - nvidia,update-fc-fixup: This is a boolean property and needs to be present to
     improve performance when a platform is designed in such a way that it
@@ -120,6 +125,9 @@ Tegra194:
 		num-lanes = <8>;
 		linux,pci-domain = <0>;
 
+		pinctrl-names = "default";
+		pinctrl-0 = <&pex_rst_c5_out_state>, <&clkreq_c5_bi_dir_state>;
+
 		clocks = <&bpmp TEGRA194_CLK_PEX0_CORE_0>;
 		clock-names = "core";
 
-- 
2.17.1


_______________________________________________
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linux-arm-kernel@lists.infradead.org
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  reply	other threads:[~2019-08-26  7:31 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-08-26  7:31 [PATCH 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Vidya Sagar
2019-08-26  7:31 ` Vidya Sagar
2019-08-26  7:31 ` Vidya Sagar
2019-08-26  7:31 ` Vidya Sagar [this message]
2019-08-26  7:31   ` [PATCH 1/6] dt-bindings: PCI: tegra: Add sideband pins configuration entries Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31 ` [PATCH 2/6] arm64: tegra: Add configuration for PCIe C5 sideband signals Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31 ` [PATCH 3/6] PCI: tegra: Add support to configure sideband pins Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-27 15:30   ` Andrew Murray
2019-08-27 15:30     ` Andrew Murray
2019-08-27 15:40     ` Vidya Sagar
2019-08-27 15:40       ` Vidya Sagar
2019-08-27 15:40       ` Vidya Sagar
2019-08-26  7:31 ` [PATCH 4/6] dt-bindings: PCI: tegra: Add PCIe slot supplies regulator entries Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31 ` [PATCH 5/6] arm64: tegra: Add PCIe slot supply information in p2972-0000 platform Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31 ` [PATCH 6/6] PCI: tegra: Add support to enable slot regulators Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-26  7:31   ` Vidya Sagar
2019-08-27 15:47   ` Andrew Murray
2019-08-27 15:47     ` Andrew Murray
2019-08-27 16:24     ` Vidya Sagar
2019-08-27 16:24       ` Vidya Sagar
2019-08-27 16:24       ` Vidya Sagar
2019-08-27 17:13       ` Andrew Murray
2019-08-27 17:13         ` Andrew Murray
2019-08-28  9:07         ` Thierry Reding
2019-08-28  9:07           ` Thierry Reding
2019-08-28  9:37           ` Andrew Murray
2019-08-28  9:37             ` Andrew Murray
2019-08-28  9:10 ` [PATCH 0/6] PCI: tegra: Enable PCIe C5 controller of Tegra194 in p2972-0000 platform Thierry Reding
2019-08-28  9:10   ` Thierry Reding
2019-08-28 10:04   ` Vidya Sagar
2019-08-28 10:04     ` Vidya Sagar
2019-08-28 10:04     ` Vidya Sagar

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