Does sfence.vma implicitly cover what fence.i does?

Does sfence.vma implicitly cover what fence.i does?

[Alan Kao]

Hi Paul, Palmer,

In arch/riscv/include/asm/tlbflush.h, the comment says

> Flush entire local TLB.  'sfence.vma' implicitly fences with the instruction
> cache as well, so a 'fence.i' is not necessary.

and in the privileged spec, it is stated that

> Executing an SFENCE.VMA instruction guarantees that any previous stores
> already visible to the current RISC-V hart are ordered before all subsequent
> implicit references from that hart to the memory-management data structures.

So my question is straightforward.  Is I-cache a kind of memory-management data
structure?  am I missing something here?

Thanks for any clarification.

Alan

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Re: Does sfence.vma implicitly cover what fence.i does?

[Paul Walmsley]

Hi Alan,

On Wed, 9 Oct 2019, Alan Kao wrote:

> In arch/riscv/include/asm/tlbflush.h, the comment says
> 
> > Flush entire local TLB.  'sfence.vma' implicitly fences with the instruction
> > cache as well, so a 'fence.i' is not necessary.
> 
> and in the privileged spec, it is stated that
> 
> > Executing an SFENCE.VMA instruction guarantees that any previous stores
> > already visible to the current RISC-V hart are ordered before all subsequent
> > implicit references from that hart to the memory-management data structures.
> 
> So my question is straightforward.  Is I-cache a kind of memory-management data
> structure?  am I missing something here?
> 
> Thanks for any clarification.

We just had a discussion about this with Andrew.  He clarified that 
SFENCE.VMA does not imply a FENCE.I, and we concluded that the comment in 
tlbflush.h is more confusing than helpful.  So we'll remove it:

https://lore.kernel.org/linux-riscv/alpine.DEB.2.21.9999.1910141254360.12988@viisi.sifive.com/T/#u

Thanks for bringing this up,


- Paul

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