All of lore.kernel.org
 help / color / mirror / Atom feed
From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: lorenzo.pieralisi@arm.com, bhelgaas@google.com,
	robh+dt@kernel.org, jonathanh@nvidia.com, andrew.murray@arm.com,
	linux-pci@vger.kernel.org, devicetree@vger.kernel.org,
	linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, kthota@nvidia.com,
	mmaddireddy@nvidia.com, sagar.tv@gmail.com
Subject: Re: [PATCH 1/2] PCI: tegra: Fix CLKREQ dependency programming
Date: Wed, 16 Oct 2019 18:19:20 +0200	[thread overview]
Message-ID: <20191016161920.GA2526111@ulmo> (raw)
In-Reply-To: <20191005164212.3646-1-vidyas@nvidia.com>

[-- Attachment #1: Type: text/plain, Size: 1735 bytes --]

On Sat, Oct 05, 2019 at 10:12:11PM +0530, Vidya Sagar wrote:
> Corrects the programming to provide REFCLK to the downstream device
> when there is no CLKREQ sideband signal routing present from root port
> to the endpont.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index f89f5acee72d..cbe95f0ea0ca 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -40,8 +40,6 @@
>  #define APPL_PINMUX_CLKREQ_OVERRIDE		BIT(3)
>  #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN	BIT(4)
>  #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE	BIT(5)
> -#define APPL_PINMUX_CLKREQ_OUT_OVRD_EN		BIT(9)
> -#define APPL_PINMUX_CLKREQ_OUT_OVRD		BIT(10)
>  
>  #define APPL_CTRL				0x4
>  #define APPL_CTRL_SYS_PRE_DET_STATE		BIT(6)
> @@ -1193,8 +1191,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>  
>  	if (!pcie->supports_clkreq) {
>  		val = appl_readl(pcie, APPL_PINMUX);
> -		val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
> -		val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
> +		val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
> +		val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
>  		appl_writel(pcie, val, APPL_PINMUX);
>  	}

If we do support CLKREQ, do we have to explicitly set the OVERRIDE bit?
Or clear the OVERRIDE_EN bit? Is it always guaranteed that the defaults
(OVERRIDE_EN = 0) is applied at this point?

That's an issue that's orthogonal to this patch, though, so for this
one:

Acked-by: Thierry Reding <treding@nvidia.com>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

WARNING: multiple messages have this Message-ID (diff)
From: Thierry Reding <thierry.reding@gmail.com>
To: Vidya Sagar <vidyas@nvidia.com>
Cc: devicetree@vger.kernel.org, lorenzo.pieralisi@arm.com,
	mmaddireddy@nvidia.com, kthota@nvidia.com,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	jonathanh@nvidia.com, linux-tegra@vger.kernel.org,
	robh+dt@kernel.org, bhelgaas@google.com, andrew.murray@arm.com,
	linux-arm-kernel@lists.infradead.org, sagar.tv@gmail.com
Subject: Re: [PATCH 1/2] PCI: tegra: Fix CLKREQ dependency programming
Date: Wed, 16 Oct 2019 18:19:20 +0200	[thread overview]
Message-ID: <20191016161920.GA2526111@ulmo> (raw)
In-Reply-To: <20191005164212.3646-1-vidyas@nvidia.com>


[-- Attachment #1.1: Type: text/plain, Size: 1735 bytes --]

On Sat, Oct 05, 2019 at 10:12:11PM +0530, Vidya Sagar wrote:
> Corrects the programming to provide REFCLK to the downstream device
> when there is no CLKREQ sideband signal routing present from root port
> to the endpont.
> 
> Signed-off-by: Vidya Sagar <vidyas@nvidia.com>
> ---
>  drivers/pci/controller/dwc/pcie-tegra194.c | 6 ++----
>  1 file changed, 2 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c
> index f89f5acee72d..cbe95f0ea0ca 100644
> --- a/drivers/pci/controller/dwc/pcie-tegra194.c
> +++ b/drivers/pci/controller/dwc/pcie-tegra194.c
> @@ -40,8 +40,6 @@
>  #define APPL_PINMUX_CLKREQ_OVERRIDE		BIT(3)
>  #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE_EN	BIT(4)
>  #define APPL_PINMUX_CLK_OUTPUT_IN_OVERRIDE	BIT(5)
> -#define APPL_PINMUX_CLKREQ_OUT_OVRD_EN		BIT(9)
> -#define APPL_PINMUX_CLKREQ_OUT_OVRD		BIT(10)
>  
>  #define APPL_CTRL				0x4
>  #define APPL_CTRL_SYS_PRE_DET_STATE		BIT(6)
> @@ -1193,8 +1191,8 @@ static int tegra_pcie_config_controller(struct tegra_pcie_dw *pcie,
>  
>  	if (!pcie->supports_clkreq) {
>  		val = appl_readl(pcie, APPL_PINMUX);
> -		val |= APPL_PINMUX_CLKREQ_OUT_OVRD_EN;
> -		val |= APPL_PINMUX_CLKREQ_OUT_OVRD;
> +		val |= APPL_PINMUX_CLKREQ_OVERRIDE_EN;
> +		val &= ~APPL_PINMUX_CLKREQ_OVERRIDE;
>  		appl_writel(pcie, val, APPL_PINMUX);
>  	}

If we do support CLKREQ, do we have to explicitly set the OVERRIDE bit?
Or clear the OVERRIDE_EN bit? Is it always guaranteed that the defaults
(OVERRIDE_EN = 0) is applied at this point?

That's an issue that's orthogonal to this patch, though, so for this
one:

Acked-by: Thierry Reding <treding@nvidia.com>

[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]

[-- Attachment #2: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  parent reply	other threads:[~2019-10-16 16:19 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-10-05 16:42 [PATCH 1/2] PCI: tegra: Fix CLKREQ dependency programming Vidya Sagar
2019-10-05 16:42 ` Vidya Sagar
2019-10-05 16:42 ` Vidya Sagar
2019-10-05 16:42 ` [PATCH 2/2] arm64: tegra: Assume no CLKREQ presence by default Vidya Sagar
2019-10-05 16:42   ` Vidya Sagar
2019-10-05 16:42   ` Vidya Sagar
2019-10-16 16:19   ` Thierry Reding
2019-10-16 16:19     ` Thierry Reding
2019-10-16 16:19 ` Thierry Reding [this message]
2019-10-16 16:19   ` [PATCH 1/2] PCI: tegra: Fix CLKREQ dependency programming Thierry Reding
2019-10-18  9:01 ` Lorenzo Pieralisi
2019-10-18  9:01   ` Lorenzo Pieralisi
2019-10-18  9:01   ` Lorenzo Pieralisi

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20191016161920.GA2526111@ulmo \
    --to=thierry.reding@gmail.com \
    --cc=andrew.murray@arm.com \
    --cc=bhelgaas@google.com \
    --cc=devicetree@vger.kernel.org \
    --cc=jonathanh@nvidia.com \
    --cc=kthota@nvidia.com \
    --cc=linux-arm-kernel@lists.infradead.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-pci@vger.kernel.org \
    --cc=linux-tegra@vger.kernel.org \
    --cc=lorenzo.pieralisi@arm.com \
    --cc=mmaddireddy@nvidia.com \
    --cc=robh+dt@kernel.org \
    --cc=sagar.tv@gmail.com \
    --cc=vidyas@nvidia.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.