From: Christoph Hellwig <hch@lst.de>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org, Atish Patra <atish.patra@wdc.com>,
linux-riscv@lists.infradead.org, Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH 08/20] riscv: abstract out CSR names for supervisor vs machine mode
Date: Thu, 17 Oct 2019 18:20:52 +0200 [thread overview]
Message-ID: <20191017162052.GA10221@lst.de> (raw)
In-Reply-To: <alpine.DEB.2.21.9999.1910151902060.12675@viisi.sifive.com>
On Tue, Oct 15, 2019 at 07:07:17PM -0700, Paul Walmsley wrote:
> > void start_thread(struct pt_regs *regs, unsigned long pc,
> > unsigned long sp)
> > {
> > - regs->sstatus = SR_SPIE;
> > + regs->xstatus = SR_SPIE;
>
> Looks like this should be "regs->xstatus = SR_PIE;"
>
> Will update it here. Let me know if you don't agree -
there is no SR_PIE, do you mean SR_XPІE? Good catch in that case,
but please let me resend the whole thing. I have some minor updates,
and I'd also like to do the rebase myself.
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WARNING: multiple messages have this Message-ID (diff)
From: Christoph Hellwig <hch@lst.de>
To: Paul Walmsley <paul.walmsley@sifive.com>
Cc: Christoph Hellwig <hch@lst.de>,
Palmer Dabbelt <palmer@sifive.com>,
Damien Le Moal <damien.lemoal@wdc.com>,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
Atish Patra <atish.patra@wdc.com>
Subject: Re: [PATCH 08/20] riscv: abstract out CSR names for supervisor vs machine mode
Date: Thu, 17 Oct 2019 18:20:52 +0200 [thread overview]
Message-ID: <20191017162052.GA10221@lst.de> (raw)
In-Reply-To: <alpine.DEB.2.21.9999.1910151902060.12675@viisi.sifive.com>
On Tue, Oct 15, 2019 at 07:07:17PM -0700, Paul Walmsley wrote:
> > void start_thread(struct pt_regs *regs, unsigned long pc,
> > unsigned long sp)
> > {
> > - regs->sstatus = SR_SPIE;
> > + regs->xstatus = SR_SPIE;
>
> Looks like this should be "regs->xstatus = SR_PIE;"
>
> Will update it here. Let me know if you don't agree -
there is no SR_PIE, do you mean SR_XPІE? Good catch in that case,
but please let me resend the whole thing. I have some minor updates,
and I'd also like to do the rebase myself.
next prev parent reply other threads:[~2019-10-17 16:20 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-03 9:32 RISC-V nommu support v4 Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 01/20] irqchip/sifive-plic: set max threshold for ignored handlers Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 02/20] riscv: refactor the IPI code Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 03/20] riscv: cleanup send_ipi_mask Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 04/20] riscv: optimize send_ipi_single Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 05/20] riscv: cleanup riscv_cpuid_to_hartid_mask Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 06/20] riscv: don't use the rdtime(h) pseudo-instructions Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 07/20] riscv: move the TLB flush logic out of line Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 08/20] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-10-16 2:07 ` Paul Walmsley
2019-10-16 2:07 ` Paul Walmsley
2019-10-17 16:20 ` Christoph Hellwig [this message]
2019-10-17 16:20 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 09/20] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 10/20] riscv: poison SBI calls " Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 11/20] riscv: cleanup the default power off implementation Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 12/20] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 13/20] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 14/20] riscv: provide native clint access for M-mode Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 15/20] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 16/20] riscv: use the correct interrupt levels for M-mode Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 17/20] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 18/20] riscv: add nommu support Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 19/20] riscv: provide a flat image loader Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
2019-09-03 9:32 ` [PATCH 20/20] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-09-03 9:32 ` Christoph Hellwig
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