[PATCH 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates.

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* [PATCH 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates.
@ 2019-10-24 18:24 ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
updates to make sure that we enable sending of VSC SDP and HDR Metadata
Infoframe SDP packet (when applicable) on fastsets.
In order to set an enabled state of VSC SDP and HDR Metadata Infoframe SDP,
It adds intel_enable_infoframe() function to handle enabling/disabling of
each Video DIP. And it add intel_infoframe_enabled() function to get an
enabled state of a specific infoframe.

Gwan-gyeong Mun (5):
  drm/i915: Add whether or not to enable an each of Video DIP
  drm/i915: Add checking a specific Video DIP is enabled or not
  drm/i915/dp: Stop sending of VSC SDP when it is not needed
  drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not
    needed
  drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe
    updates

 drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +
 .../drm/i915/display/intel_display_types.h    |  4 ++
 drivers/gpu/drm/i915/display/intel_dp.c       | 20 ++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 56 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h     |  6 ++
 5 files changed, 86 insertions(+), 2 deletions(-)

-- 
2.23.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates.
@ 2019-10-24 18:24 ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
updates to make sure that we enable sending of VSC SDP and HDR Metadata
Infoframe SDP packet (when applicable) on fastsets.
In order to set an enabled state of VSC SDP and HDR Metadata Infoframe SDP,
It adds intel_enable_infoframe() function to handle enabling/disabling of
each Video DIP. And it add intel_infoframe_enabled() function to get an
enabled state of a specific infoframe.

Gwan-gyeong Mun (5):
  drm/i915: Add whether or not to enable an each of Video DIP
  drm/i915: Add checking a specific Video DIP is enabled or not
  drm/i915/dp: Stop sending of VSC SDP when it is not needed
  drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not
    needed
  drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe
    updates

 drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +
 .../drm/i915/display/intel_display_types.h    |  4 ++
 drivers/gpu/drm/i915/display/intel_dp.c       | 20 ++++++-
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 56 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h     |  6 ++
 5 files changed, 86 insertions(+), 2 deletions(-)

-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [PATCH 1/5] drm/i915: Add whether or not to enable an each of Video DIP
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

Because DP ports don't use set_infoframes() / intel_write_infoframe()
machanisms, DP ports requires a handling of enabling/disabling of each
Video DIP when a changing usage of video DIP for SDP transmission such as
whether or not to use HDR.
For now it only adds enable_infoframe() callback for hsw platform.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  4 +++
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 35 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h     |  3 ++
 3 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index bac40482a2aa..a541c8cc8d83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1305,6 +1305,10 @@ struct intel_digital_port {
 			       const struct intel_crtc_state *crtc_state,
 			       unsigned int type,
 			       void *frame, ssize_t len);
+	void (*enable_infoframe)(struct intel_encoder *encoder,
+				 bool enable,
+				 const struct intel_crtc_state *crtc_state,
+				 unsigned int type);
 	void (*set_infoframes)(struct intel_encoder *encoder,
 			       bool enable,
 			       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b54ccbb5aad5..3c2aea93ae02 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -559,6 +559,24 @@ static void hsw_read_infoframe(struct intel_encoder *encoder,
 						     type, i >> 2));
 }
 
+static void hsw_enable_infoframe(struct intel_encoder *encoder,
+				 bool enable,
+				 const struct intel_crtc_state *crtc_state,
+				 unsigned int type)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+	u32 val = I915_READ(ctl_reg);
+
+	if (enable)
+		val |= hsw_infoframe_enable(type);
+	else
+		val &= ~hsw_infoframe_enable(type);
+
+	I915_WRITE(ctl_reg, val);
+	POSTING_READ(ctl_reg);
+}
+
 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *pipe_config)
 {
@@ -586,6 +604,22 @@ static const u8 infoframe_type_to_idx[] = {
 	HDMI_INFOFRAME_TYPE_DRM,
 };
 
+void intel_enable_infoframe(struct intel_encoder *encoder,
+			    bool enable,
+			    const struct intel_crtc_state *crtc_state,
+			    unsigned int type)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+	if (dig_port->enable_infoframe)
+		dig_port->enable_infoframe(encoder, enable, crtc_state, type);
+	else {
+		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+		DRM_DEBUG_KMS("GEN%d enable_infoframe() callback is not implemented!",
+			      INTEL_GEN(dev_priv));
+	}
+}
+
 u32 intel_hdmi_infoframe_enable(unsigned int type)
 {
 	int i;
@@ -3104,6 +3138,7 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
 		} else {
 			intel_dig_port->write_infoframe = hsw_write_infoframe;
 			intel_dig_port->read_infoframe = hsw_read_infoframe;
+			intel_dig_port->enable_infoframe = hsw_enable_infoframe;
 			intel_dig_port->set_infoframes = hsw_set_infoframes;
 			intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index cf1ea5427639..86f925526514 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -48,5 +48,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
 			  const struct intel_crtc_state *crtc_state,
 			  enum hdmi_infoframe_type type,
 			  union hdmi_infoframe *frame);
+void intel_enable_infoframe(struct intel_encoder *encoder, bool enable,
+			    const struct intel_crtc_state *crtc_state,
+			    unsigned int type);
 
 #endif /* __INTEL_HDMI_H__ */
-- 
2.23.0

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 1/5] drm/i915: Add whether or not to enable an each of Video DIP
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

Because DP ports don't use set_infoframes() / intel_write_infoframe()
machanisms, DP ports requires a handling of enabling/disabling of each
Video DIP when a changing usage of video DIP for SDP transmission such as
whether or not to use HDR.
For now it only adds enable_infoframe() callback for hsw platform.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 .../drm/i915/display/intel_display_types.h    |  4 +++
 drivers/gpu/drm/i915/display/intel_hdmi.c     | 35 +++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h     |  3 ++
 3 files changed, 42 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index bac40482a2aa..a541c8cc8d83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -1305,6 +1305,10 @@ struct intel_digital_port {
 			       const struct intel_crtc_state *crtc_state,
 			       unsigned int type,
 			       void *frame, ssize_t len);
+	void (*enable_infoframe)(struct intel_encoder *encoder,
+				 bool enable,
+				 const struct intel_crtc_state *crtc_state,
+				 unsigned int type);
 	void (*set_infoframes)(struct intel_encoder *encoder,
 			       bool enable,
 			       const struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index b54ccbb5aad5..3c2aea93ae02 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -559,6 +559,24 @@ static void hsw_read_infoframe(struct intel_encoder *encoder,
 						     type, i >> 2));
 }
 
+static void hsw_enable_infoframe(struct intel_encoder *encoder,
+				 bool enable,
+				 const struct intel_crtc_state *crtc_state,
+				 unsigned int type)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	i915_reg_t ctl_reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+	u32 val = I915_READ(ctl_reg);
+
+	if (enable)
+		val |= hsw_infoframe_enable(type);
+	else
+		val &= ~hsw_infoframe_enable(type);
+
+	I915_WRITE(ctl_reg, val);
+	POSTING_READ(ctl_reg);
+}
+
 static u32 hsw_infoframes_enabled(struct intel_encoder *encoder,
 				  const struct intel_crtc_state *pipe_config)
 {
@@ -586,6 +604,22 @@ static const u8 infoframe_type_to_idx[] = {
 	HDMI_INFOFRAME_TYPE_DRM,
 };
 
+void intel_enable_infoframe(struct intel_encoder *encoder,
+			    bool enable,
+			    const struct intel_crtc_state *crtc_state,
+			    unsigned int type)
+{
+	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+
+	if (dig_port->enable_infoframe)
+		dig_port->enable_infoframe(encoder, enable, crtc_state, type);
+	else {
+		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+		DRM_DEBUG_KMS("GEN%d enable_infoframe() callback is not implemented!",
+			      INTEL_GEN(dev_priv));
+	}
+}
+
 u32 intel_hdmi_infoframe_enable(unsigned int type)
 {
 	int i;
@@ -3104,6 +3138,7 @@ void intel_infoframe_init(struct intel_digital_port *intel_dig_port)
 		} else {
 			intel_dig_port->write_infoframe = hsw_write_infoframe;
 			intel_dig_port->read_infoframe = hsw_read_infoframe;
+			intel_dig_port->enable_infoframe = hsw_enable_infoframe;
 			intel_dig_port->set_infoframes = hsw_set_infoframes;
 			intel_dig_port->infoframes_enabled = hsw_infoframes_enabled;
 		}
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index cf1ea5427639..86f925526514 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -48,5 +48,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
 			  const struct intel_crtc_state *crtc_state,
 			  enum hdmi_infoframe_type type,
 			  union hdmi_infoframe *frame);
+void intel_enable_infoframe(struct intel_encoder *encoder, bool enable,
+			    const struct intel_crtc_state *crtc_state,
+			    unsigned int type);
 
 #endif /* __INTEL_HDMI_H__ */
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 2/5] drm/i915: Add checking a specific Video DIP is enabled or not
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

Because DP ports don't use intel_hdmi_infoframes_enabled() machanism,
DP ports requires a way to check a specific infoframe (aka. Video DIP )
is enabled or not.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |  3 +++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3c2aea93ae02..aed06a5da489 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -620,6 +620,27 @@ void intel_enable_infoframe(struct intel_encoder *encoder,
 	}
 }
 
+bool intel_infoframe_enabled(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
+			     unsigned int type)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	u32 val = 0;
+
+	val = dig_port->infoframes_enabled(encoder, crtc_state);
+
+	if (HAS_DDI(dev_priv)) {
+		if (val & hsw_infoframe_enable(type))
+			return true;
+	} else {
+		if (val & g4x_infoframe_enable(type))
+			return true;
+	}
+
+	return false;
+}
+
 u32 intel_hdmi_infoframe_enable(unsigned int type)
 {
 	int i;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 86f925526514..96d50f591b69 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -51,5 +51,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
 void intel_enable_infoframe(struct intel_encoder *encoder, bool enable,
 			    const struct intel_crtc_state *crtc_state,
 			    unsigned int type);
+bool intel_infoframe_enabled(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
+			     unsigned int type);
 
 #endif /* __INTEL_HDMI_H__ */
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 2/5] drm/i915: Add checking a specific Video DIP is enabled or not
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

Because DP ports don't use intel_hdmi_infoframes_enabled() machanism,
DP ports requires a way to check a specific infoframe (aka. Video DIP )
is enabled or not.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_hdmi.c | 21 +++++++++++++++++++++
 drivers/gpu/drm/i915/display/intel_hdmi.h |  3 +++
 2 files changed, 24 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.c b/drivers/gpu/drm/i915/display/intel_hdmi.c
index 3c2aea93ae02..aed06a5da489 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.c
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.c
@@ -620,6 +620,27 @@ void intel_enable_infoframe(struct intel_encoder *encoder,
 	}
 }
 
+bool intel_infoframe_enabled(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
+			     unsigned int type)
+{
+	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+	struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base);
+	u32 val = 0;
+
+	val = dig_port->infoframes_enabled(encoder, crtc_state);
+
+	if (HAS_DDI(dev_priv)) {
+		if (val & hsw_infoframe_enable(type))
+			return true;
+	} else {
+		if (val & g4x_infoframe_enable(type))
+			return true;
+	}
+
+	return false;
+}
+
 u32 intel_hdmi_infoframe_enable(unsigned int type)
 {
 	int i;
diff --git a/drivers/gpu/drm/i915/display/intel_hdmi.h b/drivers/gpu/drm/i915/display/intel_hdmi.h
index 86f925526514..96d50f591b69 100644
--- a/drivers/gpu/drm/i915/display/intel_hdmi.h
+++ b/drivers/gpu/drm/i915/display/intel_hdmi.h
@@ -51,5 +51,8 @@ void intel_read_infoframe(struct intel_encoder *encoder,
 void intel_enable_infoframe(struct intel_encoder *encoder, bool enable,
 			    const struct intel_crtc_state *crtc_state,
 			    unsigned int type);
+bool intel_infoframe_enabled(struct intel_encoder *encoder,
+			     const struct intel_crtc_state *crtc_state,
+			     unsigned int type);
 
 #endif /* __INTEL_HDMI_H__ */
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 3/5] drm/i915/dp: Stop sending of VSC SDP when it is not needed
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

It prevents sending VSC SDP Packet to a receiver when VSC SDP is not
needed. Because VSC SDP is used for PSR, YCbCr 420, HDR BT.2020 and etc,
it checks PSR is enabled or not.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 521ce23f38ac..ed6845485b41 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4735,8 +4735,16 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 			 const struct intel_crtc_state *crtc_state,
 			 const struct drm_connector_state *conn_state)
 {
-	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+		struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+		struct intel_encoder *encoder = &intel_dig_port->base;
+
+		if (!intel_psr_enabled(intel_dp) &&
+		    intel_infoframe_enabled(encoder, crtc_state, DP_SDP_VSC))
+			intel_enable_infoframe(encoder, false, crtc_state, DP_SDP_VSC);
+
 		return;
+	}
 
 	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
 }
-- 
2.23.0

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^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 3/5] drm/i915/dp: Stop sending of VSC SDP when it is not needed
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

It prevents sending VSC SDP Packet to a receiver when VSC SDP is not
needed. Because VSC SDP is used for PSR, YCbCr 420, HDR BT.2020 and etc,
it checks PSR is enabled or not.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 521ce23f38ac..ed6845485b41 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4735,8 +4735,16 @@ void intel_dp_vsc_enable(struct intel_dp *intel_dp,
 			 const struct intel_crtc_state *crtc_state,
 			 const struct drm_connector_state *conn_state)
 {
-	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state))
+	if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) {
+		struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+		struct intel_encoder *encoder = &intel_dig_port->base;
+
+		if (!intel_psr_enabled(intel_dp) &&
+		    intel_infoframe_enabled(encoder, crtc_state, DP_SDP_VSC))
+			intel_enable_infoframe(encoder, false, crtc_state, DP_SDP_VSC);
+
 		return;
+	}
 
 	intel_dp_setup_vsc_sdp(intel_dp, crtc_state, conn_state);
 }
-- 
2.23.0

_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 4/5] drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

It prevents sending HDR Metadata Infoframe SDP packet to a receiver when
HDR Metadata Infoframe SDP is not needed.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ed6845485b41..729f1e8cb49a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4753,8 +4753,16 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
 {
-	if (!conn_state->hdr_output_metadata)
+	if (!conn_state->hdr_output_metadata) {
+		struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+		struct intel_encoder *encoder = &intel_dig_port->base;
+
+		    if (intel_infoframe_enabled(encoder, crtc_state,
+						HDMI_PACKET_TYPE_GAMUT_METADATA))
+			intel_enable_infoframe(encoder, false, crtc_state,
+					       HDMI_PACKET_TYPE_GAMUT_METADATA);
 		return;
+	}
 
 	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
 						  crtc_state,
-- 
2.23.0

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 4/5] drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

It prevents sending HDR Metadata Infoframe SDP packet to a receiver when
HDR Metadata Infoframe SDP is not needed.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_dp.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index ed6845485b41..729f1e8cb49a 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -4753,8 +4753,16 @@ void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp,
 				  const struct intel_crtc_state *crtc_state,
 				  const struct drm_connector_state *conn_state)
 {
-	if (!conn_state->hdr_output_metadata)
+	if (!conn_state->hdr_output_metadata) {
+		struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
+		struct intel_encoder *encoder = &intel_dig_port->base;
+
+		    if (intel_infoframe_enabled(encoder, crtc_state,
+						HDMI_PACKET_TYPE_GAMUT_METADATA))
+			intel_enable_infoframe(encoder, false, crtc_state,
+					       HDMI_PACKET_TYPE_GAMUT_METADATA);
 		return;
+	}
 
 	intel_dp_setup_hdr_metadata_infoframe_sdp(intel_dp,
 						  crtc_state,
-- 
2.23.0

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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [PATCH 5/5] drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

Call intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
updates to make sure that we enable sending of VSC SDP and HDR Metadata
Infoframe SDP packet (when applicable) on fastsets.

These functions check pipe state and when the features does not need,
they disable the features.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1a49266f4f57..e07591ff2a6e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4020,6 +4020,8 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
 	intel_psr_update(intel_dp, crtc_state);
+	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
+	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	intel_panel_update_backlight(encoder, crtc_state, conn_state);
-- 
2.23.0

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* [Intel-gfx] [PATCH 5/5] drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates
@ 2019-10-24 18:24   ` Gwan-gyeong Mun
  0 siblings, 0 replies; 18+ messages in thread
From: Gwan-gyeong Mun @ 2019-10-24 18:24 UTC (permalink / raw)
  To: intel-gfx

Call intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
updates to make sure that we enable sending of VSC SDP and HDR Metadata
Infoframe SDP packet (when applicable) on fastsets.

These functions check pipe state and when the features does not need,
they disable the features.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
---
 drivers/gpu/drm/i915/display/intel_ddi.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index 1a49266f4f57..e07591ff2a6e 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4020,6 +4020,8 @@ static void intel_ddi_update_pipe_dp(struct intel_encoder *encoder,
 	intel_ddi_set_dp_msa(crtc_state, conn_state);
 
 	intel_psr_update(intel_dp, crtc_state);
+	intel_dp_vsc_enable(intel_dp, crtc_state, conn_state);
+	intel_dp_hdr_metadata_enable(intel_dp, crtc_state, conn_state);
 	intel_edp_drrs_enable(intel_dp, crtc_state);
 
 	intel_panel_update_backlight(encoder, crtc_state, conn_state);
-- 
2.23.0

_______________________________________________
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https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply related	[flat|nested] 18+ messages in thread

* ✗ Fi.CI.CHECKPATCH: warning for Update VSC SDP / HDR Metadata SDP states on pipe updates.
@ 2019-10-24 22:08   ` Patchwork
  0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-10-24 22:08 UTC (permalink / raw)
  To: Gwan-gyeong Mun; +Cc: intel-gfx

== Series Details ==

Series: Update VSC SDP / HDR Metadata SDP states on pipe updates.
URL   : https://patchwork.freedesktop.org/series/68531/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d3e19ea1104d drm/i915: Add whether or not to enable an each of Video DIP
-:71: CHECK:BRACES: Unbalanced braces around else statement
#71: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:616:
+	else {

-:73: WARNING:LINE_SPACING: Missing a blank line after declarations
#73: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:618:
+		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+		DRM_DEBUG_KMS("GEN%d enable_infoframe() callback is not implemented!",

total: 0 errors, 1 warnings, 1 checks, 71 lines checked
b396335c33e9 drm/i915: Add checking a specific Video DIP is enabled or not
f32dfb7a6a6c drm/i915/dp: Stop sending of VSC SDP when it is not needed
f98d7188544e drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed
-:25: WARNING:TABSTOP: Statements should start on a tabstop
#25: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4760:
+		    if (intel_infoframe_enabled(encoder, crtc_state,

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
4e64e33c758a drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Update VSC SDP / HDR Metadata SDP states on pipe updates.
@ 2019-10-24 22:08   ` Patchwork
  0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-10-24 22:08 UTC (permalink / raw)
  To: Gwan-gyeong Mun; +Cc: intel-gfx

== Series Details ==

Series: Update VSC SDP / HDR Metadata SDP states on pipe updates.
URL   : https://patchwork.freedesktop.org/series/68531/
State : warning

== Summary ==

$ dim checkpatch origin/drm-tip
d3e19ea1104d drm/i915: Add whether or not to enable an each of Video DIP
-:71: CHECK:BRACES: Unbalanced braces around else statement
#71: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:616:
+	else {

-:73: WARNING:LINE_SPACING: Missing a blank line after declarations
#73: FILE: drivers/gpu/drm/i915/display/intel_hdmi.c:618:
+		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+		DRM_DEBUG_KMS("GEN%d enable_infoframe() callback is not implemented!",

total: 0 errors, 1 warnings, 1 checks, 71 lines checked
b396335c33e9 drm/i915: Add checking a specific Video DIP is enabled or not
f32dfb7a6a6c drm/i915/dp: Stop sending of VSC SDP when it is not needed
f98d7188544e drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed
-:25: WARNING:TABSTOP: Statements should start on a tabstop
#25: FILE: drivers/gpu/drm/i915/display/intel_dp.c:4760:
+		    if (intel_infoframe_enabled(encoder, crtc_state,

total: 0 errors, 1 warnings, 0 checks, 17 lines checked
4e64e33c758a drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates

_______________________________________________
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Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

* ✗ Fi.CI.BAT: failure for Update VSC SDP / HDR Metadata SDP states on pipe updates.
@ 2019-10-24 22:37   ` Patchwork
  0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-10-24 22:37 UTC (permalink / raw)
  To: Gwan-gyeong Mun; +Cc: intel-gfx

== Series Details ==

Series: Update VSC SDP / HDR Metadata SDP states on pipe updates.
URL   : https://patchwork.freedesktop.org/series/68531/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7176 -> Patchwork_14973
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14973 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14973, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14973:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_uncore:
    - fi-kbl-r:           [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-r/igt@i915_selftest@live_uncore.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-r/igt@i915_selftest@live_uncore.html

  
Known issues
------------

  Here are the changes found in Patchwork_14973 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_basic@bad-close:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_basic@bad-close.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-icl-u3/igt@gem_basic@bad-close.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-8109u:       [PASS][5] -> [DMESG-FAIL][6] ([fdo#112050 ])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  * {igt@i915_selftest@live_gt_heartbeat}:
    - fi-kbl-x1275:       [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html

  * igt@kms_busy@basic-flip-a:
    - {fi-tgl-u2}:        [DMESG-WARN][11] ([fdo#111600]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-tgl-u2/igt@kms_busy@basic-flip-a.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-tgl-u2/igt@kms_busy@basic-flip-a.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111045] / [fdo#111096])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050 
  [fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096


Participating hosts (49 -> 45)
------------------------------

  Additional (2): fi-bxt-dsi fi-icl-dsi 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7176 -> Patchwork_14973

  CI-20190529: 20190529
  CI_DRM_7176: 9c250db49037a2ef0dc499d6cd2f9712fcbdf8c0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14973: 4e64e33c758a1d6adc26972ac5f5ca5ef41897c6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4e64e33c758a drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates
f98d7188544e drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed
f32dfb7a6a6c drm/i915/dp: Stop sending of VSC SDP when it is not needed
b396335c33e9 drm/i915: Add checking a specific Video DIP is enabled or not
d3e19ea1104d drm/i915: Add whether or not to enable an each of Video DIP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

* [Intel-gfx] ✗ Fi.CI.BAT: failure for Update VSC SDP / HDR Metadata SDP states on pipe updates.
@ 2019-10-24 22:37   ` Patchwork
  0 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2019-10-24 22:37 UTC (permalink / raw)
  To: Gwan-gyeong Mun; +Cc: intel-gfx

== Series Details ==

Series: Update VSC SDP / HDR Metadata SDP states on pipe updates.
URL   : https://patchwork.freedesktop.org/series/68531/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7176 -> Patchwork_14973
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_14973 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_14973, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_14973:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_uncore:
    - fi-kbl-r:           [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-r/igt@i915_selftest@live_uncore.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-r/igt@i915_selftest@live_uncore.html

  
Known issues
------------

  Here are the changes found in Patchwork_14973 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_basic@bad-close:
    - fi-icl-u3:          [PASS][3] -> [DMESG-WARN][4] ([fdo#107724]) +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_basic@bad-close.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-icl-u3/igt@gem_basic@bad-close.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-cfl-8109u:       [PASS][5] -> [DMESG-FAIL][6] ([fdo#112050 ])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-cfl-8109u/igt@i915_selftest@live_gem_contexts.html

  
#### Possible fixes ####

  * igt@gem_mmap_gtt@basic-write-cpu-read-gtt:
    - fi-icl-u3:          [DMESG-WARN][7] ([fdo#107724]) -> [PASS][8] +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-icl-u3/igt@gem_mmap_gtt@basic-write-cpu-read-gtt.html

  * {igt@i915_selftest@live_gt_heartbeat}:
    - fi-kbl-x1275:       [DMESG-FAIL][9] ([fdo#112096]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-x1275/igt@i915_selftest@live_gt_heartbeat.html

  * igt@kms_busy@basic-flip-a:
    - {fi-tgl-u2}:        [DMESG-WARN][11] ([fdo#111600]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-tgl-u2/igt@kms_busy@basic-flip-a.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-tgl-u2/igt@kms_busy@basic-flip-a.html

  
#### Warnings ####

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][13] ([fdo#111407]) -> [FAIL][14] ([fdo#111045] / [fdo#111096])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7176/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#107724]: https://bugs.freedesktop.org/show_bug.cgi?id=107724
  [fdo#111045]: https://bugs.freedesktop.org/show_bug.cgi?id=111045
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407
  [fdo#111600]: https://bugs.freedesktop.org/show_bug.cgi?id=111600
  [fdo#111735]: https://bugs.freedesktop.org/show_bug.cgi?id=111735
  [fdo#111747]: https://bugs.freedesktop.org/show_bug.cgi?id=111747
  [fdo#112050 ]: https://bugs.freedesktop.org/show_bug.cgi?id=112050 
  [fdo#112096]: https://bugs.freedesktop.org/show_bug.cgi?id=112096


Participating hosts (49 -> 45)
------------------------------

  Additional (2): fi-bxt-dsi fi-icl-dsi 
  Missing    (6): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-icl-y fi-byt-clapper 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7176 -> Patchwork_14973

  CI-20190529: 20190529
  CI_DRM_7176: 9c250db49037a2ef0dc499d6cd2f9712fcbdf8c0 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5237: 9a46404de7c42c8cc2d492176e956597ef28d7c4 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_14973: 4e64e33c758a1d6adc26972ac5f5ca5ef41897c6 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

4e64e33c758a drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates
f98d7188544e drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not needed
f32dfb7a6a6c drm/i915/dp: Stop sending of VSC SDP when it is not needed
b396335c33e9 drm/i915: Add checking a specific Video DIP is enabled or not
d3e19ea1104d drm/i915: Add whether or not to enable an each of Video DIP

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_14973/index.html
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [PATCH 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates.
@ 2019-10-25 12:19   ` Ville Syrjälä
  0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2019-10-25 12:19 UTC (permalink / raw)
  To: Gwan-gyeong Mun; +Cc: intel-gfx

On Thu, Oct 24, 2019 at 09:24:18PM +0300, Gwan-gyeong Mun wrote:
> It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
> updates to make sure that we enable sending of VSC SDP and HDR Metadata
> Infoframe SDP packet (when applicable) on fastsets.

I think we first need to move the stuff into the crtc state and add
real precompute+readout+state check. Then we could start thinking about
optimizing things for fastsets.

> In order to set an enabled state of VSC SDP and HDR Metadata Infoframe SDP,
> It adds intel_enable_infoframe() function to handle enabling/disabling of
> each Video DIP. And it add intel_infoframe_enabled() function to get an
> enabled state of a specific infoframe.
> 
> Gwan-gyeong Mun (5):
>   drm/i915: Add whether or not to enable an each of Video DIP
>   drm/i915: Add checking a specific Video DIP is enabled or not
>   drm/i915/dp: Stop sending of VSC SDP when it is not needed
>   drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not
>     needed
>   drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe
>     updates
> 
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +
>  .../drm/i915/display/intel_display_types.h    |  4 ++
>  drivers/gpu/drm/i915/display/intel_dp.c       | 20 ++++++-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     | 56 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_hdmi.h     |  6 ++
>  5 files changed, 86 insertions(+), 2 deletions(-)
> 
> -- 
> 2.23.0

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

* Re: [Intel-gfx] [PATCH 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates.
@ 2019-10-25 12:19   ` Ville Syrjälä
  0 siblings, 0 replies; 18+ messages in thread
From: Ville Syrjälä @ 2019-10-25 12:19 UTC (permalink / raw)
  To: Gwan-gyeong Mun; +Cc: intel-gfx

On Thu, Oct 24, 2019 at 09:24:18PM +0300, Gwan-gyeong Mun wrote:
> It calls intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() on pipe
> updates to make sure that we enable sending of VSC SDP and HDR Metadata
> Infoframe SDP packet (when applicable) on fastsets.

I think we first need to move the stuff into the crtc state and add
real precompute+readout+state check. Then we could start thinking about
optimizing things for fastsets.

> In order to set an enabled state of VSC SDP and HDR Metadata Infoframe SDP,
> It adds intel_enable_infoframe() function to handle enabling/disabling of
> each Video DIP. And it add intel_infoframe_enabled() function to get an
> enabled state of a specific infoframe.
> 
> Gwan-gyeong Mun (5):
>   drm/i915: Add whether or not to enable an each of Video DIP
>   drm/i915: Add checking a specific Video DIP is enabled or not
>   drm/i915/dp: Stop sending of VSC SDP when it is not needed
>   drm/i915/dp: Stop sending of HDR Metadata Infoframe when it is not
>     needed
>   drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe
>     updates
> 
>  drivers/gpu/drm/i915/display/intel_ddi.c      |  2 +
>  .../drm/i915/display/intel_display_types.h    |  4 ++
>  drivers/gpu/drm/i915/display/intel_dp.c       | 20 ++++++-
>  drivers/gpu/drm/i915/display/intel_hdmi.c     | 56 +++++++++++++++++++
>  drivers/gpu/drm/i915/display/intel_hdmi.h     |  6 ++
>  5 files changed, 86 insertions(+), 2 deletions(-)
> 
> -- 
> 2.23.0

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

^ permalink raw reply	[flat|nested] 18+ messages in thread

end of thread, other threads:[~2019-10-25 12:19 UTC | newest]

Thread overview: 18+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2019-10-24 18:24 [PATCH 0/5] Update VSC SDP / HDR Metadata SDP states on pipe updates Gwan-gyeong Mun
2019-10-24 18:24 ` [Intel-gfx] " Gwan-gyeong Mun
2019-10-24 18:24 ` [PATCH 1/5] drm/i915: Add whether or not to enable an each of Video DIP Gwan-gyeong Mun
2019-10-24 18:24   ` [Intel-gfx] " Gwan-gyeong Mun
2019-10-24 18:24 ` [PATCH 2/5] drm/i915: Add checking a specific Video DIP is enabled or not Gwan-gyeong Mun
2019-10-24 18:24   ` [Intel-gfx] " Gwan-gyeong Mun
2019-10-24 18:24 ` [PATCH 3/5] drm/i915/dp: Stop sending of VSC SDP when it is not needed Gwan-gyeong Mun
2019-10-24 18:24   ` [Intel-gfx] " Gwan-gyeong Mun
2019-10-24 18:24 ` [PATCH 4/5] drm/i915/dp: Stop sending of HDR Metadata Infoframe " Gwan-gyeong Mun
2019-10-24 18:24   ` [Intel-gfx] " Gwan-gyeong Mun
2019-10-24 18:24 ` [PATCH 5/5] drm/i915/dp: Call dp_vsc_enable() / dp_hdr_metata_enable() on pipe updates Gwan-gyeong Mun
2019-10-24 18:24   ` [Intel-gfx] " Gwan-gyeong Mun
2019-10-24 22:08 ` ✗ Fi.CI.CHECKPATCH: warning for Update VSC SDP / HDR Metadata SDP states " Patchwork
2019-10-24 22:08   ` [Intel-gfx] " Patchwork
2019-10-24 22:37 ` ✗ Fi.CI.BAT: failure " Patchwork
2019-10-24 22:37   ` [Intel-gfx] " Patchwork
2019-10-25 12:19 ` [PATCH 0/5] " Ville Syrjälä
2019-10-25 12:19   ` [Intel-gfx] " Ville Syrjälä

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