From: Segher Boessenkool <segher@kernel.crashing.org>
To: "Alastair D'Silva" <alastair@au1.ibm.com>
Cc: David Hildenbrand <david@redhat.com>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Paul Mackerras <paulus@samba.org>,
Nicholas Piggin <npiggin@gmail.com>,
alastair@d-silva.org, Qian Cai <cai@lca.pw>,
Thomas Gleixner <tglx@linutronix.de>,
linuxppc-dev@lists.ozlabs.org,
Andrew Morton <akpm@linux-foundation.org>,
Allison Randal <allison@lohutok.net>
Subject: Re: [PATCH v5 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB
Date: Mon, 4 Nov 2019 13:43:57 -0600 [thread overview]
Message-ID: <20191104194357.GE16031@gate.crashing.org> (raw)
In-Reply-To: <20191104023305.9581-2-alastair@au1.ibm.com>
On Mon, Nov 04, 2019 at 01:32:53PM +1100, Alastair D'Silva wrote:
> When calling flush_icache_range with a size >4GB, we were masking
> off the upper 32 bits, so we would incorrectly flush a range smaller
> than intended.
>
> This patch replaces the 32 bit shifts with 64 bit ones, so that
> the full size is accounted for.
Please send this separately, to be committed right now? It is a bug fix,
independent of the rest of the series.
Segher
WARNING: multiple messages have this Message-ID (diff)
From: Segher Boessenkool <segher@kernel.crashing.org>
To: "Alastair D'Silva" <alastair@au1.ibm.com>
Cc: alastair@d-silva.org,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
David Hildenbrand <david@redhat.com>,
linux-kernel@vger.kernel.org, stable@vger.kernel.org,
Paul Mackerras <paulus@samba.org>,
Nicholas Piggin <npiggin@gmail.com>, Qian Cai <cai@lca.pw>,
Thomas Gleixner <tglx@linutronix.de>,
linuxppc-dev@lists.ozlabs.org,
Andrew Morton <akpm@linux-foundation.org>,
Allison Randal <allison@lohutok.net>
Subject: Re: [PATCH v5 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB
Date: Mon, 4 Nov 2019 13:43:57 -0600 [thread overview]
Message-ID: <20191104194357.GE16031@gate.crashing.org> (raw)
In-Reply-To: <20191104023305.9581-2-alastair@au1.ibm.com>
On Mon, Nov 04, 2019 at 01:32:53PM +1100, Alastair D'Silva wrote:
> When calling flush_icache_range with a size >4GB, we were masking
> off the upper 32 bits, so we would incorrectly flush a range smaller
> than intended.
>
> This patch replaces the 32 bit shifts with 64 bit ones, so that
> the full size is accounted for.
Please send this separately, to be committed right now? It is a bug fix,
independent of the rest of the series.
Segher
next prev parent reply other threads:[~2019-11-04 19:46 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-11-04 2:32 [PATCH v5 0/6] powerpc: convert cache asm to C Alastair D'Silva
2019-11-04 2:32 ` Alastair D'Silva
2019-11-04 2:32 ` [PATCH v5 1/6] powerpc: Allow flush_icache_range to work across ranges >4GB Alastair D'Silva
2019-11-04 2:32 ` Alastair D'Silva
2019-11-04 19:43 ` Segher Boessenkool [this message]
2019-11-04 19:43 ` Segher Boessenkool
2019-11-05 6:04 ` Christophe Leroy
2019-11-05 6:04 ` Christophe Leroy
2019-11-06 17:49 ` Segher Boessenkool
2019-11-14 9:08 ` Michael Ellerman
2019-11-14 9:08 ` Michael Ellerman
2019-11-04 2:32 ` [PATCH v5 2/6] powerpc: Allow 64bit VDSO __kernel_sync_dicache " Alastair D'Silva
2019-11-04 2:32 ` Alastair D'Silva
2019-11-04 2:32 ` [PATCH v5 3/6] powerpc: define helpers to get L1 icache sizes Alastair D'Silva
2019-11-04 2:32 ` Alastair D'Silva
2019-11-04 2:32 ` [PATCH v5 4/6] powerpc: Convert flush_icache_range & friends to C Alastair D'Silva
2019-11-04 2:32 ` Alastair D'Silva
2019-11-04 4:54 ` kbuild test robot
2019-11-04 4:54 ` kbuild test robot
2019-11-04 4:54 ` kbuild test robot
2019-11-12 10:49 ` Michael Ellerman
2019-11-12 10:49 ` Michael Ellerman
2019-11-04 2:32 ` [PATCH v5 5/6] powerpc: Chunk calls to flush_dcache_range in arch_*_memory Alastair D'Silva
2019-11-04 2:32 ` Alastair D'Silva
2019-11-07 11:54 ` Michael Ellerman
2019-11-07 11:54 ` Michael Ellerman
2019-11-04 2:32 ` [PATCH v5 6/6] powerpc: Don't flush caches when adding memory Alastair D'Silva
2019-11-04 2:32 ` Alastair D'Silva
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