Re: [V3 1/8] drm/i915/dsi: Configure transcoder operation for command mode.

[kbuild test robot <lkp@intel.com>]

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Hi Vandita,

Thank you for the patch! Yet something to improve:

[auto build test ERROR on drm-intel/for-linux-next]
[cannot apply to v5.4-rc8 next-20191118]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]

url:    https://github.com/0day-ci/linux/commits/Vandita-Kulkarni/Add-support-for-mipi-dsi-cmd-mode/20191120-015713
base:   git://anongit.freedesktop.org/drm-intel for-linux-next
config: i386-defconfig (attached as .config)
compiler: gcc-7 (Debian 7.4.0-14) 7.4.0
reproduce:
        # save the attached .config to linux build tree
        make ARCH=i386 

If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>

All error/warnings (new ones prefixed by >>):

   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_configure_transcoder':
>> drivers/gpu/drm/i915/display/icl_dsi.c:718:11: error: 'TE_SOURCE_GPIO' undeclared (first use in this function); did you mean 'DP_SOURCE_OUI'?
       tmp |= TE_SOURCE_GPIO;
              ^~~~~~~~~~~~~~
              DP_SOURCE_OUI
   drivers/gpu/drm/i915/display/icl_dsi.c:718:11: note: each undeclared identifier is reported only once for each function it appears in
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_config_util_pin':
>> drivers/gpu/drm/i915/display/icl_dsi.c:986:10: error: 'UTIL_PIN_DIRECTION_INPUT' undeclared (first use in this function); did you mean 'UTIL_PIN_PIPE_MASK'?
      tmp |= UTIL_PIN_DIRECTION_INPUT;
             ^~~~~~~~~~~~~~~~~~~~~~~~
             UTIL_PIN_PIPE_MASK
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/display/icl_dsi.c: In function 'gen11_dsi_deconfigure_trancoder':
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:20: error: implicit declaration of function 'DSI_CMD_FRMCTL'; did you mean 'DSI_CMD_RXCTL'? [-Werror=implicit-function-declaration]
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
                       ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
>> drivers/gpu/drm/i915/i915_drv.h:1981:57: error: incompatible type for argument 2 of 'intel_uncore_read'
    #define I915_READ(reg__)  __I915_REG_OP(read, dev_priv, (reg__))
                                                            ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1151:10: note: in expansion of macro 'I915_READ'
       tmp = I915_READ(DSI_CMD_FRMCTL(port));
             ^~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:287:22: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline u##x__ intel_uncore_##name__(struct intel_uncore *uncore, \
                         ^
>> drivers/gpu/drm/i915/intel_uncore.h:302:1: note: in expansion of macro '__uncore_read'
    __uncore_read(read, 32, l, true)
    ^~~~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1152:12: error: 'DSI_PERIODIC_FRAME_UPDATE_ENABLE' undeclared (first use in this function); did you mean 'GEN6_MBCTL_BME_UPDATE_ENABLE'?
       tmp &= ~DSI_PERIODIC_FRAME_UPDATE_ENABLE;
               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
               GEN6_MBCTL_BME_UPDATE_ENABLE
   In file included from drivers/gpu/drm/i915/display/intel_display_types.h:46:0,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
>> drivers/gpu/drm/i915/i915_drv.h:1982:65: error: incompatible type for argument 2 of 'intel_uncore_write'
    #define I915_WRITE(reg__, val__) __I915_REG_OP(write, dev_priv, (reg__), (val__))
                                                                    ^
   drivers/gpu/drm/i915/i915_drv.h:1979:45: note: in definition of macro '__I915_REG_OP'
     intel_uncore_##op__(&(dev_priv__)->uncore, __VA_ARGS__)
                                                ^~~~~~~~~~~
>> drivers/gpu/drm/i915/display/icl_dsi.c:1153:4: note: in expansion of macro 'I915_WRITE'
       I915_WRITE(DSI_CMD_FRMCTL(port), tmp);
       ^~~~~~~~~~
   In file included from drivers/gpu/drm/i915/gt/uc/intel_guc.h:9:0,
                    from drivers/gpu/drm/i915/gt/uc/intel_uc.h:9,
                    from drivers/gpu/drm/i915/gt/intel_gt_types.h:16,
                    from drivers/gpu/drm/i915/i915_drv.h:81,
                    from drivers/gpu/drm/i915/display/intel_display_types.h:46,
                    from drivers/gpu/drm/i915/display/intel_dsi.h:30,
                    from drivers/gpu/drm/i915/display/icl_dsi.c:35:
   drivers/gpu/drm/i915/intel_uncore.h:294:20: note: expected 'i915_reg_t {aka struct <anonymous>}' but argument is of type 'int'
    static inline void intel_uncore_##name__(struct intel_uncore *uncore, \
                       ^
>> drivers/gpu/drm/i915/intel_uncore.h:308:1: note: in expansion of macro '__uncore_write'
    __uncore_write(write, 32, l, true)
    ^~~~~~~~~~~~~~
   cc1: some warnings being treated as errors

vim +718 drivers/gpu/drm/i915/display/icl_dsi.c

   621	
   622	static void
   623	gen11_dsi_configure_transcoder(struct intel_encoder *encoder,
   624				       const struct intel_crtc_state *pipe_config)
   625	{
   626		struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   627		struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
   628		struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
   629		enum pipe pipe = intel_crtc->pipe;
   630		u32 tmp;
   631		enum port port;
   632		enum transcoder dsi_trans;
   633	
   634		for_each_dsi_port(port, intel_dsi->ports) {
   635			dsi_trans = dsi_port_to_transcoder(port);
   636			tmp = I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans));
   637	
   638			if (intel_dsi->eotp_pkt)
   639				tmp &= ~EOTP_DISABLED;
   640			else
   641				tmp |= EOTP_DISABLED;
   642	
   643			/* enable link calibration if freq > 1.5Gbps */
   644			if (intel_dsi_bitrate(intel_dsi) >= 1500 * 1000) {
   645				tmp &= ~LINK_CALIBRATION_MASK;
   646				tmp |= CALIBRATION_ENABLED_INITIAL_ONLY;
   647			}
   648	
   649			/* configure continuous clock */
   650			tmp &= ~CONTINUOUS_CLK_MASK;
   651			if (intel_dsi->clock_stop)
   652				tmp |= CLK_ENTER_LP_AFTER_DATA;
   653			else
   654				tmp |= CLK_HS_CONTINUOUS;
   655	
   656			/* configure buffer threshold limit to minimum */
   657			tmp &= ~PIX_BUF_THRESHOLD_MASK;
   658			tmp |= PIX_BUF_THRESHOLD_1_4;
   659	
   660			/* set virtual channel to '0' */
   661			tmp &= ~PIX_VIRT_CHAN_MASK;
   662			tmp |= PIX_VIRT_CHAN(0);
   663	
   664			/* program BGR transmission */
   665			if (intel_dsi->bgr_enabled)
   666				tmp |= BGR_TRANSMISSION;
   667	
   668			/* select pixel format */
   669			tmp &= ~PIX_FMT_MASK;
   670			switch (intel_dsi->pixel_format) {
   671			default:
   672				MISSING_CASE(intel_dsi->pixel_format);
   673				/* fallthrough */
   674			case MIPI_DSI_FMT_RGB565:
   675				tmp |= PIX_FMT_RGB565;
   676				break;
   677			case MIPI_DSI_FMT_RGB666_PACKED:
   678				tmp |= PIX_FMT_RGB666_PACKED;
   679				break;
   680			case MIPI_DSI_FMT_RGB666:
   681				tmp |= PIX_FMT_RGB666_LOOSE;
   682				break;
   683			case MIPI_DSI_FMT_RGB888:
   684				tmp |= PIX_FMT_RGB888;
   685				break;
   686			}
   687	
   688			if (INTEL_GEN(dev_priv) >= 12) {
   689				if (is_vid_mode(intel_dsi))
   690					tmp |= BLANKING_PACKET_ENABLE;
   691			}
   692	
   693			/* program DSI operation mode */
   694			if (is_vid_mode(intel_dsi)) {
   695				tmp &= ~OP_MODE_MASK;
   696				switch (intel_dsi->video_mode_format) {
   697				default:
   698					MISSING_CASE(intel_dsi->video_mode_format);
   699					/* fallthrough */
   700				case VIDEO_MODE_NON_BURST_WITH_SYNC_EVENTS:
   701					tmp |= VIDEO_MODE_SYNC_EVENT;
   702					break;
   703				case VIDEO_MODE_NON_BURST_WITH_SYNC_PULSE:
   704					tmp |= VIDEO_MODE_SYNC_PULSE;
   705					break;
   706				}
   707			} else {
   708				/*
   709				 * FIXME: Retrieve this info from VBT.
   710				 * As per the spec when dsi transcoder is operating
   711				 * in TE GATE mode, TE comes from GPIO
   712				 * which is UTIL PIN for DSI 0.
   713				 * Also this GPIO would not be used for other
   714				 * purposes is an assumption.
   715				 */
   716				tmp &= ~OP_MODE_MASK;
   717				tmp |= CMD_MODE_TE_GATE;
 > 718				tmp |= TE_SOURCE_GPIO;
   719			}
   720	
   721			I915_WRITE(DSI_TRANS_FUNC_CONF(dsi_trans), tmp);
   722		}
   723	
   724		/* enable port sync mode if dual link */
   725		if (intel_dsi->dual_link) {
   726			for_each_dsi_port(port, intel_dsi->ports) {
   727				dsi_trans = dsi_port_to_transcoder(port);
   728				tmp = I915_READ(TRANS_DDI_FUNC_CTL2(dsi_trans));
   729				tmp |= PORT_SYNC_MODE_ENABLE;
   730				I915_WRITE(TRANS_DDI_FUNC_CTL2(dsi_trans), tmp);
   731			}
   732	
   733			/* configure stream splitting */
   734			configure_dual_link_mode(encoder, pipe_config);
   735		}
   736	
   737		for_each_dsi_port(port, intel_dsi->ports) {
   738			dsi_trans = dsi_port_to_transcoder(port);
   739	
   740			/* select data lane width */
   741			tmp = I915_READ(TRANS_DDI_FUNC_CTL(dsi_trans));
   742			tmp &= ~DDI_PORT_WIDTH_MASK;
   743			tmp |= DDI_PORT_WIDTH(intel_dsi->lane_count);
   744	
   745			/* select input pipe */
   746			tmp &= ~TRANS_DDI_EDP_INPUT_MASK;
   747			switch (pipe) {
   748			default:
   749				MISSING_CASE(pipe);
   750				/* fallthrough */
   751			case PIPE_A:
   752				tmp |= TRANS_DDI_EDP_INPUT_A_ON;
   753				break;
   754			case PIPE_B:
   755				tmp |= TRANS_DDI_EDP_INPUT_B_ONOFF;
   756				break;
   757			case PIPE_C:
   758				tmp |= TRANS_DDI_EDP_INPUT_C_ONOFF;
   759				break;
   760			}
   761	
   762			/* enable DDI buffer */
   763			tmp |= TRANS_DDI_FUNC_ENABLE;
   764			I915_WRITE(TRANS_DDI_FUNC_CTL(dsi_trans), tmp);
   765		}
   766	
   767		/* wait for link ready */
   768		for_each_dsi_port(port, intel_dsi->ports) {
   769			dsi_trans = dsi_port_to_transcoder(port);
   770			if (wait_for_us((I915_READ(DSI_TRANS_FUNC_CONF(dsi_trans)) &
   771					LINK_READY), 2500))
   772				DRM_ERROR("DSI link not ready\n");
   773		}
   774	}
   775	

---
0-DAY kernel test infrastructure                 Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation

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