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From: Kishon Vijay Abraham I <kishon@ti.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andrew Murray <andrew.murray@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Murali Karicheri <m-karicheri2@ti.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	Kishon Vijay Abraham I <kishon@ti.com>,
	<linux-pci@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<linux-arm-kernel@lists.infradead.org>,
	Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: [PATCH 3/4] PCI: keystone: Allow AM654 PCIe Endpoint to raise MSIX interrupt
Date: Wed, 11 Dec 2019 18:16:07 +0530	[thread overview]
Message-ID: <20191211124608.887-4-kishon@ti.com> (raw)
In-Reply-To: <20191211124608.887-1-kishon@ti.com>

AM654 PCIe EP controller has MSIX capability register and has the
ability to raise MSIX interrupt. Add support in pci-keystone.c
for PCIe endpoint controller in AM654 to raise MSIX interrupts.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/dwc/pci-keystone.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index af677254a072..dbe31589eb61 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -959,6 +959,9 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	case PCI_EPC_IRQ_MSI:
 		dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
 		break;
+	case PCI_EPC_IRQ_MSIX:
+		dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
+		break;
 	default:
 		dev_err(pci->dev, "UNKNOWN IRQ type\n");
 		return -EINVAL;
@@ -970,7 +973,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 static const struct pci_epc_features ks_pcie_am654_epc_features = {
 	.linkup_notifier = false,
 	.msi_capable = true,
-	.msix_capable = false,
+	.msix_capable = true,
 	.reserved_bar = 1 << BAR_0 | 1 << BAR_1,
 	.bar_fixed_64bit = 1 << BAR_0,
 	.bar_fixed_size[2] = SZ_1M,
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Kishon Vijay Abraham I <kishon@ti.com>
To: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andrew Murray <andrew.murray@arm.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>
Cc: Xiaowei Bao <xiaowei.bao@nxp.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	linux-kernel@vger.kernel.org,
	Kishon Vijay Abraham I <kishon@ti.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org
Subject: [PATCH 3/4] PCI: keystone: Allow AM654 PCIe Endpoint to raise MSIX interrupt
Date: Wed, 11 Dec 2019 18:16:07 +0530	[thread overview]
Message-ID: <20191211124608.887-4-kishon@ti.com> (raw)
In-Reply-To: <20191211124608.887-1-kishon@ti.com>

AM654 PCIe EP controller has MSIX capability register and has the
ability to raise MSIX interrupt. Add support in pci-keystone.c
for PCIe endpoint controller in AM654 to raise MSIX interrupts.

Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
 drivers/pci/controller/dwc/pci-keystone.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/drivers/pci/controller/dwc/pci-keystone.c b/drivers/pci/controller/dwc/pci-keystone.c
index af677254a072..dbe31589eb61 100644
--- a/drivers/pci/controller/dwc/pci-keystone.c
+++ b/drivers/pci/controller/dwc/pci-keystone.c
@@ -959,6 +959,9 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 	case PCI_EPC_IRQ_MSI:
 		dw_pcie_ep_raise_msi_irq(ep, func_no, interrupt_num);
 		break;
+	case PCI_EPC_IRQ_MSIX:
+		dw_pcie_ep_raise_msix_irq(ep, func_no, interrupt_num);
+		break;
 	default:
 		dev_err(pci->dev, "UNKNOWN IRQ type\n");
 		return -EINVAL;
@@ -970,7 +973,7 @@ static int ks_pcie_am654_raise_irq(struct dw_pcie_ep *ep, u8 func_no,
 static const struct pci_epc_features ks_pcie_am654_epc_features = {
 	.linkup_notifier = false,
 	.msi_capable = true,
-	.msix_capable = false,
+	.msix_capable = true,
 	.reserved_bar = 1 << BAR_0 | 1 << BAR_1,
 	.bar_fixed_64bit = 1 << BAR_0,
 	.bar_fixed_size[2] = SZ_1M,
-- 
2.17.1


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  parent reply	other threads:[~2019-12-11 12:45 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-11 12:46 [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core Kishon Vijay Abraham I
2019-12-11 12:46 ` Kishon Vijay Abraham I
2019-12-11 12:46 ` [PATCH 1/4] PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments Kishon Vijay Abraham I
2019-12-11 12:46   ` Kishon Vijay Abraham I
2019-12-11 12:46 ` [PATCH 2/4] PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table address Kishon Vijay Abraham I
2019-12-11 12:46   ` Kishon Vijay Abraham I
2019-12-11 12:46 ` Kishon Vijay Abraham I [this message]
2019-12-11 12:46   ` [PATCH 3/4] PCI: keystone: Allow AM654 PCIe Endpoint to raise MSIX interrupt Kishon Vijay Abraham I
2019-12-11 12:46 ` [PATCH 4/4] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I
2019-12-11 12:46   ` Kishon Vijay Abraham I
2020-01-23 22:10   ` Ramon Fried
2020-01-23 22:10     ` Ramon Fried
2019-12-11 22:46 ` [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core Bjorn Helgaas
2019-12-11 22:46   ` Bjorn Helgaas
2020-01-09 10:19   ` Kishon Vijay Abraham I
2020-01-09 10:19     ` Kishon Vijay Abraham I
2020-01-09 10:20     ` Xiaowei Bao
2020-01-09 10:20       ` Xiaowei Bao
2020-01-09 10:33     ` Gustavo Pimentel
2020-01-09 10:33       ` Gustavo Pimentel

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