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From: Bjorn Helgaas <helgaas@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Andrew Murray <andrew.murray@arm.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	Murali Karicheri <m-karicheri2@ti.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	Xiaowei Bao <xiaowei.bao@nxp.com>
Subject: Re: [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core
Date: Wed, 11 Dec 2019 16:46:36 -0600	[thread overview]
Message-ID: <20191211224636.GA122332@google.com> (raw)
In-Reply-To: <20191211124608.887-1-kishon@ti.com>

On Wed, Dec 11, 2019 at 06:16:04PM +0530, Kishon Vijay Abraham I wrote:
> Existing MSI-X support in Endpoint core has limitations:
>  1) MSIX table (which is mapped to a BAR) is not allocated by
>     anyone. Ideally this should be allocated by endpoint
>     function driver.
>  2) Endpoint controller can choose any random BARs for MSIX
>     table (irrespective of whether the endpoint function driver
>     has allocated memory for it or not)
> 
> In order to avoid these limitations, pci_epc_set_msix() is
> modified to include BAR Indicator register (BIR) configuration
> and MSIX table offset as arguments. This series also fixed MSIX
> support in dwc driver and add MSI-X support in Cadence PCIe driver.
> 
> The previous version of Cadence EP MSI-X support is @ [1].
> This series is created on top of [2]
> 
> [1] -> https://patchwork.ozlabs.org/patch/971160/
> [2] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com
> 
> Alan Douglas (1):
>   PCI: cadence: Add MSI-X support to Endpoint driver
> 
> Kishon Vijay Abraham I (3):
>   PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
>   PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table
>     address
>   PCI: keystone: Add AM654 PCIe Endpoint to raise MSIX interrupt

Trivial nits:

  - There's a mix of "MSI-X" and "MSIX" in the subjects, commit logs,
    and comments.  I prefer "MSI-X" to match usage in the spec.

  - "Fixes:" tags need not include "commit".  It doesn't *hurt*
    anything, but it takes up space that could be used for the
    subject.

  - Commit references typically use a 12-char SHA1.  Again, doesn't
    hurt anything.

WARNING: multiple messages have this Message-ID (diff)
From: Bjorn Helgaas <helgaas@kernel.org>
To: Kishon Vijay Abraham I <kishon@ti.com>
Cc: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
	Xiaowei Bao <xiaowei.bao@nxp.com>,
	Jingoo Han <jingoohan1@gmail.com>,
	linux-kernel@vger.kernel.org,
	Murali Karicheri <m-karicheri2@ti.com>,
	linux-pci@vger.kernel.org, Andrew Murray <andrew.murray@arm.com>,
	Gustavo Pimentel <gustavo.pimentel@synopsys.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core
Date: Wed, 11 Dec 2019 16:46:36 -0600	[thread overview]
Message-ID: <20191211224636.GA122332@google.com> (raw)
In-Reply-To: <20191211124608.887-1-kishon@ti.com>

On Wed, Dec 11, 2019 at 06:16:04PM +0530, Kishon Vijay Abraham I wrote:
> Existing MSI-X support in Endpoint core has limitations:
>  1) MSIX table (which is mapped to a BAR) is not allocated by
>     anyone. Ideally this should be allocated by endpoint
>     function driver.
>  2) Endpoint controller can choose any random BARs for MSIX
>     table (irrespective of whether the endpoint function driver
>     has allocated memory for it or not)
> 
> In order to avoid these limitations, pci_epc_set_msix() is
> modified to include BAR Indicator register (BIR) configuration
> and MSIX table offset as arguments. This series also fixed MSIX
> support in dwc driver and add MSI-X support in Cadence PCIe driver.
> 
> The previous version of Cadence EP MSI-X support is @ [1].
> This series is created on top of [2]
> 
> [1] -> https://patchwork.ozlabs.org/patch/971160/
> [2] -> http://lore.kernel.org/r/20191209092147.22901-1-kishon@ti.com
> 
> Alan Douglas (1):
>   PCI: cadence: Add MSI-X support to Endpoint driver
> 
> Kishon Vijay Abraham I (3):
>   PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments
>   PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table
>     address
>   PCI: keystone: Add AM654 PCIe Endpoint to raise MSIX interrupt

Trivial nits:

  - There's a mix of "MSI-X" and "MSIX" in the subjects, commit logs,
    and comments.  I prefer "MSI-X" to match usage in the spec.

  - "Fixes:" tags need not include "commit".  It doesn't *hurt*
    anything, but it takes up space that could be used for the
    subject.

  - Commit references typically use a 12-char SHA1.  Again, doesn't
    hurt anything.

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  parent reply	other threads:[~2019-12-11 22:46 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-12-11 12:46 [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core Kishon Vijay Abraham I
2019-12-11 12:46 ` Kishon Vijay Abraham I
2019-12-11 12:46 ` [PATCH 1/4] PCI: endpoint: Fix ->set_msix() to take BIR and offset as arguments Kishon Vijay Abraham I
2019-12-11 12:46   ` Kishon Vijay Abraham I
2019-12-11 12:46 ` [PATCH 2/4] PCI: dwc: Fix dw_pcie_ep_raise_msix_irq() to get correct MSIX table address Kishon Vijay Abraham I
2019-12-11 12:46   ` Kishon Vijay Abraham I
2019-12-11 12:46 ` [PATCH 3/4] PCI: keystone: Allow AM654 PCIe Endpoint to raise MSIX interrupt Kishon Vijay Abraham I
2019-12-11 12:46   ` Kishon Vijay Abraham I
2019-12-11 12:46 ` [PATCH 4/4] PCI: cadence: Add MSI-X support to Endpoint driver Kishon Vijay Abraham I
2019-12-11 12:46   ` Kishon Vijay Abraham I
2020-01-23 22:10   ` Ramon Fried
2020-01-23 22:10     ` Ramon Fried
2019-12-11 22:46 ` Bjorn Helgaas [this message]
2019-12-11 22:46   ` [PATCH 0/4] Redesign MSI-X support in PCIe Endpoint Core Bjorn Helgaas
2020-01-09 10:19   ` Kishon Vijay Abraham I
2020-01-09 10:19     ` Kishon Vijay Abraham I
2020-01-09 10:20     ` Xiaowei Bao
2020-01-09 10:20       ` Xiaowei Bao
2020-01-09 10:33     ` Gustavo Pimentel
2020-01-09 10:33       ` Gustavo Pimentel

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