* [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC
@ 2019-12-11 16:23 Jani Nikula
2019-12-11 16:23 ` [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders Jani Nikula
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Jani Nikula @ 2019-12-11 16:23 UTC (permalink / raw)
To: intel-gfx; +Cc: jani.nikula
This should bring the fi-icl-dsi host on CI back online. It's using the
wrong registers for DSC.
Unfortunately intel_dsc_power_domain() remains broken for DSI, for all
generations. The rabbit hole goes deeper; POWER_DOMAIN_TRANSCODER() is
also broken for DSI transcoders, beyond DSC and beyond the recent gens.
But let's start here.
BR,
Jani.
Jani Nikula (2):
drm/i915/dsc: fix DSC register selection for ICL DSI transcoders
drm/i915/dsc: clarify DSC support for pipe A on ICL
drivers/gpu/drm/i915/display/intel_vdsc.c | 66 +++++++++++++++--------
1 file changed, 45 insertions(+), 21 deletions(-)
--
2.20.1
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^ permalink raw reply [flat|nested] 18+ messages in thread* [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula @ 2019-12-11 16:23 ` Jani Nikula 2019-12-11 22:08 ` Manasi Navare 2019-12-11 16:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/dsc: clarify DSC support for pipe A on ICL Jani Nikula ` (7 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jani Nikula @ 2019-12-11 16:23 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula ICL eDP and DSI transcoders have a DSC engine separate from the pipe. Abstract the register selection and fix it for ICL. Add a warning for pipe A DSC on ICL; it does not exist. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 58 +++++++++++++++-------- 1 file changed, 38 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index ed9048140937..e6f60be9ee84 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -353,6 +353,26 @@ bool intel_dsc_source_support(struct intel_encoder *encoder, return false; } +static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) +{ + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + const struct drm_i915_private *i915 = to_i915(crtc->base.dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + + if (INTEL_GEN(i915) >= 12) + return true; + + if (cpu_transcoder == TRANSCODER_EDP || + cpu_transcoder == TRANSCODER_DSI_0 || + cpu_transcoder == TRANSCODER_DSI_1) + return false; + + /* There's no pipe A DSC engine on ICL */ + WARN_ON(crtc->pipe == PIPE_A); + + return true; +} + int intel_dsc_compute_params(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) { @@ -471,7 +491,6 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; enum pipe pipe = crtc->pipe; - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; u32 pps_val = 0; u32 rc_buf_thresh_dword[4]; u32 rc_range_params_dword[8]; @@ -492,7 +511,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, if (vdsc_cfg->vbr_enable) pps_val |= DSC_VBR_ENABLE; DRM_INFO("PPS0 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -511,7 +530,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val = 0; pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); DRM_INFO("PPS1 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -531,7 +550,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); DRM_INFO("PPS2 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -551,7 +570,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | DSC_SLICE_WIDTH(vdsc_cfg->slice_width); DRM_INFO("PPS3 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -571,7 +590,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); DRM_INFO("PPS4 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -591,7 +610,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); DRM_INFO("PPS5 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -613,7 +632,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); DRM_INFO("PPS6 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -633,7 +652,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); DRM_INFO("PPS7 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -653,7 +672,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); DRM_INFO("PPS8 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -673,7 +692,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); DRM_INFO("PPS9 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -695,7 +714,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); DRM_INFO("PPS10 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -718,7 +737,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / vdsc_cfg->slice_height); DRM_INFO("PPS16 = 0x%08x\n", pps_val); - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); /* * If 2 VDSC instances are needed, configure PPS for second @@ -742,7 +761,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, rc_buf_thresh_dword[i / 4]); } - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); @@ -791,7 +810,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, rc_range_params_dword[i / 2]); } - if (cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, rc_range_params_dword[0]); I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, @@ -870,7 +889,6 @@ void intel_dsc_get_config(struct intel_encoder *encoder, struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; enum pipe pipe = crtc->pipe; enum intel_display_power_domain power_domain; intel_wakeref_t wakeref; @@ -885,7 +903,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, if (!wakeref) return; - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { dss_ctl1 = I915_READ(DSS_CTL1); dss_ctl2 = I915_READ(DSS_CTL2); } else { @@ -903,7 +921,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, /* FIXME: add more state readout as needed */ /* PPS1 */ - if (cpu_transcoder == TRANSCODER_EDP) + if (!is_pipe_dsc(crtc_state)) val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); else val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); @@ -975,7 +993,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, else intel_dsc_dp_pps_write(encoder, crtc_state); - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(crtc_state)) { dss_ctl1_reg = DSS_CTL1; dss_ctl2_reg = DSS_CTL2; } else { @@ -1002,7 +1020,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) if (!old_crtc_state->dsc.compression_enable) return; - if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { + if (!is_pipe_dsc(old_crtc_state)) { dss_ctl1_reg = DSS_CTL1; dss_ctl2_reg = DSS_CTL2; } else { -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders 2019-12-11 16:23 ` [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders Jani Nikula @ 2019-12-11 22:08 ` Manasi Navare 2019-12-12 7:18 ` Jani Nikula 0 siblings, 1 reply; 18+ messages in thread From: Manasi Navare @ 2019-12-11 22:08 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Wed, Dec 11, 2019 at 06:23:46PM +0200, Jani Nikula wrote: > ICL eDP and DSI transcoders have a DSC engine separate from the > pipe. Abstract the register selection and fix it for ICL. > > Add a warning for pipe A DSC on ICL; it does not exist. > > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 58 +++++++++++++++-------- > 1 file changed, 38 insertions(+), 20 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index ed9048140937..e6f60be9ee84 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -353,6 +353,26 @@ bool intel_dsc_source_support(struct intel_encoder *encoder, > return false; > } > > +static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) > +{ > + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + const struct drm_i915_private *i915 = to_i915(crtc->base.dev); > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + > + if (INTEL_GEN(i915) >= 12) > + return true; > + > + if (cpu_transcoder == TRANSCODER_EDP || > + cpu_transcoder == TRANSCODER_DSI_0 || > + cpu_transcoder == TRANSCODER_DSI_1) > + return false; > + > + /* There's no pipe A DSC engine on ICL */ > + WARN_ON(crtc->pipe == PIPE_A); > + > + return true; > +} > + So for >=Gen12, it will always go to the else part in PPS configure and use ICL_DSC0_PICTURE_PARAMETER_SET_1 register per pipe. Right now this only calculates register addresses for PIPE_B and PIPE_C for ICL but no register defs for DSC_PPS for GEN >=12 As far as the selection logic this patch looks good and will work for <12 GEN , but it will currently fail for DSC on >=12 Lucas, Jose - Is thsi something anyone's looking at adding? Regards Manasi > int intel_dsc_compute_params(struct intel_encoder *encoder, > struct intel_crtc_state *pipe_config) > { > @@ -471,7 +491,6 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > enum pipe pipe = crtc->pipe; > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > u32 pps_val = 0; > u32 rc_buf_thresh_dword[4]; > u32 rc_range_params_dword[8]; > @@ -492,7 +511,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > if (vdsc_cfg->vbr_enable) > pps_val |= DSC_VBR_ENABLE; > DRM_INFO("PPS0 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -511,7 +530,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > pps_val = 0; > pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); > DRM_INFO("PPS1 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -531,7 +550,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > DRM_INFO("PPS2 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -551,7 +570,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | > DSC_SLICE_WIDTH(vdsc_cfg->slice_width); > DRM_INFO("PPS3 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -571,7 +590,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | > DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); > DRM_INFO("PPS4 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -591,7 +610,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | > DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); > DRM_INFO("PPS5 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -613,7 +632,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | > DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); > DRM_INFO("PPS6 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -633,7 +652,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | > DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); > DRM_INFO("PPS7 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -653,7 +672,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | > DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); > DRM_INFO("PPS8 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -673,7 +692,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | > DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); > DRM_INFO("PPS9 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -695,7 +714,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | > DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); > DRM_INFO("PPS10 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -718,7 +737,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / > vdsc_cfg->slice_height); > DRM_INFO("PPS16 = 0x%08x\n", pps_val); > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); > /* > * If 2 VDSC instances are needed, configure PPS for second > @@ -742,7 +761,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, > rc_buf_thresh_dword[i / 4]); > } > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); > I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); > I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); > @@ -791,7 +810,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, > rc_range_params_dword[i / 2]); > } > - if (cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, > rc_range_params_dword[0]); > I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, > @@ -870,7 +889,6 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > enum pipe pipe = crtc->pipe; > enum intel_display_power_domain power_domain; > intel_wakeref_t wakeref; > @@ -885,7 +903,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > if (!wakeref) > return; > > - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > dss_ctl1 = I915_READ(DSS_CTL1); > dss_ctl2 = I915_READ(DSS_CTL2); > } else { > @@ -903,7 +921,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > /* FIXME: add more state readout as needed */ > > /* PPS1 */ > - if (cpu_transcoder == TRANSCODER_EDP) > + if (!is_pipe_dsc(crtc_state)) > val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); > else > val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); > @@ -975,7 +993,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, > else > intel_dsc_dp_pps_write(encoder, crtc_state); > > - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(crtc_state)) { > dss_ctl1_reg = DSS_CTL1; > dss_ctl2_reg = DSS_CTL2; > } else { > @@ -1002,7 +1020,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) > if (!old_crtc_state->dsc.compression_enable) > return; > > - if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { > + if (!is_pipe_dsc(old_crtc_state)) { > dss_ctl1_reg = DSS_CTL1; > dss_ctl2_reg = DSS_CTL2; > } else { > -- > 2.20.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders 2019-12-11 22:08 ` Manasi Navare @ 2019-12-12 7:18 ` Jani Nikula 2019-12-12 22:05 ` Manasi Navare 0 siblings, 1 reply; 18+ messages in thread From: Jani Nikula @ 2019-12-12 7:18 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx On Wed, 11 Dec 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > On Wed, Dec 11, 2019 at 06:23:46PM +0200, Jani Nikula wrote: >> ICL eDP and DSI transcoders have a DSC engine separate from the >> pipe. Abstract the register selection and fix it for ICL. >> >> Add a warning for pipe A DSC on ICL; it does not exist. >> >> Cc: Manasi Navare <manasi.d.navare@intel.com> >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 58 +++++++++++++++-------- >> 1 file changed, 38 insertions(+), 20 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index ed9048140937..e6f60be9ee84 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -353,6 +353,26 @@ bool intel_dsc_source_support(struct intel_encoder *encoder, >> return false; >> } >> >> +static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) >> +{ >> + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); >> + const struct drm_i915_private *i915 = to_i915(crtc->base.dev); >> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> + >> + if (INTEL_GEN(i915) >= 12) >> + return true; >> + >> + if (cpu_transcoder == TRANSCODER_EDP || >> + cpu_transcoder == TRANSCODER_DSI_0 || >> + cpu_transcoder == TRANSCODER_DSI_1) >> + return false; >> + >> + /* There's no pipe A DSC engine on ICL */ >> + WARN_ON(crtc->pipe == PIPE_A); >> + >> + return true; >> +} >> + > > So for >=Gen12, it will always go to the else part in PPS configure and use > ICL_DSC0_PICTURE_PARAMETER_SET_1 register per pipe. FWIW, this was already the case for gen 12+, because there's no eDP transcoder. > Right now this only calculates register addresses for PIPE_B and PIPE_C for ICL but > no register defs for DSC_PPS for GEN >=12 > > As far as the selection logic this patch looks good and will work for <12 GEN , but it will > currently fail for DSC on >=12 > > Lucas, Jose - Is thsi something anyone's looking at adding? Oh, I failed to mention how subtle this is. It does work fine on all pipes on gen 12+. It's just that with pipe A, the index becomes (PIPE_A - PIPE_B) = -1, and it extrapolates the correct register offset, the other direction than usually. You see, gen 12 only has pipe DSC, with a DSC engine added to pipe A too, and no eDP/DSI specific DSC like ICL. Sure, the register definitions need an update, it's ugly and misleading, but it's not really broken for gen 12 pipe A. :) BR, Jani. > > Regards > Manasi > >> int intel_dsc_compute_params(struct intel_encoder *encoder, >> struct intel_crtc_state *pipe_config) >> { >> @@ -471,7 +491,6 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; >> enum pipe pipe = crtc->pipe; >> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> u32 pps_val = 0; >> u32 rc_buf_thresh_dword[4]; >> u32 rc_range_params_dword[8]; >> @@ -492,7 +511,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> if (vdsc_cfg->vbr_enable) >> pps_val |= DSC_VBR_ENABLE; >> DRM_INFO("PPS0 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -511,7 +530,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> pps_val = 0; >> pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); >> DRM_INFO("PPS1 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -531,7 +550,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | >> DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); >> DRM_INFO("PPS2 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -551,7 +570,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | >> DSC_SLICE_WIDTH(vdsc_cfg->slice_width); >> DRM_INFO("PPS3 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -571,7 +590,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | >> DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); >> DRM_INFO("PPS4 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -591,7 +610,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | >> DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); >> DRM_INFO("PPS5 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -613,7 +632,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | >> DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); >> DRM_INFO("PPS6 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -633,7 +652,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | >> DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); >> DRM_INFO("PPS7 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -653,7 +672,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | >> DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); >> DRM_INFO("PPS8 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -673,7 +692,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | >> DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); >> DRM_INFO("PPS9 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -695,7 +714,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | >> DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); >> DRM_INFO("PPS10 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -718,7 +737,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / >> vdsc_cfg->slice_height); >> DRM_INFO("PPS16 = 0x%08x\n", pps_val); >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); >> /* >> * If 2 VDSC instances are needed, configure PPS for second >> @@ -742,7 +761,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, >> rc_buf_thresh_dword[i / 4]); >> } >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); >> I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); >> I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); >> @@ -791,7 +810,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, >> rc_range_params_dword[i / 2]); >> } >> - if (cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, >> rc_range_params_dword[0]); >> I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, >> @@ -870,7 +889,6 @@ void intel_dsc_get_config(struct intel_encoder *encoder, >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); >> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); >> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> enum pipe pipe = crtc->pipe; >> enum intel_display_power_domain power_domain; >> intel_wakeref_t wakeref; >> @@ -885,7 +903,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, >> if (!wakeref) >> return; >> >> - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> dss_ctl1 = I915_READ(DSS_CTL1); >> dss_ctl2 = I915_READ(DSS_CTL2); >> } else { >> @@ -903,7 +921,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, >> /* FIXME: add more state readout as needed */ >> >> /* PPS1 */ >> - if (cpu_transcoder == TRANSCODER_EDP) >> + if (!is_pipe_dsc(crtc_state)) >> val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); >> else >> val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); >> @@ -975,7 +993,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, >> else >> intel_dsc_dp_pps_write(encoder, crtc_state); >> >> - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(crtc_state)) { >> dss_ctl1_reg = DSS_CTL1; >> dss_ctl2_reg = DSS_CTL2; >> } else { >> @@ -1002,7 +1020,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) >> if (!old_crtc_state->dsc.compression_enable) >> return; >> >> - if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { >> + if (!is_pipe_dsc(old_crtc_state)) { >> dss_ctl1_reg = DSS_CTL1; >> dss_ctl2_reg = DSS_CTL2; >> } else { >> -- >> 2.20.1 >> -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders 2019-12-12 7:18 ` Jani Nikula @ 2019-12-12 22:05 ` Manasi Navare 2019-12-13 0:53 ` Manasi Navare 0 siblings, 1 reply; 18+ messages in thread From: Manasi Navare @ 2019-12-12 22:05 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Thu, Dec 12, 2019 at 09:18:48AM +0200, Jani Nikula wrote: > On Wed, 11 Dec 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > > On Wed, Dec 11, 2019 at 06:23:46PM +0200, Jani Nikula wrote: > >> ICL eDP and DSI transcoders have a DSC engine separate from the > >> pipe. Abstract the register selection and fix it for ICL. > >> > >> Add a warning for pipe A DSC on ICL; it does not exist. > >> > >> Cc: Manasi Navare <manasi.d.navare@intel.com> > >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > >> --- > >> drivers/gpu/drm/i915/display/intel_vdsc.c | 58 +++++++++++++++-------- > >> 1 file changed, 38 insertions(+), 20 deletions(-) > >> > >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > >> index ed9048140937..e6f60be9ee84 100644 > >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > >> @@ -353,6 +353,26 @@ bool intel_dsc_source_support(struct intel_encoder *encoder, > >> return false; > >> } > >> > >> +static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) > >> +{ > >> + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > >> + const struct drm_i915_private *i915 = to_i915(crtc->base.dev); > >> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > >> + > >> + if (INTEL_GEN(i915) >= 12) > >> + return true; > >> + > >> + if (cpu_transcoder == TRANSCODER_EDP || > >> + cpu_transcoder == TRANSCODER_DSI_0 || > >> + cpu_transcoder == TRANSCODER_DSI_1) > >> + return false; > >> + > >> + /* There's no pipe A DSC engine on ICL */ > >> + WARN_ON(crtc->pipe == PIPE_A); > >> + > >> + return true; > >> +} > >> + > > > > So for >=Gen12, it will always go to the else part in PPS configure and use > > ICL_DSC0_PICTURE_PARAMETER_SET_1 register per pipe. > > FWIW, this was already the case for gen 12+, because there's no eDP > transcoder. > > > Right now this only calculates register addresses for PIPE_B and PIPE_C for ICL but > > no register defs for DSC_PPS for GEN >=12 > > > > As far as the selection logic this patch looks good and will work for <12 GEN , but it will > > currently fail for DSC on >=12 > > > > Lucas, Jose - Is thsi something anyone's looking at adding? > > Oh, I failed to mention how subtle this is. It does work fine on all > pipes on gen 12+. It's just that with pipe A, the index becomes (PIPE_A > - PIPE_B) = -1, and it extrapolates the correct register offset, the > other direction than usually. > > You see, gen 12 only has pipe DSC, with a DSC engine added to pipe A > too, and no eDP/DSI specific DSC like ICL. > > Sure, the register definitions need an update, it's ugly and misleading, > but it's not really broken for gen 12 pipe A. :) > > BR, > Jani. Okay, it will work for Pipe A agreed but IMO still broken for Pipe D that also has DSC now. Are you looking at fixing this for all pipes? Manasi > > > > > > Regards > > Manasi > > > >> int intel_dsc_compute_params(struct intel_encoder *encoder, > >> struct intel_crtc_state *pipe_config) > >> { > >> @@ -471,7 +491,6 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > >> enum pipe pipe = crtc->pipe; > >> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > >> u32 pps_val = 0; > >> u32 rc_buf_thresh_dword[4]; > >> u32 rc_range_params_dword[8]; > >> @@ -492,7 +511,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> if (vdsc_cfg->vbr_enable) > >> pps_val |= DSC_VBR_ENABLE; > >> DRM_INFO("PPS0 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -511,7 +530,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> pps_val = 0; > >> pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); > >> DRM_INFO("PPS1 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -531,7 +550,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > >> DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > >> DRM_INFO("PPS2 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -551,7 +570,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | > >> DSC_SLICE_WIDTH(vdsc_cfg->slice_width); > >> DRM_INFO("PPS3 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -571,7 +590,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | > >> DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); > >> DRM_INFO("PPS4 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -591,7 +610,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | > >> DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); > >> DRM_INFO("PPS5 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -613,7 +632,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | > >> DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); > >> DRM_INFO("PPS6 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -633,7 +652,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | > >> DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); > >> DRM_INFO("PPS7 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -653,7 +672,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | > >> DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); > >> DRM_INFO("PPS8 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -673,7 +692,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | > >> DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); > >> DRM_INFO("PPS9 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -695,7 +714,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | > >> DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); > >> DRM_INFO("PPS10 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -718,7 +737,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / > >> vdsc_cfg->slice_height); > >> DRM_INFO("PPS16 = 0x%08x\n", pps_val); > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); > >> /* > >> * If 2 VDSC instances are needed, configure PPS for second > >> @@ -742,7 +761,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, > >> rc_buf_thresh_dword[i / 4]); > >> } > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); > >> I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); > >> I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); > >> @@ -791,7 +810,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > >> DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, > >> rc_range_params_dword[i / 2]); > >> } > >> - if (cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, > >> rc_range_params_dword[0]); > >> I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, > >> @@ -870,7 +889,6 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > >> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > >> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > >> enum pipe pipe = crtc->pipe; > >> enum intel_display_power_domain power_domain; > >> intel_wakeref_t wakeref; > >> @@ -885,7 +903,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > >> if (!wakeref) > >> return; > >> > >> - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> dss_ctl1 = I915_READ(DSS_CTL1); > >> dss_ctl2 = I915_READ(DSS_CTL2); > >> } else { > >> @@ -903,7 +921,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > >> /* FIXME: add more state readout as needed */ > >> > >> /* PPS1 */ > >> - if (cpu_transcoder == TRANSCODER_EDP) > >> + if (!is_pipe_dsc(crtc_state)) > >> val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); > >> else > >> val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); > >> @@ -975,7 +993,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, > >> else > >> intel_dsc_dp_pps_write(encoder, crtc_state); > >> > >> - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(crtc_state)) { > >> dss_ctl1_reg = DSS_CTL1; > >> dss_ctl2_reg = DSS_CTL2; > >> } else { > >> @@ -1002,7 +1020,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) > >> if (!old_crtc_state->dsc.compression_enable) > >> return; > >> > >> - if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { > >> + if (!is_pipe_dsc(old_crtc_state)) { > >> dss_ctl1_reg = DSS_CTL1; > >> dss_ctl2_reg = DSS_CTL2; > >> } else { > >> -- > >> 2.20.1 > >> > > -- > Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders 2019-12-12 22:05 ` Manasi Navare @ 2019-12-13 0:53 ` Manasi Navare 0 siblings, 0 replies; 18+ messages in thread From: Manasi Navare @ 2019-12-13 0:53 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Thu, Dec 12, 2019 at 02:05:10PM -0800, Manasi Navare wrote: > On Thu, Dec 12, 2019 at 09:18:48AM +0200, Jani Nikula wrote: > > On Wed, 11 Dec 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > > > On Wed, Dec 11, 2019 at 06:23:46PM +0200, Jani Nikula wrote: > > >> ICL eDP and DSI transcoders have a DSC engine separate from the > > >> pipe. Abstract the register selection and fix it for ICL. > > >> > > >> Add a warning for pipe A DSC on ICL; it does not exist. > > >> > > >> Cc: Manasi Navare <manasi.d.navare@intel.com> > > >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > > >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> > > >> --- > > >> drivers/gpu/drm/i915/display/intel_vdsc.c | 58 +++++++++++++++-------- > > >> 1 file changed, 38 insertions(+), 20 deletions(-) > > >> > > >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > > >> index ed9048140937..e6f60be9ee84 100644 > > >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > > >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > > >> @@ -353,6 +353,26 @@ bool intel_dsc_source_support(struct intel_encoder *encoder, > > >> return false; > > >> } > > >> > > >> +static bool is_pipe_dsc(const struct intel_crtc_state *crtc_state) > > >> +{ > > >> + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > > >> + const struct drm_i915_private *i915 = to_i915(crtc->base.dev); > > >> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > >> + > > >> + if (INTEL_GEN(i915) >= 12) > > >> + return true; > > >> + > > >> + if (cpu_transcoder == TRANSCODER_EDP || > > >> + cpu_transcoder == TRANSCODER_DSI_0 || > > >> + cpu_transcoder == TRANSCODER_DSI_1) > > >> + return false; > > >> + > > >> + /* There's no pipe A DSC engine on ICL */ > > >> + WARN_ON(crtc->pipe == PIPE_A); > > >> + > > >> + return true; > > >> +} > > >> + > > > > > > So for >=Gen12, it will always go to the else part in PPS configure and use > > > ICL_DSC0_PICTURE_PARAMETER_SET_1 register per pipe. > > > > FWIW, this was already the case for gen 12+, because there's no eDP > > transcoder. > > > > > Right now this only calculates register addresses for PIPE_B and PIPE_C for ICL but > > > no register defs for DSC_PPS for GEN >=12 > > > > > > As far as the selection logic this patch looks good and will work for <12 GEN , but it will > > > currently fail for DSC on >=12 > > > > > > Lucas, Jose - Is thsi something anyone's looking at adding? > > > > Oh, I failed to mention how subtle this is. It does work fine on all > > pipes on gen 12+. It's just that with pipe A, the index becomes (PIPE_A > > - PIPE_B) = -1, and it extrapolates the correct register offset, the > > other direction than usually. > > > > You see, gen 12 only has pipe DSC, with a DSC engine added to pipe A > > too, and no eDP/DSI specific DSC like ICL. > > > > Sure, the register definitions need an update, it's ugly and misleading, > > but it's not really broken for gen 12 pipe A. :) > > > > BR, > > Jani. > > Okay, it will work for Pipe A agreed but IMO still broken for Pipe D that also has DSC now. > Are you looking at fixing this for all pipes? > > Manasi Actually I just did the register offsets calculations for DSC0_PPS and DSC1_PPS registers on TGL: And yes it does still work to give correct offsets for Pipe A-D but at some point we should rewrite it to look less of magic Manasi > > > > > > > > > > Regards > > > Manasi > > > > > >> int intel_dsc_compute_params(struct intel_encoder *encoder, > > >> struct intel_crtc_state *pipe_config) > > >> { > > >> @@ -471,7 +491,6 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > >> const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > > >> enum pipe pipe = crtc->pipe; > > >> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > >> u32 pps_val = 0; > > >> u32 rc_buf_thresh_dword[4]; > > >> u32 rc_range_params_dword[8]; > > >> @@ -492,7 +511,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> if (vdsc_cfg->vbr_enable) > > >> pps_val |= DSC_VBR_ENABLE; > > >> DRM_INFO("PPS0 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_0, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -511,7 +530,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> pps_val = 0; > > >> pps_val |= DSC_BPP(vdsc_cfg->bits_per_pixel); > > >> DRM_INFO("PPS1 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_1, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -531,7 +550,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> pps_val |= DSC_PIC_HEIGHT(vdsc_cfg->pic_height) | > > >> DSC_PIC_WIDTH(vdsc_cfg->pic_width / num_vdsc_instances); > > >> DRM_INFO("PPS2 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_2, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -551,7 +570,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> pps_val |= DSC_SLICE_HEIGHT(vdsc_cfg->slice_height) | > > >> DSC_SLICE_WIDTH(vdsc_cfg->slice_width); > > >> DRM_INFO("PPS3 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_3, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -571,7 +590,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> pps_val |= DSC_INITIAL_XMIT_DELAY(vdsc_cfg->initial_xmit_delay) | > > >> DSC_INITIAL_DEC_DELAY(vdsc_cfg->initial_dec_delay); > > >> DRM_INFO("PPS4 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_4, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -591,7 +610,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> pps_val |= DSC_SCALE_INC_INT(vdsc_cfg->scale_increment_interval) | > > >> DSC_SCALE_DEC_INT(vdsc_cfg->scale_decrement_interval); > > >> DRM_INFO("PPS5 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_5, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -613,7 +632,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> DSC_FLATNESS_MIN_QP(vdsc_cfg->flatness_min_qp) | > > >> DSC_FLATNESS_MAX_QP(vdsc_cfg->flatness_max_qp); > > >> DRM_INFO("PPS6 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_6, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -633,7 +652,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> pps_val |= DSC_SLICE_BPG_OFFSET(vdsc_cfg->slice_bpg_offset) | > > >> DSC_NFL_BPG_OFFSET(vdsc_cfg->nfl_bpg_offset); > > >> DRM_INFO("PPS7 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_7, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -653,7 +672,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> pps_val |= DSC_FINAL_OFFSET(vdsc_cfg->final_offset) | > > >> DSC_INITIAL_OFFSET(vdsc_cfg->initial_offset); > > >> DRM_INFO("PPS8 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_8, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -673,7 +692,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> pps_val |= DSC_RC_MODEL_SIZE(DSC_RC_MODEL_SIZE_CONST) | > > >> DSC_RC_EDGE_FACTOR(DSC_RC_EDGE_FACTOR_CONST); > > >> DRM_INFO("PPS9 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_9, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -695,7 +714,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> DSC_RC_TARGET_OFF_HIGH(DSC_RC_TGT_OFFSET_HI_CONST) | > > >> DSC_RC_TARGET_OFF_LOW(DSC_RC_TGT_OFFSET_LO_CONST); > > >> DRM_INFO("PPS10 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_10, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -718,7 +737,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> DSC_SLICE_ROW_PER_FRAME(vdsc_cfg->pic_height / > > >> vdsc_cfg->slice_height); > > >> DRM_INFO("PPS16 = 0x%08x\n", pps_val); > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_PICTURE_PARAMETER_SET_16, pps_val); > > >> /* > > >> * If 2 VDSC instances are needed, configure PPS for second > > >> @@ -742,7 +761,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> DRM_INFO(" RC_BUF_THRESH%d = 0x%08x\n", i, > > >> rc_buf_thresh_dword[i / 4]); > > >> } > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_RC_BUF_THRESH_0, rc_buf_thresh_dword[0]); > > >> I915_WRITE(DSCA_RC_BUF_THRESH_0_UDW, rc_buf_thresh_dword[1]); > > >> I915_WRITE(DSCA_RC_BUF_THRESH_1, rc_buf_thresh_dword[2]); > > >> @@ -791,7 +810,7 @@ static void intel_dsc_pps_configure(struct intel_encoder *encoder, > > >> DRM_INFO(" RC_RANGE_PARAM_%d = 0x%08x\n", i, > > >> rc_range_params_dword[i / 2]); > > >> } > > >> - if (cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0, > > >> rc_range_params_dword[0]); > > >> I915_WRITE(DSCA_RC_RANGE_PARAMETERS_0_UDW, > > >> @@ -870,7 +889,6 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > > >> struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); > > >> struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; > > >> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > > >> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > > >> enum pipe pipe = crtc->pipe; > > >> enum intel_display_power_domain power_domain; > > >> intel_wakeref_t wakeref; > > >> @@ -885,7 +903,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > > >> if (!wakeref) > > >> return; > > >> > > >> - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> dss_ctl1 = I915_READ(DSS_CTL1); > > >> dss_ctl2 = I915_READ(DSS_CTL2); > > >> } else { > > >> @@ -903,7 +921,7 @@ void intel_dsc_get_config(struct intel_encoder *encoder, > > >> /* FIXME: add more state readout as needed */ > > >> > > >> /* PPS1 */ > > >> - if (cpu_transcoder == TRANSCODER_EDP) > > >> + if (!is_pipe_dsc(crtc_state)) > > >> val = I915_READ(DSCA_PICTURE_PARAMETER_SET_1); > > >> else > > >> val = I915_READ(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe)); > > >> @@ -975,7 +993,7 @@ void intel_dsc_enable(struct intel_encoder *encoder, > > >> else > > >> intel_dsc_dp_pps_write(encoder, crtc_state); > > >> > > >> - if (crtc_state->cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(crtc_state)) { > > >> dss_ctl1_reg = DSS_CTL1; > > >> dss_ctl2_reg = DSS_CTL2; > > >> } else { > > >> @@ -1002,7 +1020,7 @@ void intel_dsc_disable(const struct intel_crtc_state *old_crtc_state) > > >> if (!old_crtc_state->dsc.compression_enable) > > >> return; > > >> > > >> - if (old_crtc_state->cpu_transcoder == TRANSCODER_EDP) { > > >> + if (!is_pipe_dsc(old_crtc_state)) { > > >> dss_ctl1_reg = DSS_CTL1; > > >> dss_ctl2_reg = DSS_CTL2; > > >> } else { > > >> -- > > >> 2.20.1 > > >> > > > > -- > > Jani Nikula, Intel Open Source Graphics Center > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915/dsc: clarify DSC support for pipe A on ICL 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula 2019-12-11 16:23 ` [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders Jani Nikula @ 2019-12-11 16:23 ` Jani Nikula 2019-12-11 21:43 ` Manasi Navare 2019-12-12 0:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsc: fixes for ICL DSI DSC Patchwork ` (6 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jani Nikula @ 2019-12-11 16:23 UTC (permalink / raw) To: intel-gfx; +Cc: jani.nikula The check for cpu_transcoder != TRANSCODER_A is more magic than necessary, and potentially misleading. Before TGL, DSC is supported on pipe A if, and only if, it's used with eDP or DSI transcoders. No functional changes. Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index e6f60be9ee84..41718f721484 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -337,7 +337,10 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp, bool intel_dsc_source_support(struct intel_encoder *encoder, const struct intel_crtc_state *crtc_state) { + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(encoder->base.dev); + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + enum pipe pipe = crtc->pipe; if (!INTEL_INFO(i915)->display.has_dsc) return false; @@ -347,7 +350,10 @@ bool intel_dsc_source_support(struct intel_encoder *encoder, return true; if (INTEL_GEN(i915) >= 10 && - crtc_state->cpu_transcoder != TRANSCODER_A) + (pipe != PIPE_A || + (cpu_transcoder == TRANSCODER_EDP || + cpu_transcoder == TRANSCODER_DSI_0 || + cpu_transcoder == TRANSCODER_DSI_1))) return true; return false; -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/dsc: clarify DSC support for pipe A on ICL 2019-12-11 16:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/dsc: clarify DSC support for pipe A on ICL Jani Nikula @ 2019-12-11 21:43 ` Manasi Navare 2019-12-12 7:27 ` Jani Nikula 0 siblings, 1 reply; 18+ messages in thread From: Manasi Navare @ 2019-12-11 21:43 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx On Wed, Dec 11, 2019 at 06:23:47PM +0200, Jani Nikula wrote: > The check for cpu_transcoder != TRANSCODER_A is more magic than > necessary, and potentially misleading. Before TGL, DSC is supported on > pipe A if, and only if, it's used with eDP or DSI transcoders. No > functional changes. > Hmm, so we could still use PIPE_A but if its eDP or DSI it would use TRANSCODER_EDP or TRANSCODER_DSI and that should still work? So its simpler to say that if it is PIPE_A && transcoder_A then it doesnt support DSC? Wouldnt it be simpler to change the condition to : if (INTEL_GEN(i915) >= 10 && !(pipe_A && transcode_A) return true; Regards Manasi > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +++++++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c > index e6f60be9ee84..41718f721484 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -337,7 +337,10 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp, > bool intel_dsc_source_support(struct intel_encoder *encoder, > const struct intel_crtc_state *crtc_state) > { > + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *i915 = to_i915(encoder->base.dev); > + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + enum pipe pipe = crtc->pipe; > > if (!INTEL_INFO(i915)->display.has_dsc) > return false; > @@ -347,7 +350,10 @@ bool intel_dsc_source_support(struct intel_encoder *encoder, > return true; > > if (INTEL_GEN(i915) >= 10 && > - crtc_state->cpu_transcoder != TRANSCODER_A) > + (pipe != PIPE_A || > + (cpu_transcoder == TRANSCODER_EDP || > + cpu_transcoder == TRANSCODER_DSI_0 || > + cpu_transcoder == TRANSCODER_DSI_1))) > return true; > > return false; > -- > 2.20.1 > _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915/dsc: clarify DSC support for pipe A on ICL 2019-12-11 21:43 ` Manasi Navare @ 2019-12-12 7:27 ` Jani Nikula 0 siblings, 0 replies; 18+ messages in thread From: Jani Nikula @ 2019-12-12 7:27 UTC (permalink / raw) To: Manasi Navare; +Cc: intel-gfx On Wed, 11 Dec 2019, Manasi Navare <manasi.d.navare@intel.com> wrote: > On Wed, Dec 11, 2019 at 06:23:47PM +0200, Jani Nikula wrote: >> The check for cpu_transcoder != TRANSCODER_A is more magic than >> necessary, and potentially misleading. Before TGL, DSC is supported on >> pipe A if, and only if, it's used with eDP or DSI transcoders. No >> functional changes. >> > > Hmm, so we could still use PIPE_A but if its eDP or DSI it would use > TRANSCODER_EDP or TRANSCODER_DSI and that should still work? Correct, because on gen 11 eDP/DSI have a DSC engine in front of the transcoder. > So its simpler to say that if it is PIPE_A && transcoder_A then it doesnt > support DSC? > Wouldnt it be simpler to change the condition to : > if (INTEL_GEN(i915) >= 10 && !(pipe_A && transcode_A) > return true; The simplest is really the code as it is... but it's not clear, and would deserve a comment. But I very much prefer self-documenting code over comments explaining surprising code. So I'd like to spell out the eDP/DSI transcoders here. BR, Jani. > > Regards > Manasi > >> Cc: Manasi Navare <manasi.d.navare@intel.com> >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 8 +++++++- >> 1 file changed, 7 insertions(+), 1 deletion(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index e6f60be9ee84..41718f721484 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -337,7 +337,10 @@ static const struct rc_parameters *get_rc_params(u16 compressed_bpp, >> bool intel_dsc_source_support(struct intel_encoder *encoder, >> const struct intel_crtc_state *crtc_state) >> { >> + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); >> struct drm_i915_private *i915 = to_i915(encoder->base.dev); >> + enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> + enum pipe pipe = crtc->pipe; >> >> if (!INTEL_INFO(i915)->display.has_dsc) >> return false; >> @@ -347,7 +350,10 @@ bool intel_dsc_source_support(struct intel_encoder *encoder, >> return true; >> >> if (INTEL_GEN(i915) >= 10 && >> - crtc_state->cpu_transcoder != TRANSCODER_A) >> + (pipe != PIPE_A || >> + (cpu_transcoder == TRANSCODER_EDP || >> + cpu_transcoder == TRANSCODER_DSI_0 || >> + cpu_transcoder == TRANSCODER_DSI_1))) >> return true; >> >> return false; >> -- >> 2.20.1 >> -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsc: fixes for ICL DSI DSC 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula 2019-12-11 16:23 ` [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders Jani Nikula 2019-12-11 16:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/dsc: clarify DSC support for pipe A on ICL Jani Nikula @ 2019-12-12 0:57 ` Patchwork 2019-12-12 9:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsc: fixes for ICL DSI DSC (rev2) Patchwork ` (5 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2019-12-12 0:57 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/dsc: fixes for ICL DSI DSC URL : https://patchwork.freedesktop.org/series/70770/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7545 -> Patchwork_15697 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15697 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15697, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15697: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live_gt_pm: - fi-kbl-x1275: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-kbl-x1275/igt@i915_selftest@live_gt_pm.html Known issues ------------ Here are the changes found in Patchwork_15697 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][2] -> [DMESG-FAIL][3] ([i915#722]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html * igt@kms_chamelium@dp-crc-fast: - fi-kbl-7500u: [PASS][4] -> [FAIL][5] ([fdo#109635] / [i915#262]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html #### Possible fixes #### * igt@gem_exec_parallel@basic: - {fi-tgl-guc}: [INCOMPLETE][6] ([i915#476]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-tgl-guc/igt@gem_exec_parallel@basic.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-tgl-guc/igt@gem_exec_parallel@basic.html * igt@i915_selftest@live_blt: - fi-hsw-4770: [DMESG-FAIL][8] ([i915#725]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-hsw-4770/igt@i915_selftest@live_blt.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-hsw-4770/igt@i915_selftest@live_blt.html - fi-hsw-4770r: [DMESG-FAIL][10] ([i915#553] / [i915#725]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-hsw-4770r/igt@i915_selftest@live_blt.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-hsw-4770r/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][12] ([fdo#111096] / [i915#323]) -> [PASS][13] [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html #### Warnings #### * igt@i915_module_load@reload: - fi-icl-u2: [DMESG-WARN][14] ([i915#109] / [i915#289]) -> [DMESG-WARN][15] ([i915#289]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-icl-u2/igt@i915_module_load@reload.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-icl-u2/igt@i915_module_load@reload.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy: - fi-kbl-x1275: [DMESG-WARN][16] ([i915#62] / [i915#92]) -> [DMESG-WARN][17] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-kbl-x1275/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][19] ([i915#62] / [i915#92]) +6 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7545/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#262]: https://gitlab.freedesktop.org/drm/intel/issues/262 [i915#289]: https://gitlab.freedesktop.org/drm/intel/issues/289 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (52 -> 47) ------------------------------ Additional (1): fi-kbl-7560u Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7545 -> Patchwork_15697 CI-20190529: 20190529 CI_DRM_7545: b1b808dff985c3c2050b20771050453589a60ca3 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5346: 466b0e6cbcbaccff012b484d1fd7676364b37b93 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15697: 5882f06b4c66abe2565092b7539fb6acc4ac272c @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 5882f06b4c66 drm/i915/dsc: clarify DSC support for pipe A on ICL 9cf81d2a431a drm/i915/dsc: fix DSC register selection for ICL DSI transcoders == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15697/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsc: fixes for ICL DSI DSC (rev2) 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula ` (2 preceding siblings ...) 2019-12-12 0:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsc: fixes for ICL DSI DSC Patchwork @ 2019-12-12 9:10 ` Patchwork 2019-12-12 11:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (4 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2019-12-12 9:10 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/dsc: fixes for ICL DSI DSC (rev2) URL : https://patchwork.freedesktop.org/series/70770/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7548 -> Patchwork_15709 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15709 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15709, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/index.html Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15709: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live_gt_pm: - fi-kbl-x1275: NOTRUN -> [DMESG-FAIL][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-kbl-x1275/igt@i915_selftest@live_gt_pm.html Known issues ------------ Here are the changes found in Patchwork_15709 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_pm_rpm@module-reload: - fi-skl-lmem: [PASS][2] -> [DMESG-WARN][3] ([i915#592]) [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live_blt: - fi-byt-j1900: [PASS][4] -> [DMESG-FAIL][5] ([i915#725]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-byt-j1900/igt@i915_selftest@live_blt.html [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-byt-j1900/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [PASS][6] -> [INCOMPLETE][7] ([i915#45]) [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html #### Possible fixes #### * igt@gem_exec_gttfill@basic: - {fi-tgl-u}: [INCOMPLETE][8] ([fdo#111593]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-tgl-u/igt@gem_exec_gttfill@basic.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-tgl-u/igt@gem_exec_gttfill@basic.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [DMESG-FAIL][10] ([i915#722]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html #### Warnings #### * igt@gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][12] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][13] ([i915#62] / [i915#92]) +5 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html * igt@i915_selftest@live_blt: - fi-ivb-3770: [DMESG-FAIL][14] ([i915#563]) -> [DMESG-FAIL][15] ([i915#725]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-ivb-3770/igt@i915_selftest@live_blt.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][16] ([fdo#111407]) -> [FAIL][17] ([fdo#111096] / [i915#323]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][18] ([i915#62] / [i915#92]) -> [DMESG-WARN][19] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7548 -> Patchwork_15709 CI-20190529: 20190529 CI_DRM_7548: 406e570d4e8be08530c7a7cad1e593d5347d1577 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5346: 466b0e6cbcbaccff012b484d1fd7676364b37b93 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15709: d6adc272da174dde62707c28bd0ea035f09bbd69 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d6adc272da17 drm/i915/dsc: clarify DSC support for pipe A on ICL e01fade65cc9 drm/i915/dsc: fix DSC register selection for ICL DSI transcoders == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: fixes for ICL DSI DSC (rev2) 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula ` (3 preceding siblings ...) 2019-12-12 9:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsc: fixes for ICL DSI DSC (rev2) Patchwork @ 2019-12-12 11:27 ` Patchwork 2019-12-12 13:47 ` [Intel-gfx] [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI Jani Nikula ` (3 subsequent siblings) 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2019-12-12 11:27 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/dsc: fixes for ICL DSI DSC (rev2) URL : https://patchwork.freedesktop.org/series/70770/ State : success == Summary == CI Bug Log - changes from CI_DRM_7548 -> Patchwork_15709 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/index.html Known issues ------------ Here are the changes found in Patchwork_15709 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_pm_rpm@module-reload: - fi-skl-lmem: [PASS][1] -> [DMESG-WARN][2] ([i915#592]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-skl-lmem/igt@i915_pm_rpm@module-reload.html * igt@i915_selftest@live_blt: - fi-byt-j1900: [PASS][3] -> [DMESG-FAIL][4] ([i915#725]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-byt-j1900/igt@i915_selftest@live_blt.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-byt-j1900/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_gem_contexts: - fi-byt-n2820: [PASS][5] -> [INCOMPLETE][6] ([i915#45]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-byt-n2820/igt@i915_selftest@live_gem_contexts.html #### Possible fixes #### * igt@gem_exec_gttfill@basic: - {fi-tgl-u}: [INCOMPLETE][7] ([fdo#111593]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-tgl-u/igt@gem_exec_gttfill@basic.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-tgl-u/igt@gem_exec_gttfill@basic.html * igt@i915_selftest@live_gem_contexts: - fi-byt-j1900: [DMESG-FAIL][9] ([i915#722]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-byt-j1900/igt@i915_selftest@live_gem_contexts.html #### Warnings #### * igt@gem_exec_suspend@basic-s3: - fi-kbl-x1275: [DMESG-WARN][11] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][12] ([i915#62] / [i915#92]) +5 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-kbl-x1275/igt@gem_exec_suspend@basic-s3.html * igt@i915_selftest@live_blt: - fi-ivb-3770: [DMESG-FAIL][13] ([i915#563]) -> [DMESG-FAIL][14] ([i915#725]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-ivb-3770/igt@i915_selftest@live_blt.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-ivb-3770/igt@i915_selftest@live_blt.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][15] ([fdo#111407]) -> [FAIL][16] ([fdo#111096] / [i915#323]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][17] ([i915#62] / [i915#92]) -> [DMESG-WARN][18] ([i915#62] / [i915#92] / [i915#95]) +8 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7548/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111407]: https://bugs.freedesktop.org/show_bug.cgi?id=111407 [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#45]: https://gitlab.freedesktop.org/drm/intel/issues/45 [i915#476]: https://gitlab.freedesktop.org/drm/intel/issues/476 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#592]: https://gitlab.freedesktop.org/drm/intel/issues/592 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (49 -> 43) ------------------------------ Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-ctg-p8600 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7548 -> Patchwork_15709 CI-20190529: 20190529 CI_DRM_7548: 406e570d4e8be08530c7a7cad1e593d5347d1577 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5346: 466b0e6cbcbaccff012b484d1fd7676364b37b93 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15709: d6adc272da174dde62707c28bd0ea035f09bbd69 @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == d6adc272da17 drm/i915/dsc: clarify DSC support for pipe A on ICL e01fade65cc9 drm/i915/dsc: fix DSC register selection for ICL DSI transcoders == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula ` (4 preceding siblings ...) 2019-12-12 11:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2019-12-12 13:47 ` Jani Nikula 2019-12-19 10:49 ` Kulkarni, Vandita 2019-12-12 13:48 ` [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula ` (2 subsequent siblings) 8 siblings, 1 reply; 18+ messages in thread From: Jani Nikula @ 2019-12-12 13:47 UTC (permalink / raw) To: Jani Nikula, intel-gfx Fix several issues with DSC power domains that did not take DSI transcoders into account: - On TGL+ we need to use PW2 for DSC on pipe A, not transcoder A. There is no longer an eDP transcoder, but there are two DSI transcoders which may be connected to pipe A. - On TGL+ we need to use the pipe, not transcoder, power domains for DSC on pipes other than A. Again, there are DSI transcoders. - On ICL we need to use PW2 for DSC also for DSI transcoders, not just for the eDP transcoder. Using is_pipe_dsc() also adds the warning about ICL pipe A DSC, which does not exist. Cc: José Roberto de Souza <jose.souza@intel.com> Cc: Manasi Navare <manasi.d.navare@intel.com> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> Signed-off-by: Jani Nikula <jani.nikula@intel.com> --- drivers/gpu/drm/i915/display/intel_vdsc.c | 28 ++++++++++++----------- 1 file changed, 15 insertions(+), 13 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c index 41718f721484..6bab08db5d75 100644 --- a/drivers/gpu/drm/i915/display/intel_vdsc.c +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c @@ -469,25 +469,27 @@ int intel_dsc_compute_params(struct intel_encoder *encoder, enum intel_display_power_domain intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) { - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); + struct drm_i915_private *i915 = to_i915(crtc->base.dev); + enum pipe pipe = crtc->pipe; /* - * On ICL VDSC/joining for eDP transcoder uses a separate power well, - * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain. - * For any other transcoder, VDSC/joining uses the power well associated - * with the pipe/transcoder in use. Hence another reference on the - * transcoder power domain will suffice. + * VDSC/joining uses a separate power well, PW2, and requires + * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two cases: * - * On TGL we have the same mapping, but for transcoder A (the special - * TRANSCODER_EDP is gone). + * - ICL eDP/DSI transcoder + * - TGL pipe A + * + * For any other pipe, VDSC/joining uses the power well associated with + * the pipe in use. Hence another reference on the pipe power domain + * will suffice. (Except no VDSC/joining on ICL pipe A.) */ - if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A) - return POWER_DOMAIN_TRANSCODER_VDSC_PW2; - else if (cpu_transcoder == TRANSCODER_EDP) + if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A) return POWER_DOMAIN_TRANSCODER_VDSC_PW2; + else if (is_pipe_dsc(crtc_state)) + return POWER_DOMAIN_PIPE(pipe); else - return POWER_DOMAIN_TRANSCODER(cpu_transcoder); + return POWER_DOMAIN_TRANSCODER_VDSC_PW2; } static void intel_dsc_pps_configure(struct intel_encoder *encoder, -- 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI 2019-12-12 13:47 ` [Intel-gfx] [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI Jani Nikula @ 2019-12-19 10:49 ` Kulkarni, Vandita 2019-12-19 13:26 ` Jani Nikula 0 siblings, 1 reply; 18+ messages in thread From: Kulkarni, Vandita @ 2019-12-19 10:49 UTC (permalink / raw) To: Nikula, Jani, Nikula, Jani, intel-gfx@lists.freedesktop.org > -----Original Message----- > From: Jani Nikula <jani.nikula@intel.com> > Sent: Thursday, December 12, 2019 7:17 PM > To: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org > Cc: Souza, Jose <jose.souza@intel.com>; Navare, Manasi D > <manasi.d.navare@intel.com>; Kulkarni, Vandita > <vandita.kulkarni@intel.com> > Subject: [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI > > Fix several issues with DSC power domains that did not take DSI transcoders > into account: > > - On TGL+ we need to use PW2 for DSC on pipe A, not transcoder A. There > is no longer an eDP transcoder, but there are two DSI transcoders > which may be connected to pipe A. > > - On TGL+ we need to use the pipe, not transcoder, power domains for DSC > on pipes other than A. Again, there are DSI transcoders. > > - On ICL we need to use PW2 for DSC also for DSI transcoders, not just > for the eDP transcoder. > > Using is_pipe_dsc() also adds the warning about ICL pipe A DSC, which does > not exist. > > Cc: José Roberto de Souza <jose.souza@intel.com> > Cc: Manasi Navare <manasi.d.navare@intel.com> > Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> > Signed-off-by: Jani Nikula <jani.nikula@intel.com> > --- > drivers/gpu/drm/i915/display/intel_vdsc.c | 28 ++++++++++++----------- > 1 file changed, 15 insertions(+), 13 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c > b/drivers/gpu/drm/i915/display/intel_vdsc.c > index 41718f721484..6bab08db5d75 100644 > --- a/drivers/gpu/drm/i915/display/intel_vdsc.c > +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c > @@ -469,25 +469,27 @@ int intel_dsc_compute_params(struct > intel_encoder *encoder, enum intel_display_power_domain > intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) { > - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); > - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; > + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > + struct drm_i915_private *i915 = to_i915(crtc->base.dev); > + enum pipe pipe = crtc->pipe; > > /* > - * On ICL VDSC/joining for eDP transcoder uses a separate power > well, > - * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 > power domain. > - * For any other transcoder, VDSC/joining uses the power well > associated > - * with the pipe/transcoder in use. Hence another reference on the > - * transcoder power domain will suffice. > + * VDSC/joining uses a separate power well, PW2, and requires > + * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two > cases: > * > - * On TGL we have the same mapping, but for transcoder A (the > special > - * TRANSCODER_EDP is gone). Comment in drivers/gpu/drm/i915/display/intel_display_power.h where POWER_DOMAIN_TRANSCODER_VDSC_PW2 is defined misses DSI transcoder. Rest all looks good to me. Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Thanks, Vandita > + * - ICL eDP/DSI transcoder > + * - TGL pipe A > + * > + * For any other pipe, VDSC/joining uses the power well associated > with > + * the pipe in use. Hence another reference on the pipe power > domain > + * will suffice. (Except no VDSC/joining on ICL pipe A.) > */ > - if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A) > - return POWER_DOMAIN_TRANSCODER_VDSC_PW2; > - else if (cpu_transcoder == TRANSCODER_EDP) > + if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A) > return POWER_DOMAIN_TRANSCODER_VDSC_PW2; > + else if (is_pipe_dsc(crtc_state)) > + return POWER_DOMAIN_PIPE(pipe); > else > - return POWER_DOMAIN_TRANSCODER(cpu_transcoder); > + return POWER_DOMAIN_TRANSCODER_VDSC_PW2; > } > > static void intel_dsc_pps_configure(struct intel_encoder *encoder, > -- > 2.20.1 _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI 2019-12-19 10:49 ` Kulkarni, Vandita @ 2019-12-19 13:26 ` Jani Nikula 0 siblings, 0 replies; 18+ messages in thread From: Jani Nikula @ 2019-12-19 13:26 UTC (permalink / raw) To: Kulkarni, Vandita, intel-gfx@lists.freedesktop.org On Thu, 19 Dec 2019, "Kulkarni, Vandita" <vandita.kulkarni@intel.com> wrote: >> -----Original Message----- >> From: Jani Nikula <jani.nikula@intel.com> >> Sent: Thursday, December 12, 2019 7:17 PM >> To: Nikula, Jani <jani.nikula@intel.com>; intel-gfx@lists.freedesktop.org >> Cc: Souza, Jose <jose.souza@intel.com>; Navare, Manasi D >> <manasi.d.navare@intel.com>; Kulkarni, Vandita >> <vandita.kulkarni@intel.com> >> Subject: [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI >> >> Fix several issues with DSC power domains that did not take DSI transcoders >> into account: >> >> - On TGL+ we need to use PW2 for DSC on pipe A, not transcoder A. There >> is no longer an eDP transcoder, but there are two DSI transcoders >> which may be connected to pipe A. >> >> - On TGL+ we need to use the pipe, not transcoder, power domains for DSC >> on pipes other than A. Again, there are DSI transcoders. >> >> - On ICL we need to use PW2 for DSC also for DSI transcoders, not just >> for the eDP transcoder. >> >> Using is_pipe_dsc() also adds the warning about ICL pipe A DSC, which does >> not exist. >> >> Cc: José Roberto de Souza <jose.souza@intel.com> >> Cc: Manasi Navare <manasi.d.navare@intel.com> >> Cc: Vandita Kulkarni <vandita.kulkarni@intel.com> >> Signed-off-by: Jani Nikula <jani.nikula@intel.com> >> --- >> drivers/gpu/drm/i915/display/intel_vdsc.c | 28 ++++++++++++----------- >> 1 file changed, 15 insertions(+), 13 deletions(-) >> >> diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c >> b/drivers/gpu/drm/i915/display/intel_vdsc.c >> index 41718f721484..6bab08db5d75 100644 >> --- a/drivers/gpu/drm/i915/display/intel_vdsc.c >> +++ b/drivers/gpu/drm/i915/display/intel_vdsc.c >> @@ -469,25 +469,27 @@ int intel_dsc_compute_params(struct >> intel_encoder *encoder, enum intel_display_power_domain >> intel_dsc_power_domain(const struct intel_crtc_state *crtc_state) { >> - struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); >> - enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; >> + struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); >> + struct drm_i915_private *i915 = to_i915(crtc->base.dev); >> + enum pipe pipe = crtc->pipe; >> >> /* >> - * On ICL VDSC/joining for eDP transcoder uses a separate power >> well, >> - * PW2. This requires POWER_DOMAIN_TRANSCODER_VDSC_PW2 >> power domain. >> - * For any other transcoder, VDSC/joining uses the power well >> associated >> - * with the pipe/transcoder in use. Hence another reference on the >> - * transcoder power domain will suffice. >> + * VDSC/joining uses a separate power well, PW2, and requires >> + * POWER_DOMAIN_TRANSCODER_VDSC_PW2 power domain in two >> cases: >> * >> - * On TGL we have the same mapping, but for transcoder A (the >> special >> - * TRANSCODER_EDP is gone). > > Comment in drivers/gpu/drm/i915/display/intel_display_power.h where > POWER_DOMAIN_TRANSCODER_VDSC_PW2 is defined misses DSI transcoder. I'll send a follow-up patch for this. > Rest all looks good to me. > Reviewed-by: Vandita Kulkarni <vandita.kulkarni@intel.com> Pushed the lot, thanks for the review. BR, Jani. > > Thanks, > Vandita > >> + * - ICL eDP/DSI transcoder >> + * - TGL pipe A >> + * >> + * For any other pipe, VDSC/joining uses the power well associated >> with >> + * the pipe in use. Hence another reference on the pipe power >> domain >> + * will suffice. (Except no VDSC/joining on ICL pipe A.) >> */ >> - if (INTEL_GEN(i915) >= 12 && cpu_transcoder == TRANSCODER_A) >> - return POWER_DOMAIN_TRANSCODER_VDSC_PW2; >> - else if (cpu_transcoder == TRANSCODER_EDP) >> + if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A) >> return POWER_DOMAIN_TRANSCODER_VDSC_PW2; >> + else if (is_pipe_dsc(crtc_state)) >> + return POWER_DOMAIN_PIPE(pipe); >> else >> - return POWER_DOMAIN_TRANSCODER(cpu_transcoder); >> + return POWER_DOMAIN_TRANSCODER_VDSC_PW2; >> } >> >> static void intel_dsc_pps_configure(struct intel_encoder *encoder, >> -- >> 2.20.1 > > _______________________________________________ > Intel-gfx mailing list > Intel-gfx@lists.freedesktop.org > https://lists.freedesktop.org/mailman/listinfo/intel-gfx -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula ` (5 preceding siblings ...) 2019-12-12 13:47 ` [Intel-gfx] [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI Jani Nikula @ 2019-12-12 13:48 ` Jani Nikula 2019-12-12 14:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: fixes for ICL DSI DSC (rev3) Patchwork 2019-12-13 4:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 8 siblings, 0 replies; 18+ messages in thread From: Jani Nikula @ 2019-12-12 13:48 UTC (permalink / raw) To: intel-gfx On Wed, 11 Dec 2019, Jani Nikula <jani.nikula@intel.com> wrote: > This should bring the fi-icl-dsi host on CI back online. It's using the > wrong registers for DSC. Confirmed by [1] for fi-icl-dsi. BR, Jani. [1] https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15709/index.html? -- Jani Nikula, Intel Open Source Graphics Center _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: fixes for ICL DSI DSC (rev3) 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula ` (6 preceding siblings ...) 2019-12-12 13:48 ` [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula @ 2019-12-12 14:08 ` Patchwork 2019-12-13 4:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2019-12-12 14:08 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/dsc: fixes for ICL DSI DSC (rev3) URL : https://patchwork.freedesktop.org/series/70770/ State : success == Summary == CI Bug Log - changes from CI_DRM_7549 -> Patchwork_15716 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/index.html Known issues ------------ Here are the changes found in Patchwork_15716 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@i915_selftest@live_gem_contexts: - fi-hsw-peppy: [PASS][1] -> [INCOMPLETE][2] ([i915#694]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html #### Possible fixes #### * igt@gem_exec_gttfill@basic: - {fi-tgl-u}: [INCOMPLETE][3] ([fdo#111593]) -> [PASS][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/fi-tgl-u/igt@gem_exec_gttfill@basic.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/fi-tgl-u/igt@gem_exec_gttfill@basic.html * igt@i915_selftest@live_blt: - fi-ivb-3770: [DMESG-FAIL][5] ([i915#563]) -> [PASS][6] [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/fi-ivb-3770/igt@i915_selftest@live_blt.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/fi-ivb-3770/igt@i915_selftest@live_blt.html - fi-hsw-4770: [DMESG-FAIL][7] ([i915#553] / [i915#725]) -> [PASS][8] [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/fi-hsw-4770/igt@i915_selftest@live_blt.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/fi-hsw-4770/igt@i915_selftest@live_blt.html * igt@i915_selftest@live_hangcheck: - fi-icl-u3: [INCOMPLETE][9] ([fdo#108569] / [i915#140]) -> [PASS][10] [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/fi-icl-u3/igt@i915_selftest@live_hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/fi-icl-u3/igt@i915_selftest@live_hangcheck.html * igt@kms_chamelium@hdmi-hpd-fast: - fi-kbl-7500u: [FAIL][11] ([fdo#111096] / [i915#323]) -> [PASS][12] [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html #### Warnings #### * igt@kms_busy@basic-flip-pipe-b: - fi-kbl-x1275: [DMESG-WARN][13] ([i915#62] / [i915#92]) -> [DMESG-WARN][14] ([i915#62] / [i915#92] / [i915#95]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/fi-kbl-x1275/igt@kms_busy@basic-flip-pipe-b.html * igt@kms_flip@basic-flip-vs-modeset: - fi-kbl-x1275: [DMESG-WARN][15] ([i915#62] / [i915#92] / [i915#95]) -> [DMESG-WARN][16] ([i915#62] / [i915#92]) +5 similar issues [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/fi-kbl-x1275/igt@kms_flip@basic-flip-vs-modeset.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108569]: https://bugs.freedesktop.org/show_bug.cgi?id=108569 [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096 [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593 [i915#140]: https://gitlab.freedesktop.org/drm/intel/issues/140 [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323 [i915#553]: https://gitlab.freedesktop.org/drm/intel/issues/553 [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563 [i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62 [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694 [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725 [i915#92]: https://gitlab.freedesktop.org/drm/intel/issues/92 [i915#95]: https://gitlab.freedesktop.org/drm/intel/issues/95 Participating hosts (48 -> 45) ------------------------------ Additional (3): fi-kbl-soraka fi-hsw-4770r fi-cfl-guc Missing (6): fi-ilk-m540 fi-byt-squawks fi-bsw-cyan fi-gdg-551 fi-byt-clapper fi-bdw-samus Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7549 -> Patchwork_15716 CI-20190529: 20190529 CI_DRM_7549: 9573e1b7d1cb54cc984cf5c4f93a743641d868da @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5346: 466b0e6cbcbaccff012b484d1fd7676364b37b93 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15716: 8a15e71913d540717adf4d39224ddf1319a17e4f @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 8a15e71913d5 drm/i915/dsc: clarify DSC support for pipe A on ICL 67b0f5c694b1 drm/i915/dsc: fix DSC register selection for ICL DSI transcoders == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dsc: fixes for ICL DSI DSC (rev3) 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula ` (7 preceding siblings ...) 2019-12-12 14:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: fixes for ICL DSI DSC (rev3) Patchwork @ 2019-12-13 4:38 ` Patchwork 8 siblings, 0 replies; 18+ messages in thread From: Patchwork @ 2019-12-13 4:38 UTC (permalink / raw) To: Jani Nikula; +Cc: intel-gfx == Series Details == Series: drm/i915/dsc: fixes for ICL DSI DSC (rev3) URL : https://patchwork.freedesktop.org/series/70770/ State : failure == Summary == CI Bug Log - changes from CI_DRM_7549_full -> Patchwork_15716_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_15716_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_15716_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_15716_full: ### IGT changes ### #### Possible regressions #### * igt@gem_exec_balancer@bonded-slice: - shard-iclb: [PASS][1] -> [FAIL][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb4/igt@gem_exec_balancer@bonded-slice.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb1/igt@gem_exec_balancer@bonded-slice.html Known issues ------------ Here are the changes found in Patchwork_15716_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_ctx_persistence@vecs0-mixed-process: - shard-apl: [PASS][3] -> [FAIL][4] ([i915#679]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-apl4/igt@gem_ctx_persistence@vecs0-mixed-process.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-apl2/igt@gem_ctx_persistence@vecs0-mixed-process.html * igt@gem_exec_parse_blt@allowed-all: - shard-kbl: [PASS][5] -> [DMESG-WARN][6] ([i915#716]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-kbl3/igt@gem_exec_parse_blt@allowed-all.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl1/igt@gem_exec_parse_blt@allowed-all.html * igt@gem_exec_schedule@preempt-hang-bsd: - shard-iclb: [PASS][7] -> [SKIP][8] ([fdo#112146]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb8/igt@gem_exec_schedule@preempt-hang-bsd.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb4/igt@gem_exec_schedule@preempt-hang-bsd.html * igt@gem_exec_suspend@basic-s0: - shard-iclb: [PASS][9] -> [DMESG-WARN][10] ([fdo#111764]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb1/igt@gem_exec_suspend@basic-s0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb2/igt@gem_exec_suspend@basic-s0.html * igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive: - shard-hsw: [PASS][11] -> [TIMEOUT][12] ([i915#530]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-hsw2/igt@gem_persistent_relocs@forked-interruptible-faulting-reloc-thrash-inactive.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#644]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-glk7/igt@gem_ppgtt@flink-and-close-vma-leak.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-glk1/igt@gem_ppgtt@flink-and-close-vma-leak.html - shard-tglb: [PASS][15] -> [FAIL][16] ([i915#644]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb1/igt@gem_ppgtt@flink-and-close-vma-leak.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb8/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@i915_pm_dc@dc5-dpms: - shard-iclb: [PASS][17] -> [FAIL][18] ([i915#447]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb2/igt@i915_pm_dc@dc5-dpms.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb3/igt@i915_pm_dc@dc5-dpms.html * igt@i915_selftest@mock_sanitycheck: - shard-skl: [PASS][19] -> [DMESG-WARN][20] ([i915#747]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl10/igt@i915_selftest@mock_sanitycheck.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl9/igt@i915_selftest@mock_sanitycheck.html * igt@i915_suspend@sysfs-reader: - shard-kbl: [PASS][21] -> [DMESG-WARN][22] ([i915#180]) +2 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-kbl7/igt@i915_suspend@sysfs-reader.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl7/igt@i915_suspend@sysfs-reader.html * igt@kms_color@pipe-b-ctm-0-5: - shard-skl: [PASS][23] -> [DMESG-WARN][24] ([i915#109]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl4/igt@kms_color@pipe-b-ctm-0-5.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl3/igt@kms_color@pipe-b-ctm-0-5.html * igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen: - shard-skl: [PASS][25] -> [FAIL][26] ([i915#54]) [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl3/igt@kms_cursor_crc@pipe-a-cursor-128x42-onscreen.html * igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled: - shard-skl: [PASS][27] -> [INCOMPLETE][28] ([i915#646] / [i915#667]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl4/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl9/igt@kms_draw_crc@draw-method-xrgb2101010-blt-untiled.html * igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled: - shard-skl: [PASS][29] -> [FAIL][30] ([i915#52] / [i915#54]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl7/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl5/igt@kms_draw_crc@draw-method-xrgb8888-render-ytiled.html * igt@kms_flip@flip-vs-expired-vblank: - shard-skl: [PASS][31] -> [FAIL][32] ([i915#79]) [31]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl8/igt@kms_flip@flip-vs-expired-vblank.html [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl1/igt@kms_flip@flip-vs-expired-vblank.html * igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite: - shard-tglb: [PASS][33] -> [FAIL][34] ([i915#49]) +1 similar issue [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb4/igt@kms_frontbuffer_tracking@fbc-1p-offscren-pri-shrfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt: - shard-tglb: [PASS][35] -> [INCOMPLETE][36] ([fdo#112393] / [i915#667]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb8/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb4/igt@kms_frontbuffer_tracking@psr-1p-primscrn-spr-indfb-draw-blt.html * igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b: - shard-tglb: [PASS][37] -> [INCOMPLETE][38] ([i915#456] / [i915#460]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb2/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb8/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-b.html * igt@kms_plane@pixel-format-pipe-b-planes: - shard-kbl: [PASS][39] -> [INCOMPLETE][40] ([fdo#103665] / [i915#648] / [i915#667]) +1 similar issue [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-kbl6/igt@kms_plane@pixel-format-pipe-b-planes.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl2/igt@kms_plane@pixel-format-pipe-b-planes.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes: - shard-snb: [PASS][41] -> [DMESG-WARN][42] ([i915#42]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-snb5/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-snb6/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [PASS][43] -> [FAIL][44] ([fdo#108145]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_psr2_su@page_flip: - shard-iclb: [PASS][45] -> [SKIP][46] ([fdo#109642] / [fdo#111068]) [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb2/igt@kms_psr2_su@page_flip.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb3/igt@kms_psr2_su@page_flip.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][47] -> [SKIP][48] ([fdo#109441]) [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb3/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_vblank@pipe-c-ts-continuation-suspend: - shard-apl: [PASS][49] -> [DMESG-WARN][50] ([i915#180]) +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-apl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-apl6/igt@kms_vblank@pipe-c-ts-continuation-suspend.html * igt@perf_pmu@idle-vcs1: - shard-iclb: [PASS][51] -> [SKIP][52] ([fdo#112080]) +2 similar issues [51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb4/igt@perf_pmu@idle-vcs1.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb6/igt@perf_pmu@idle-vcs1.html * igt@prime_busy@after-bsd2: - shard-iclb: [PASS][53] -> [SKIP][54] ([fdo#109276]) +4 similar issues [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb2/igt@prime_busy@after-bsd2.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb3/igt@prime_busy@after-bsd2.html #### Possible fixes #### * igt@gem_busy@extended-parallel-vcs1: - shard-iclb: [SKIP][55] ([fdo#112080]) -> [PASS][56] +1 similar issue [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb8/igt@gem_busy@extended-parallel-vcs1.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb4/igt@gem_busy@extended-parallel-vcs1.html * igt@gem_ctx_isolation@vcs1-s3: - shard-tglb: [INCOMPLETE][57] ([i915#456]) -> [PASS][58] [57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb3/igt@gem_ctx_isolation@vcs1-s3.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb2/igt@gem_ctx_isolation@vcs1-s3.html * igt@gem_eio@reset-stress: - shard-snb: [FAIL][59] ([i915#232]) -> [PASS][60] [59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-snb2/igt@gem_eio@reset-stress.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-snb7/igt@gem_eio@reset-stress.html * igt@gem_exec_async@concurrent-writes-bsd: - shard-iclb: [SKIP][61] ([fdo#112146]) -> [PASS][62] [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb4/igt@gem_exec_async@concurrent-writes-bsd.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb6/igt@gem_exec_async@concurrent-writes-bsd.html * igt@gem_exec_nop@basic-parallel: - shard-tglb: [INCOMPLETE][63] ([i915#435]) -> [PASS][64] [63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb4/igt@gem_exec_nop@basic-parallel.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb2/igt@gem_exec_nop@basic-parallel.html * igt@gem_exec_parallel@vcs1: - shard-tglb: [INCOMPLETE][65] ([fdo#111593]) -> [PASS][66] [65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb1/igt@gem_exec_parallel@vcs1.html [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb6/igt@gem_exec_parallel@vcs1.html * {igt@gem_exec_schedule@pi-common-bsd}: - shard-iclb: [SKIP][67] ([i915#677]) -> [PASS][68] [67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb4/igt@gem_exec_schedule@pi-common-bsd.html [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb6/igt@gem_exec_schedule@pi-common-bsd.html * igt@gem_exec_schedule@preempt-queue-bsd1: - shard-iclb: [SKIP][69] ([fdo#109276]) -> [PASS][70] +3 similar issues [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb8/igt@gem_exec_schedule@preempt-queue-bsd1.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb4/igt@gem_exec_schedule@preempt-queue-bsd1.html * igt@gem_exec_suspend@basic-s0: - shard-tglb: [INCOMPLETE][71] ([i915#456] / [i915#472]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb1/igt@gem_exec_suspend@basic-s0.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb8/igt@gem_exec_suspend@basic-s0.html * igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive: - shard-snb: [TIMEOUT][73] ([i915#530]) -> [PASS][74] [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-snb1/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-snb7/igt@gem_persistent_relocs@forked-faulting-reloc-thrash-inactive.html * igt@gem_persistent_relocs@forked-interruptible-thrashing: - shard-hsw: [FAIL][75] ([i915#520]) -> [PASS][76] [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-hsw4/igt@gem_persistent_relocs@forked-interruptible-thrashing.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-hsw6/igt@gem_persistent_relocs@forked-interruptible-thrashing.html * igt@gem_ppgtt@flink-and-close-vma-leak: - shard-kbl: [FAIL][77] ([i915#644]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-kbl4/igt@gem_ppgtt@flink-and-close-vma-leak.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl7/igt@gem_ppgtt@flink-and-close-vma-leak.html - shard-iclb: [FAIL][79] ([i915#644]) -> [PASS][80] [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb1/igt@gem_ppgtt@flink-and-close-vma-leak.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb2/igt@gem_ppgtt@flink-and-close-vma-leak.html * igt@gem_softpin@noreloc-s3: - shard-skl: [INCOMPLETE][81] ([i915#69]) -> [PASS][82] +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl8/igt@gem_softpin@noreloc-s3.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl2/igt@gem_softpin@noreloc-s3.html * igt@gem_userptr_blits@sync-unmap-after-close: - shard-snb: [DMESG-WARN][83] ([fdo#111870]) -> [PASS][84] [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-snb5/igt@gem_userptr_blits@sync-unmap-after-close.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-snb6/igt@gem_userptr_blits@sync-unmap-after-close.html * igt@kms_color@pipe-b-ctm-max: - shard-skl: [DMESG-WARN][85] ([i915#109]) -> [PASS][86] +1 similar issue [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl1/igt@kms_color@pipe-b-ctm-max.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl1/igt@kms_color@pipe-b-ctm-max.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding: - shard-skl: [FAIL][87] ([i915#54]) -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl2/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl4/igt@kms_cursor_crc@pipe-b-cursor-256x256-sliding.html * igt@kms_cursor_legacy@flip-vs-cursor-legacy: - shard-skl: [FAIL][89] ([IGT#5]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl6/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled: - shard-skl: [FAIL][91] ([i915#52] / [i915#54]) -> [PASS][92] [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl8/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl9/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-ytiled.html * igt@kms_flip@flip-vs-suspend-interruptible: - shard-snb: [DMESG-WARN][93] ([i915#42]) -> [PASS][94] [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-snb2/igt@kms_flip@flip-vs-suspend-interruptible.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-snb4/igt@kms_flip@flip-vs-suspend-interruptible.html * igt@kms_flip@plain-flip-interruptible: - shard-kbl: [INCOMPLETE][95] ([fdo#103665]) -> [PASS][96] [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-kbl7/igt@kms_flip@plain-flip-interruptible.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl4/igt@kms_flip@plain-flip-interruptible.html * igt@kms_frontbuffer_tracking@fbc-suspend: - shard-tglb: [INCOMPLETE][97] ([i915#456] / [i915#460] / [i915#474]) -> [PASS][98] [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb8/igt@kms_frontbuffer_tracking@fbc-suspend.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb5/igt@kms_frontbuffer_tracking@fbc-suspend.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt: - shard-tglb: [INCOMPLETE][99] ([i915#474] / [i915#667]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb4/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb1/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-indfb-pgflip-blt.html * igt@kms_plane@pixel-format-pipe-a-planes-source-clamping: - shard-skl: [INCOMPLETE][101] ([i915#648] / [i915#667]) -> [PASS][102] [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl9/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl2/igt@kms_plane@pixel-format-pipe-a-planes-source-clamping.html * igt@kms_plane@pixel-format-pipe-b-planes-source-clamping: - shard-kbl: [INCOMPLETE][103] ([fdo#103665] / [i915#435] / [i915#648] / [i915#667]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-kbl1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl1/igt@kms_plane@pixel-format-pipe-b-planes-source-clamping.html * igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes: - shard-apl: [DMESG-WARN][105] ([i915#180]) -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-apl4/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-apl2/igt@kms_plane@plane-panning-bottom-right-suspend-pipe-c-planes.html * igt@kms_psr2_su@frontbuffer: - shard-iclb: [SKIP][107] ([fdo#109642] / [fdo#111068]) -> [PASS][108] [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb4/igt@kms_psr2_su@frontbuffer.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb2/igt@kms_psr2_su@frontbuffer.html * igt@kms_psr@psr2_cursor_blt: - shard-iclb: [SKIP][109] ([fdo#109441]) -> [PASS][110] +1 similar issue [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-iclb1/igt@kms_psr@psr2_cursor_blt.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-iclb2/igt@kms_psr@psr2_cursor_blt.html * igt@kms_setmode@basic: - shard-glk: [FAIL][111] ([i915#31]) -> [PASS][112] [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-glk8/igt@kms_setmode@basic.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-glk4/igt@kms_setmode@basic.html * igt@kms_vblank@pipe-a-ts-continuation-suspend: - shard-kbl: [DMESG-WARN][113] ([i915#180]) -> [PASS][114] +6 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-kbl1/igt@kms_vblank@pipe-a-ts-continuation-suspend.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html * igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend: - shard-tglb: [INCOMPLETE][115] ([i915#460]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-tglb1/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-tglb2/igt@kms_vblank@pipe-d-ts-continuation-dpms-suspend.html #### Warnings #### * igt@kms_plane@pixel-format-pipe-b-planes: - shard-skl: [INCOMPLETE][117] ([fdo#112391] / [i915#648] / [i915#667]) -> [INCOMPLETE][118] ([fdo#112347] / [i915#648] / [i915#667]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl7/igt@kms_plane@pixel-format-pipe-b-planes.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl10/igt@kms_plane@pixel-format-pipe-b-planes.html * igt@runner@aborted: - shard-kbl: [FAIL][119] ([k.org#204565]) -> ([FAIL][120], [FAIL][121]) ([i915#716] / [k.org#204565]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-kbl6/igt@runner@aborted.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl1/igt@runner@aborted.html [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-kbl4/igt@runner@aborted.html - shard-skl: [FAIL][122] ([i915#69]) -> [FAIL][123] ([i915#69] / [k.org#204565]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7549/shard-skl4/igt@runner@aborted.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/shard-skl9/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [IGT#5]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/5 [fdo#103665]: https://bugs.freedesktop.org/show_bug.cgi?id=103665 [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109276]: https://bugs.freedesktop.org/show_bug.cgi?id=109276 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111593]: https://bugs.freedesktop.org/show_bug.cgi?id=111593 [fdo#111764]: https://bugs.freedesktop.org/show_bug.cgi?id=111764 [fdo#111870]: https://bugs.freedesktop.org/show_bug.cgi?id=111870 [fdo#112080]: https://bugs.freedesktop.org/show_bug.cgi?id=112080 [fdo#112146]: https://bugs.freedesktop.org/show_bug.cgi?id=112146 [fdo#112347]: https://bugs.freedesktop.org/show_bug.cgi?id=112347 [fdo#112391]: https://bugs.freedesktop.org/show_bug.cgi?id=112391 [fdo#112393]: https://bugs.freedesktop.org/show_bug.cgi?id=112393 [i915#109]: https://gitlab.freedesktop.org/drm/intel/issues/109 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#232]: https://gitlab.freedesktop.org/drm/intel/issues/232 [i915#31]: https://gitlab.freedesktop.org/drm/intel/issues/31 [i915#42]: https://gitlab.freedesktop.org/drm/intel/issues/42 [i915#435]: https://gitlab.freedesktop.org/drm/intel/issues/435 [i915#447]: https://gitlab.freedesktop.org/drm/intel/issues/447 [i915#456]: https://gitlab.freedesktop.org/drm/intel/issues/456 [i915#460]: https://gitlab.freedesktop.org/drm/intel/issues/460 [i915#472]: https://gitlab.freedesktop.org/drm/intel/issues/472 [i915#474]: https://gitlab.freedesktop.org/drm/intel/issues/474 [i915#49]: https://gitlab.freedesktop.org/drm/intel/issues/49 [i915#52]: https://gitlab.freedesktop.org/drm/intel/issues/52 [i915#520]: https://gitlab.freedesktop.org/drm/intel/issues/520 [i915#530]: https://gitlab.freedesktop.org/drm/intel/issues/530 [i915#54]: https://gitlab.freedesktop.org/drm/intel/issues/54 [i915#644]: https://gitlab.freedesktop.org/drm/intel/issues/644 [i915#646]: https://gitlab.freedesktop.org/drm/intel/issues/646 [i915#648]: https://gitlab.freedesktop.org/drm/intel/issues/648 [i915#667]: https://gitlab.freedesktop.org/drm/intel/issues/667 [i915#677]: https://gitlab.freedesktop.org/drm/intel/issues/677 [i915#679]: https://gitlab.freedesktop.org/drm/intel/issues/679 [i915#69]: https://gitlab.freedesktop.org/drm/intel/issues/69 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#747]: https://gitlab.freedesktop.org/drm/intel/issues/747 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 [k.org#204565]: https://bugzilla.kernel.org/show_bug.cgi?id=204565 Participating hosts (11 -> 11) ------------------------------ No changes in participating hosts Build changes ------------- * CI: CI-20190529 -> None * Linux: CI_DRM_7549 -> Patchwork_15716 CI-20190529: 20190529 CI_DRM_7549: 9573e1b7d1cb54cc984cf5c4f93a743641d868da @ git://anongit.freedesktop.org/gfx-ci/linux IGT_5346: 466b0e6cbcbaccff012b484d1fd7676364b37b93 @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools Patchwork_15716: 8a15e71913d540717adf4d39224ddf1319a17e4f @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_15716/index.html _______________________________________________ Intel-gfx mailing list Intel-gfx@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/intel-gfx ^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2019-12-19 13:26 UTC | newest] Thread overview: 18+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2019-12-11 16:23 [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula 2019-12-11 16:23 ` [Intel-gfx] [PATCH 1/2] drm/i915/dsc: fix DSC register selection for ICL DSI transcoders Jani Nikula 2019-12-11 22:08 ` Manasi Navare 2019-12-12 7:18 ` Jani Nikula 2019-12-12 22:05 ` Manasi Navare 2019-12-13 0:53 ` Manasi Navare 2019-12-11 16:23 ` [Intel-gfx] [PATCH 2/2] drm/i915/dsc: clarify DSC support for pipe A on ICL Jani Nikula 2019-12-11 21:43 ` Manasi Navare 2019-12-12 7:27 ` Jani Nikula 2019-12-12 0:57 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsc: fixes for ICL DSI DSC Patchwork 2019-12-12 9:10 ` [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/dsc: fixes for ICL DSI DSC (rev2) Patchwork 2019-12-12 11:27 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2019-12-12 13:47 ` [Intel-gfx] [PATCH 3/2] drm/i915/dsc: fix DSC power domains for DSI Jani Nikula 2019-12-19 10:49 ` Kulkarni, Vandita 2019-12-19 13:26 ` Jani Nikula 2019-12-12 13:48 ` [Intel-gfx] [PATCH 0/2] drm/i915/dsc: fixes for ICL DSI DSC Jani Nikula 2019-12-12 14:08 ` [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dsc: fixes for ICL DSI DSC (rev3) Patchwork 2019-12-13 4:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
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