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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Andres Rodriguez <andresx7@gmail.com>,
	Maling list - DRI developers <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 5/8] drm/edid: Document why we don't bounds check the DispID CEA block start/end
Date: Tue, 28 Jan 2020 13:44:04 +0200	[thread overview]
Message-ID: <20200128114404.GG13686@intel.com> (raw)
In-Reply-To: <CADnq5_MM5VHhZan=Q-NUjgvmyovg_33DjvNcZ3kO0=rxCkizQg@mail.gmail.com>

On Mon, Jan 27, 2020 at 05:30:42PM -0500, Alex Deucher wrote:
> On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > After much head scratching I managed to convince myself that
> > for_each_displayid_db() has already done the bounds checks for
> > the DispID CEA data block. Which is why we don't need to repeat
> > them in cea_db_offsets(). To avoid having to go through that
> > pain again in the future add a comment which explains this fact.
> >
> > Cc: Andres Rodriguez <andresx7@gmail.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/drm_edid.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 3df5744026b0..0369a54e3d32 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -4001,6 +4001,10 @@ cea_db_offsets(const u8 *cea, int *start, int *end)
> >          *   no non-DTD data.
> >          */
> >         if (cea[0] == DATA_BLOCK_CTA) {
> > +               /*
> > +                * for_each_displayid_db() has already verified
> > +                * that these stay within expected bounds.
> > +                */
> 
> I think the preferred format is to have the start of the comment be on
> the first line after the /* with that fixed:

Nope.

> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> 
> >                 *start = 3;
> >                 *end = *start + cea[2];
> >         } else if (cea[0] == CEA_EXT) {
> > --
> > 2.24.1
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Ville Syrjälä
Intel
_______________________________________________
dri-devel mailing list
dri-devel@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/dri-devel

WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: Alex Deucher <alexdeucher@gmail.com>
Cc: Intel Graphics Development <intel-gfx@lists.freedesktop.org>,
	Andres Rodriguez <andresx7@gmail.com>,
	Maling list - DRI developers <dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 5/8] drm/edid: Document why we don't bounds check the DispID CEA block start/end
Date: Tue, 28 Jan 2020 13:44:04 +0200	[thread overview]
Message-ID: <20200128114404.GG13686@intel.com> (raw)
In-Reply-To: <CADnq5_MM5VHhZan=Q-NUjgvmyovg_33DjvNcZ3kO0=rxCkizQg@mail.gmail.com>

On Mon, Jan 27, 2020 at 05:30:42PM -0500, Alex Deucher wrote:
> On Fri, Jan 24, 2020 at 3:03 PM Ville Syrjala
> <ville.syrjala@linux.intel.com> wrote:
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > After much head scratching I managed to convince myself that
> > for_each_displayid_db() has already done the bounds checks for
> > the DispID CEA data block. Which is why we don't need to repeat
> > them in cea_db_offsets(). To avoid having to go through that
> > pain again in the future add a comment which explains this fact.
> >
> > Cc: Andres Rodriguez <andresx7@gmail.com>
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> >  drivers/gpu/drm/drm_edid.c | 4 ++++
> >  1 file changed, 4 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/drm_edid.c b/drivers/gpu/drm/drm_edid.c
> > index 3df5744026b0..0369a54e3d32 100644
> > --- a/drivers/gpu/drm/drm_edid.c
> > +++ b/drivers/gpu/drm/drm_edid.c
> > @@ -4001,6 +4001,10 @@ cea_db_offsets(const u8 *cea, int *start, int *end)
> >          *   no non-DTD data.
> >          */
> >         if (cea[0] == DATA_BLOCK_CTA) {
> > +               /*
> > +                * for_each_displayid_db() has already verified
> > +                * that these stay within expected bounds.
> > +                */
> 
> I think the preferred format is to have the start of the comment be on
> the first line after the /* with that fixed:

Nope.

> Acked-by: Alex Deucher <alexander.deucher@amd.com>
> 
> >                 *start = 3;
> >                 *end = *start + cea[2];
> >         } else if (cea[0] == CEA_EXT) {
> > --
> > 2.24.1
> >
> > _______________________________________________
> > dri-devel mailing list
> > dri-devel@lists.freedesktop.org
> > https://lists.freedesktop.org/mailman/listinfo/dri-devel

-- 
Ville Syrjälä
Intel
_______________________________________________
Intel-gfx mailing list
Intel-gfx@lists.freedesktop.org
https://lists.freedesktop.org/mailman/listinfo/intel-gfx

  reply	other threads:[~2020-01-28 11:44 UTC|newest]

Thread overview: 67+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-01-24 20:02 [PATCH 1/8] drm/edid: Check the number of detailed timing descriptors in the CEA ext block Ville Syrjala
2020-01-24 20:02 ` [Intel-gfx] " Ville Syrjala
2020-01-24 20:02 ` [PATCH 2/8] drm/edid: Don't accept any old garbage as a display descriptor Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:35   ` Alex Deucher
2020-01-27 22:35     ` [Intel-gfx] " Alex Deucher
2020-02-03 19:44     ` Shankar, Uma
2020-02-03 19:44       ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 3/8] drm/edid: Introduce is_detailed_timing_descritor() Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:36   ` Alex Deucher
2020-01-27 22:36     ` [Intel-gfx] " Alex Deucher
2020-02-03 19:49     ` Shankar, Uma
2020-02-03 19:49       ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 4/8] drm/i915: Clear out spurious whitespace Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:28   ` Alex Deucher
2020-01-27 22:28     ` [Intel-gfx] " Alex Deucher
2020-02-03 19:51     ` Shankar, Uma
2020-02-03 19:51       ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 5/8] drm/edid: Document why we don't bounds check the DispID CEA block start/end Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:30   ` Alex Deucher
2020-01-27 22:30     ` [Intel-gfx] " Alex Deucher
2020-01-28 11:44     ` Ville Syrjälä [this message]
2020-01-28 11:44       ` Ville Syrjälä
2020-02-03 19:58       ` Shankar, Uma
2020-02-03 19:58         ` [Intel-gfx] " Shankar, Uma
2020-01-24 20:02 ` [PATCH 6/8] drm/edid: Add a FIXME about DispID CEA data block revision Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:32   ` Alex Deucher
2020-01-27 22:32     ` [Intel-gfx] " Alex Deucher
2020-02-03 20:15   ` Shankar, Uma
2020-02-03 20:15     ` Shankar, Uma
2020-02-04 13:32     ` Ville Syrjälä
2020-02-04 13:32       ` Ville Syrjälä
2020-02-04 14:57       ` Shankar, Uma
2020-02-04 14:57         ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 7/8] drm/edid: Constify lots of things Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:38   ` Alex Deucher
2020-01-27 22:38     ` [Intel-gfx] " Alex Deucher
2020-01-28 11:49     ` Ville Syrjälä
2020-01-28 11:49       ` [Intel-gfx] " Ville Syrjälä
2020-02-03 20:34       ` Shankar, Uma
2020-02-03 20:34         ` Shankar, Uma
2020-01-24 20:02 ` [PATCH 8/8] drm/edid: Dump bogus 18 byte descriptors Ville Syrjala
2020-01-24 20:02   ` [Intel-gfx] " Ville Syrjala
2020-01-27 22:38   ` Alex Deucher
2020-01-27 22:38     ` [Intel-gfx] " Alex Deucher
2020-02-03 20:38     ` Shankar, Uma
2020-02-03 20:38       ` Shankar, Uma
2020-01-24 22:53 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for series starting with [1/8] drm/edid: Check the number of detailed timing descriptors in the CEA ext block Patchwork
2020-01-24 23:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2020-01-27 13:49 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2020-01-27 22:34 ` [PATCH 1/8] " Alex Deucher
2020-01-27 22:34   ` [Intel-gfx] " Alex Deucher
2020-02-03 19:15   ` Shankar, Uma
2020-02-03 19:15     ` [Intel-gfx] " Shankar, Uma
2020-01-28 15:17 ` Daniel Vetter
2020-01-28 15:17   ` [Intel-gfx] " Daniel Vetter
2020-01-28 16:15   ` Ville Syrjälä
2020-01-28 16:15     ` [Intel-gfx] " Ville Syrjälä
2020-01-28 16:18     ` Daniel Vetter
2020-01-28 16:18       ` [Intel-gfx] " Daniel Vetter
2020-01-28 16:28       ` Ville Syrjälä
2020-01-28 16:28         ` [Intel-gfx] " Ville Syrjälä

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