[Intel-gfx] [PATCH 1/2] drm/i915: extract engine WA programming to common resume function

[Intel-gfx] [PATCH 1/2] drm/i915: extract engine WA programming to common resume function

[Daniele Ceraolo Spurio]

The workarounds are a common "feature" across gens and submission
mechanisms and we already call the other WA related functions from
common engine ones (<setup/cleanup>_common), so it makes sense to
do the same with WA application. Medium-term, This will help us
reduce the duplication once the GuC resume function is added, but short
term it will also allow us to use the workaround lists for pre-gen8
engine workarounds.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Matthew Brost <matthew.brost@intel.com>
---
 drivers/gpu/drm/i915/gt/intel_engine.h    |  2 ++
 drivers/gpu/drm/i915/gt/intel_engine_cs.c | 14 ++++++++++++++
 drivers/gpu/drm/i915/gt/intel_gt_pm.c     |  2 +-
 drivers/gpu/drm/i915/gt/intel_lrc.c       |  3 ---
 drivers/gpu/drm/i915/gt/intel_reset.c     |  4 ++--
 5 files changed, 19 insertions(+), 6 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_engine.h b/drivers/gpu/drm/i915/gt/intel_engine.h
index 5df003061e44..b36ec1fddc3d 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine.h
@@ -192,6 +192,8 @@ void intel_engines_free(struct intel_gt *gt);
 int intel_engine_init_common(struct intel_engine_cs *engine);
 void intel_engine_cleanup_common(struct intel_engine_cs *engine);
 
+int intel_engine_resume(struct intel_engine_cs *engine);
+
 int intel_ring_submission_setup(struct intel_engine_cs *engine);
 
 int intel_engine_stop_cs(struct intel_engine_cs *engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 39fe9a5b4820..c7435475bc75 100644
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -841,6 +841,20 @@ void intel_engine_cleanup_common(struct intel_engine_cs *engine)
 	intel_wa_list_free(&engine->whitelist);
 }
 
+/**
+ * intel_engine_resume - re-initializes the HW state of the engine
+ * @engine: Engine to resume.
+ *
+ * Returns zero on success or an error code on failure.
+ */
+int intel_engine_resume(struct intel_engine_cs *engine)
+{
+	intel_engine_apply_workarounds(engine);
+	intel_engine_apply_whitelist(engine);
+
+	return engine->resume(engine);
+}
+
 u64 intel_engine_get_active_head(const struct intel_engine_cs *engine)
 {
 	struct drm_i915_private *i915 = engine->i915;
diff --git a/drivers/gpu/drm/i915/gt/intel_gt_pm.c b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
index d1c2f034296a..8b653c0f5e5f 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt_pm.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt_pm.c
@@ -216,7 +216,7 @@ int intel_gt_resume(struct intel_gt *gt)
 		intel_engine_pm_get(engine);
 
 		engine->serial++; /* kernel context lost */
-		err = engine->resume(engine);
+		err = intel_engine_resume(engine);
 
 		intel_engine_pm_put(engine);
 		if (err) {
diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 8f15ab7d8d88..601f65bd93b5 100644
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -3431,9 +3431,6 @@ static bool unexpected_starting_state(struct intel_engine_cs *engine)
 
 static int execlists_resume(struct intel_engine_cs *engine)
 {
-	intel_engine_apply_workarounds(engine);
-	intel_engine_apply_whitelist(engine);
-
 	intel_mocs_init_engine(engine);
 
 	intel_engine_reset_breadcrumbs(engine);
diff --git a/drivers/gpu/drm/i915/gt/intel_reset.c b/drivers/gpu/drm/i915/gt/intel_reset.c
index ea983eff0e4e..6d720c4648d0 100644
--- a/drivers/gpu/drm/i915/gt/intel_reset.c
+++ b/drivers/gpu/drm/i915/gt/intel_reset.c
@@ -982,7 +982,7 @@ static int resume(struct intel_gt *gt)
 	int ret;
 
 	for_each_engine(engine, gt, id) {
-		ret = engine->resume(engine);
+		ret = intel_engine_resume(engine);
 		if (ret)
 			return ret;
 	}
@@ -1157,7 +1157,7 @@ int intel_engine_reset(struct intel_engine_cs *engine, const char *msg)
 	 * have been reset to their default values. Follow the init_ring
 	 * process to program RING_MODE, HWSP and re-enable submission.
 	 */
-	ret = engine->resume(engine);
+	ret = intel_engine_resume(engine);
 
 out:
 	intel_engine_cancel_stop_cs(engine);
-- 
2.24.1

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[Intel-gfx] [PATCH 2/2] drm/i915: Move ringbuffer WAs to engine workaround list

[Daniele Ceraolo Spurio]

Now that intel_engine_apply_workarounds is called on all gens, we can
use the engine workaround lists for pre-gen8 workarounds as well to be
consistent in the way we handle and dump the WAs.

Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Cc: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
---
 .../gpu/drm/i915/gt/intel_ring_submission.c   | 37 -------------
 drivers/gpu/drm/i915/gt/intel_workarounds.c   | 55 ++++++++++++++++++-
 2 files changed, 53 insertions(+), 39 deletions(-)

diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 7e2c6ac7d6b0..6639032dab68 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -858,43 +858,6 @@ static int rcs_resume(struct intel_engine_cs *engine)
 		intel_uncore_write(uncore, ECOSKPD,
 			   _MASKED_BIT_ENABLE(ECO_CONSTANT_BUFFER_SR_DISABLE));
 
-	/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
-	if (IS_GEN_RANGE(i915, 4, 6))
-		intel_uncore_write(uncore, MI_MODE,
-				   _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
-
-	/* We need to disable the AsyncFlip performance optimisations in order
-	 * to use MI_WAIT_FOR_EVENT within the CS. It should already be
-	 * programmed to '1' on all products.
-	 *
-	 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
-	 */
-	if (IS_GEN_RANGE(i915, 6, 7))
-		intel_uncore_write(uncore, MI_MODE,
-				   _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
-
-	/* Required for the hardware to program scanline values for waiting */
-	/* WaEnableFlushTlbInvalidationMode:snb */
-	if (IS_GEN(i915, 6))
-		intel_uncore_write(uncore, GFX_MODE,
-			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT));
-
-	/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
-	if (IS_GEN(i915, 7))
-		intel_uncore_write(uncore, GFX_MODE_GEN7,
-			   _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_EXPLICIT) |
-			   _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
-
-	if (IS_GEN(i915, 6)) {
-		/* From the Sandybridge PRM, volume 1 part 3, page 24:
-		 * "If this bit is set, STCunit will have LRA as replacement
-		 *  policy. [...] This bit must be reset.  LRA replacement
-		 *  policy is not supported."
-		 */
-		intel_uncore_write(uncore, CACHE_MODE_0,
-			   _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
-	}
-
 	if (IS_GEN_RANGE(i915, 6, 7))
 		intel_uncore_write(uncore, INSTPM,
 				   _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
diff --git a/drivers/gpu/drm/i915/gt/intel_workarounds.c b/drivers/gpu/drm/i915/gt/intel_workarounds.c
index 5a7db279f702..07764bd1d9c9 100644
--- a/drivers/gpu/drm/i915/gt/intel_workarounds.c
+++ b/drivers/gpu/drm/i915/gt/intel_workarounds.c
@@ -173,6 +173,12 @@ wa_masked_en(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 	wa_write_masked_or(wal, reg, val, _MASKED_BIT_ENABLE(val));
 }
 
+static void
+wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
+{
+	wa_write_masked_or(wal, reg, val, _MASKED_BIT_DISABLE(val));
+}
+
 static void
 wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
 {
@@ -1457,6 +1463,51 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 			    GEN8_L3SQCREG4,
 			    GEN8_LQSC_FLUSH_COHERENT_LINES);
 	}
+
+	if (IS_GEN(i915, 7))
+		/* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
+		wa_masked_en(wal,
+			     GFX_MODE_GEN7,
+			     GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
+
+	if (IS_GEN_RANGE(i915, 6, 7))
+		/*
+		 * We need to disable the AsyncFlip performance optimisations in
+		 * order to use MI_WAIT_FOR_EVENT within the CS. It should
+		 * already be programmed to '1' on all products.
+		 *
+		 * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
+		 */
+		wa_masked_en(wal,
+			     MI_MODE,
+			     ASYNC_FLIP_PERF_DISABLE);
+
+	if (IS_GEN(i915, 6)) {
+		/*
+		 * Required for the hardware to program scanline values for
+		 * waiting
+		 * WaEnableFlushTlbInvalidationMode:snb
+		 */
+		wa_masked_en(wal,
+			     GFX_MODE,
+			     GFX_TLB_INVALIDATE_EXPLICIT);
+
+		/*
+		 * From the Sandybridge PRM, volume 1 part 3, page 24:
+		 * "If this bit is set, STCunit will have LRA as replacement
+		 *  policy. [...] This bit must be reset. LRA replacement
+		 *  policy is not supported."
+		 */
+		wa_masked_dis(wal,
+			      CACHE_MODE_0,
+			      CM0_STC_EVICT_DISABLE_LRA_SNB);
+	}
+
+	if (IS_GEN_RANGE(i915, 4, 6))
+		/* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
+		wa_masked_en(wal,
+			     MI_MODE,
+			     VS_TIMER_DISPATCH);
 }
 
 static void
@@ -1475,7 +1526,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 static void
 engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
 {
-	if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
+	if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
 		return;
 
 	if (engine->class == RENDER_CLASS)
@@ -1488,7 +1539,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
 {
 	struct i915_wa_list *wal = &engine->wa_list;
 
-	if (INTEL_GEN(engine->i915) < 8)
+	if (INTEL_GEN(engine->i915) < 4)
 		return;
 
 	wa_init_start(wal, "engine", engine->name);
-- 
2.24.1

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Re: [Intel-gfx] [PATCH 2/2] drm/i915: Move ringbuffer WAs to engine workaround list

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2020-01-29 23:59:00)
> Now that intel_engine_apply_workarounds is called on all gens, we can
> use the engine workaround lists for pre-gen8 workarounds as well to be
> consistent in the way we handle and dump the WAs.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>

If you go looking, you'll find plenty more gen2-7 w/a scattered about
the place.

> +static void
> +wa_masked_dis(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
> +{
> +       wa_write_masked_or(wal, reg, val, _MASKED_BIT_DISABLE(val));
> +}
> +
>  static void
>  wa_write(struct i915_wa_list *wal, i915_reg_t reg, u32 val)
>  {
> @@ -1457,6 +1463,51 @@ rcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>                             GEN8_L3SQCREG4,
>                             GEN8_LQSC_FLUSH_COHERENT_LINES);
>         }
> +
> +       if (IS_GEN(i915, 7))
> +               /* WaBCSVCSTlbInvalidationMode:ivb,vlv,hsw */
> +               wa_masked_en(wal,
> +                            GFX_MODE_GEN7,
> +                            GFX_TLB_INVALIDATE_EXPLICIT | GFX_REPLAY_MODE);
> +
> +       if (IS_GEN_RANGE(i915, 6, 7))
> +               /*
> +                * We need to disable the AsyncFlip performance optimisations in
> +                * order to use MI_WAIT_FOR_EVENT within the CS. It should
> +                * already be programmed to '1' on all products.
> +                *
> +                * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
> +                */
> +               wa_masked_en(wal,
> +                            MI_MODE,
> +                            ASYNC_FLIP_PERF_DISABLE);
> +
> +       if (IS_GEN(i915, 6)) {
> +               /*
> +                * Required for the hardware to program scanline values for
> +                * waiting
> +                * WaEnableFlushTlbInvalidationMode:snb
> +                */
> +               wa_masked_en(wal,
> +                            GFX_MODE,
> +                            GFX_TLB_INVALIDATE_EXPLICIT);
> +
> +               /*
> +                * From the Sandybridge PRM, volume 1 part 3, page 24:
> +                * "If this bit is set, STCunit will have LRA as replacement
> +                *  policy. [...] This bit must be reset. LRA replacement
> +                *  policy is not supported."
> +                */
> +               wa_masked_dis(wal,
> +                             CACHE_MODE_0,
> +                             CM0_STC_EVICT_DISABLE_LRA_SNB);
> +       }
> +
> +       if (IS_GEN_RANGE(i915, 4, 6))
> +               /* WaTimedSingleVertexDispatch:cl,bw,ctg,elk,ilk,snb */
> +               wa_masked_en(wal,
> +                            MI_MODE,
> +                            VS_TIMER_DISPATCH);
>  }

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

Let's hope this holds up in testing, now that we expose it to the tests!

>  static void
> @@ -1475,7 +1526,7 @@ xcs_engine_wa_init(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  static void
>  engine_init_workarounds(struct intel_engine_cs *engine, struct i915_wa_list *wal)
>  {
> -       if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 8))
> +       if (I915_SELFTEST_ONLY(INTEL_GEN(engine->i915) < 4))
>                 return;
>  
>         if (engine->class == RENDER_CLASS)
> @@ -1488,7 +1539,7 @@ void intel_engine_init_workarounds(struct intel_engine_cs *engine)
>  {
>         struct i915_wa_list *wal = &engine->wa_list;
>  
> -       if (INTEL_GEN(engine->i915) < 8)
> +       if (INTEL_GEN(engine->i915) < 4)
>                 return;

Can we drop this yet? It's easy to overlook when extending the list of
w/a, so quite surprising.
-Chris
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Re: [Intel-gfx] [PATCH 1/2] drm/i915: extract engine WA programming to common resume function

[Chris Wilson]

Quoting Daniele Ceraolo Spurio (2020-01-29 23:58:59)
> The workarounds are a common "feature" across gens and submission
> mechanisms and we already call the other WA related functions from
> common engine ones (<setup/cleanup>_common), so it makes sense to
> do the same with WA application. Medium-term, This will help us
> reduce the duplication once the GuC resume function is added, but short
> term it will also allow us to use the workaround lists for pre-gen8
> engine workarounds.
> 
> Signed-off-by: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
> Cc: Chris Wilson <chris@chris-wilson.co.uk>
> Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
> Cc: Matthew Brost <matthew.brost@intel.com>

Ok, we've already made the apply functions gentle and not blow up when
called on early gen, and moving the apply into a common path doesn't
hinder future plans.

The only counter argument is that this is building a midlayer, and that
the point of vfuncs is that you call into the backend and the backend
picks and chooses which helpers to use.

So we have to be really confident that this is truly universal and not a
trap for future. But at the same time, we're quite adapt at
deconstructing when we need to.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
-Chris
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: extract engine WA programming to common resume function

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: extract engine WA programming to common resume function
URL   : https://patchwork.freedesktop.org/series/72753/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7840 -> Patchwork_16327
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16327 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16327, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16327:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_active:
    - fi-bwr-2160:        [PASS][1] -> [DMESG-WARN][2] +12 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bwr-2160/igt@i915_selftest@live_active.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bwr-2160/igt@i915_selftest@live_active.html

  * igt@i915_selftest@live_uncore:
    - fi-bwr-2160:        [PASS][3] -> [DMESG-FAIL][4] +2 similar issues
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bwr-2160/igt@i915_selftest@live_uncore.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bwr-2160/igt@i915_selftest@live_uncore.html

  
Known issues
------------

  Here are the changes found in Patchwork_16327 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_close_race@basic-threads:
    - fi-hsw-peppy:       [PASS][5] -> [TIMEOUT][6] ([fdo#112271])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-hsw-peppy/igt@gem_close_race@basic-threads.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-hsw-peppy/igt@gem_close_race@basic-threads.html

  * igt@gem_exec_parallel@fds:
    - fi-byt-n2820:       [PASS][7] -> [FAIL][8] ([i915#694]) +1 similar issue
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-byt-n2820/igt@gem_exec_parallel@fds.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-byt-n2820/igt@gem_exec_parallel@fds.html

  
#### Possible fixes ####

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][9] ([i915#178]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770:        [DMESG-FAIL][11] ([i915#725]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-hsw-4770/igt@i915_selftest@live_blt.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-hsw-4770/igt@i915_selftest@live_blt.html

  * igt@i915_selftest@live_gem_contexts:
    - fi-hsw-peppy:       [DMESG-FAIL][13] ([i915#722]) -> [PASS][14]
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-hsw-peppy/igt@i915_selftest@live_gem_contexts.html

  * igt@i915_selftest@live_gtt:
    - fi-bdw-5557u:       [TIMEOUT][15] ([fdo#112271]) -> [PASS][16]
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bdw-5557u/igt@i915_selftest@live_gtt.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bdw-5557u/igt@i915_selftest@live_gtt.html

  * igt@kms_chamelium@dp-crc-fast:
    - fi-kbl-7500u:       [FAIL][17] ([fdo#109635] / [i915#217]) -> [PASS][18]
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-kbl-7500u/igt@kms_chamelium@dp-crc-fast.html

  * igt@kms_chamelium@dp-edid-read:
    - fi-cml-u2:          [FAIL][19] ([i915#217]) -> [PASS][20]
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-cml-u2/igt@kms_chamelium@dp-edid-read.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][21] ([fdo#111096] / [i915#323]) -> [PASS][22]
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
  [fdo#109635]: https://bugs.freedesktop.org/show_bug.cgi?id=109635
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
  [i915#217]: https://gitlab.freedesktop.org/drm/intel/issues/217
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#694]: https://gitlab.freedesktop.org/drm/intel/issues/694
  [i915#722]: https://gitlab.freedesktop.org/drm/intel/issues/722
  [i915#725]: https://gitlab.freedesktop.org/drm/intel/issues/725


Participating hosts (52 -> 43)
------------------------------

  Missing    (9): fi-ilk-m540 fi-hsw-4200u fi-byt-squawks fi-bsw-cyan fi-ilk-650 fi-ivb-3770 fi-skl-lmem fi-byt-clapper fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7840 -> Patchwork_16327

  CI-20190529: 20190529
  CI_DRM_7840: 5a0adbdabc71233afe7d4463ea575c199ddbe787 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5406: 786c79af483a9f6e4688811f74116030c734ca1f @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16327: 92bdfdd2fc0ce56b2268e840a70882daa2c73453 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

92bdfdd2fc0c drm/i915: Move ringbuffer WAs to engine workaround list
0ebd52f87db6 drm/i915: extract engine WA programming to common resume function

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/index.html
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: extract engine WA programming to common resume function

[Chris Wilson]

Quoting Patchwork (2020-01-30 06:49:28)
> #### Possible regressions ####
> 
>   * igt@i915_selftest@live_active:
>     - fi-bwr-2160:        [PASS][1] -> [DMESG-WARN][2] +12 similar issues
>    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bwr-2160/igt@i915_selftest@live_active.html
>    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bwr-2160/igt@i915_selftest@live_active.html

Well it works on Crestline. Broadwater snafu?
-Chris
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: extract engine WA programming to common resume function

[Ville Syrjälä]

On Thu, Jan 30, 2020 at 01:37:49PM +0000, Chris Wilson wrote:
> Quoting Patchwork (2020-01-30 06:49:28)
> > #### Possible regressions ####
> > 
> >   * igt@i915_selftest@live_active:
> >     - fi-bwr-2160:        [PASS][1] -> [DMESG-WARN][2] +12 similar issues
> >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bwr-2160/igt@i915_selftest@live_active.html
> >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bwr-2160/igt@i915_selftest@live_active.html
> 
> Well it works on Crestline. Broadwater snafu?

Does the w/a thing actually work correctly for masked registers?
It look to use rmw even for masked registers and IIRC some masked
registers return 0xffff for the mask when read. I lost track of the
values and masks being passed around before I got down that deep so
can't immediatly see if the code is guaranteed to set only the
expected mask bit(s) for the write.

-- 
Ville Syrjälä
Intel
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: extract engine WA programming to common resume function

[Chris Wilson]

Quoting Ville Syrjälä (2020-01-30 13:58:13)
> On Thu, Jan 30, 2020 at 01:37:49PM +0000, Chris Wilson wrote:
> > Quoting Patchwork (2020-01-30 06:49:28)
> > > #### Possible regressions ####
> > > 
> > >   * igt@i915_selftest@live_active:
> > >     - fi-bwr-2160:        [PASS][1] -> [DMESG-WARN][2] +12 similar issues
> > >    [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bwr-2160/igt@i915_selftest@live_active.html
> > >    [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bwr-2160/igt@i915_selftest@live_active.html
> > 
> > Well it works on Crestline. Broadwater snafu?
> 
> Does the w/a thing actually work correctly for masked registers?
> It look to use rmw even for masked registers and IIRC some masked
> registers return 0xffff for the mask when read. I lost track of the
> values and masks being passed around before I got down that deep so
> can't immediatly see if the code is guaranteed to set only the
> expected mask bit(s) for the write.

The read back gives 0x10101, the w/a is to 0x400040 (and we expect to
see 0x40 set in the readback).

That part looks consistent (and is passing on gen4-gen6 except for CI's
bw).

Hmm, don't recall that it used rmw for setting the masked mmio, so lets
check that.
-Chris
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: extract engine WA programming to common resume function

[Daniele Ceraolo Spurio]

On 1/30/20 6:08 AM, Chris Wilson wrote:
> Quoting Ville Syrjälä (2020-01-30 13:58:13)
>> On Thu, Jan 30, 2020 at 01:37:49PM +0000, Chris Wilson wrote:
>>> Quoting Patchwork (2020-01-30 06:49:28)
>>>> #### Possible regressions ####
>>>>
>>>>    * igt@i915_selftest@live_active:
>>>>      - fi-bwr-2160:        [PASS][1] -> [DMESG-WARN][2] +12 similar issues
>>>>     [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bwr-2160/igt@i915_selftest@live_active.html
>>>>     [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bwr-2160/igt@i915_selftest@live_active.html
>>>
>>> Well it works on Crestline. Broadwater snafu?
>>
>> Does the w/a thing actually work correctly for masked registers?
>> It look to use rmw even for masked registers and IIRC some masked
>> registers return 0xffff for the mask when read. I lost track of the
>> values and masks being passed around before I got down that deep so
>> can't immediatly see if the code is guaranteed to set only the
>> expected mask bit(s) for the write.

But does it make any difference is the mask is returned or not with rmw? 
if it is, we reprogram the lower 16 bits with the original value + our 
diff, while if it isn't we just toggle in place the bit we're interested 
in. The result should be the same in both cases.

> 
> The read back gives 0x10101, the w/a is to 0x400040 (and we expect to
> see 0x40 set in the readback).

Looks like the result is also not constant. Initial load and a few of 
the reloads are fine and in some cases we also see the register being 
zeroed:

	(209c=0/0, expected 400040, mask=40)

Maybe something weird happening post-reset?

Daniele

> 
> That part looks consistent (and is passing on gen4-gen6 except for CI's
> bw).
> 
> Hmm, don't recall that it used rmw for setting the masked mmio, so lets
> check that.
> -Chris
> 
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Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: extract engine WA programming to common resume function

[Ville Syrjälä]

On Thu, Jan 30, 2020 at 11:20:00AM -0800, Daniele Ceraolo Spurio wrote:
> 
> 
> On 1/30/20 6:08 AM, Chris Wilson wrote:
> > Quoting Ville Syrjälä (2020-01-30 13:58:13)
> >> On Thu, Jan 30, 2020 at 01:37:49PM +0000, Chris Wilson wrote:
> >>> Quoting Patchwork (2020-01-30 06:49:28)
> >>>> #### Possible regressions ####
> >>>>
> >>>>    * igt@i915_selftest@live_active:
> >>>>      - fi-bwr-2160:        [PASS][1] -> [DMESG-WARN][2] +12 similar issues
> >>>>     [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7840/fi-bwr-2160/igt@i915_selftest@live_active.html
> >>>>     [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16327/fi-bwr-2160/igt@i915_selftest@live_active.html
> >>>
> >>> Well it works on Crestline. Broadwater snafu?
> >>
> >> Does the w/a thing actually work correctly for masked registers?
> >> It look to use rmw even for masked registers and IIRC some masked
> >> registers return 0xffff for the mask when read. I lost track of the
> >> values and masks being passed around before I got down that deep so
> >> can't immediatly see if the code is guaranteed to set only the
> >> expected mask bit(s) for the write.
> 
> But does it make any difference is the mask is returned or not with rmw? 
> if it is, we reprogram the lower 16 bits with the original value + our 
> diff, while if it isn't we just toggle in place the bit we're interested 
> in. The result should be the same in both cases.

Some bits can also have side effects (eg. sync flush trigger bits and
whatnot).

-- 
Ville Syrjälä
Intel
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[Intel-gfx] ✗ Fi.CI.BAT: failure for series starting with [1/2] drm/i915: extract engine WA programming to common resume function (rev2)

[Patchwork]

== Series Details ==

Series: series starting with [1/2] drm/i915: extract engine WA programming to common resume function (rev2)
URL   : https://patchwork.freedesktop.org/series/72753/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_7844 -> Patchwork_16338
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_16338 absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_16338, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/index.html

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_16338:

### IGT changes ###

#### Possible regressions ####

  * igt@i915_selftest@live_gt_lrc:
    - fi-bwr-2160:        [PASS][1] -> [DMESG-WARN][2] +12 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7844/fi-bwr-2160/igt@i915_selftest@live_gt_lrc.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/fi-bwr-2160/igt@i915_selftest@live_gt_lrc.html

  * igt@i915_selftest@live_uncore:
    - fi-bwr-2160:        [PASS][3] -> [DMESG-FAIL][4] +1 similar issue
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7844/fi-bwr-2160/igt@i915_selftest@live_uncore.html
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/fi-bwr-2160/igt@i915_selftest@live_uncore.html

  
Known issues
------------

  Here are the changes found in Patchwork_16338 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@i915_selftest@live_blt:
    - fi-hsw-4770r:       [PASS][5] -> [DMESG-FAIL][6] ([i915#563])
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7844/fi-hsw-4770r/igt@i915_selftest@live_blt.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/fi-hsw-4770r/igt@i915_selftest@live_blt.html

  
#### Possible fixes ####

  * igt@gem_close_race@basic-threads:
    - fi-byt-n2820:       [TIMEOUT][7] ([fdo#112271] / [i915#1084] / [i915#816]) -> [PASS][8]
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7844/fi-byt-n2820/igt@gem_close_race@basic-threads.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/fi-byt-n2820/igt@gem_close_race@basic-threads.html

  * igt@i915_pm_rpm@module-reload:
    - fi-skl-6770hq:      [FAIL][9] ([i915#178]) -> [PASS][10]
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7844/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/fi-skl-6770hq/igt@i915_pm_rpm@module-reload.html

  * igt@kms_chamelium@hdmi-hpd-fast:
    - fi-kbl-7500u:       [FAIL][11] ([fdo#111096] / [i915#323]) -> [PASS][12]
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7844/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/fi-kbl-7500u/igt@kms_chamelium@hdmi-hpd-fast.html

  
#### Warnings ####

  * igt@i915_pm_rpm@basic-rte:
    - fi-kbl-guc:         [SKIP][13] ([fdo#109271]) -> [FAIL][14] ([i915#704])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_7844/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/fi-kbl-guc/igt@i915_pm_rpm@basic-rte.html

  
  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [fdo#111096]: https://bugs.freedesktop.org/show_bug.cgi?id=111096
  [fdo#112271]: https://bugs.freedesktop.org/show_bug.cgi?id=112271
  [i915#1084]: https://gitlab.freedesktop.org/drm/intel/issues/1084
  [i915#178]: https://gitlab.freedesktop.org/drm/intel/issues/178
  [i915#323]: https://gitlab.freedesktop.org/drm/intel/issues/323
  [i915#563]: https://gitlab.freedesktop.org/drm/intel/issues/563
  [i915#704]: https://gitlab.freedesktop.org/drm/intel/issues/704
  [i915#816]: https://gitlab.freedesktop.org/drm/intel/issues/816


Participating hosts (46 -> 43)
------------------------------

  Additional (7): fi-glk-dsi fi-ilk-650 fi-whl-u fi-cfl-8109u fi-blb-e6850 fi-skl-6600u fi-kbl-r 
  Missing    (10): fi-icl-1065g7 fi-ilk-m540 fi-bdw-5557u fi-hsw-4200u fi-hsw-peppy fi-byt-squawks fi-bsw-cyan fi-skl-lmem fi-kbl-7560u fi-bdw-samus 


Build changes
-------------

  * CI: CI-20190529 -> None
  * Linux: CI_DRM_7844 -> Patchwork_16338

  CI-20190529: 20190529
  CI_DRM_7844: 47faa2a989ef89a15089190a5f942a2d2a34fda5 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_5407: a9d69f51dadbcbc53527671f87572d05c3370cba @ git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
  Patchwork_16338: 0ffdd4bb5d73aa6965410f663afa73268f3427d8 @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

0ffdd4bb5d73 drm/i915: Move ringbuffer WAs to engine workaround list
60ab9a27c1fb drm/i915: extract engine WA programming to common resume function

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_16338/index.html
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