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From: Andy Shevchenko <andriy.shevchenko-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>
To: "Srivastava,
	Shobhit"
	<shobhit.srivastava-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Cc: Jarkko Nikula
	<jarkko.nikula-VuQAYsv1563Yd54FQh9/CA@public.gmane.org>,
	Rajat Jain <rajatja-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
	Daniel Mack <daniel-cYrQPVfZoowdnm+yROfE0A@public.gmane.org>,
	Haojian Zhuang
	<haojian.zhuang-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	Robert Jarzmik <robert.jarzmik-GANU6spQydw@public.gmane.org>,
	Mark Brown <broonie-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org>,
	"linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org"
	<linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org>,
	"linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-spi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	"linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org"
	<linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org>,
	Evan Green <evgreen-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org>,
	"rajatxjain-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org"
	<rajatxjain-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org>,
	"evgreen-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org"
	<evgreen-hpIqsD4AKlfQT0dZR+AlfA@public.gmane.org>,
	"Muthukrishnan,
	Porselvan"
	<porselvan.muthukrishnan-ral2JQCrhuEAvxtiuMwx3w@public.gmane.org>
Subject: Re: Re: [PATCH] spi: pxa2xx: Add CS control clock quirk
Date: Thu, 13 Feb 2020 19:18:36 +0200	[thread overview]
Message-ID: <20200213171836.GD10400@smile.fi.intel.com> (raw)
In-Reply-To: <CB4ED07B85D6BB40B8B44F6D5442E4F6572C1523-yHIBzpp8AekElmVAvsQTrbfspsVTdybXVpNB7YpNyf8@public.gmane.org>

On Thu, Feb 13, 2020 at 04:57:24PM +0000, Srivastava, Shobhit wrote:
> > On 2/12/20 12:34 AM, Rajat Jain wrote:

...

> > I wonder is it enough to have this quick toggling only or is time or actually
> > number of clock cycles dependent? Now there is no delay between but I'm
> > thinking if it needs certain number cycles does this still work when using low
> > ssp_clk rates similar than in commit d0283eb2dbc1 ("spi:
> > pxa2xx: Add output control for multiple Intel LPSS chip selects").
> > 
> > I'm thinking can this be done only once after resume and may other LPSS
> > blocks need the same? I.e. should this be done in drivers/mfd/intel-lpss.c?

> This behavior is seen after S0ix resume, but it is not seen after S3 resume.

I already commented in the other thread about this.

Have you checked what's going on in intel_lpss_suspend() and
intel_lpss_resume() for your case?

Is intel_lpss_prepare() called during S0ix exit?

> I am thinking that it happens because we are not enabling the SSP after resume. 
> It is deferred until we need to send data. By enabling the SSP in resume, I don’t see the issue.
> For S3, I think BIOS re-enables the SSP in resume flow.

-- 
With Best Regards,
Andy Shevchenko

WARNING: multiple messages have this Message-ID (diff)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: "Srivastava, Shobhit" <shobhit.srivastava@intel.com>
Cc: Evan Green <evgreen@chromium.org>,
	"rajatxjain@gmail.com" <rajatxjain@gmail.com>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Haojian Zhuang <haojian.zhuang@gmail.com>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
	Mark Brown <broonie@kernel.org>,
	Jarkko Nikula <jarkko.nikula@linux.intel.com>,
	"linux-arm-kernel@lists.infradead.org"
	<linux-arm-kernel@lists.infradead.org>,
	"evgreen@google.com" <evgreen@google.com>,
	Rajat Jain <rajatja@google.com>,
	Robert Jarzmik <robert.jarzmik@free.fr>,
	Daniel Mack <daniel@zonque.org>,
	"Muthukrishnan, Porselvan" <porselvan.muthukrishnan@intel.com>
Subject: Re: Re: [PATCH] spi: pxa2xx: Add CS control clock quirk
Date: Thu, 13 Feb 2020 19:18:36 +0200	[thread overview]
Message-ID: <20200213171836.GD10400@smile.fi.intel.com> (raw)
In-Reply-To: <CB4ED07B85D6BB40B8B44F6D5442E4F6572C1523@BGSMSX101.gar.corp.intel.com>

On Thu, Feb 13, 2020 at 04:57:24PM +0000, Srivastava, Shobhit wrote:
> > On 2/12/20 12:34 AM, Rajat Jain wrote:

...

> > I wonder is it enough to have this quick toggling only or is time or actually
> > number of clock cycles dependent? Now there is no delay between but I'm
> > thinking if it needs certain number cycles does this still work when using low
> > ssp_clk rates similar than in commit d0283eb2dbc1 ("spi:
> > pxa2xx: Add output control for multiple Intel LPSS chip selects").
> > 
> > I'm thinking can this be done only once after resume and may other LPSS
> > blocks need the same? I.e. should this be done in drivers/mfd/intel-lpss.c?

> This behavior is seen after S0ix resume, but it is not seen after S3 resume.

I already commented in the other thread about this.

Have you checked what's going on in intel_lpss_suspend() and
intel_lpss_resume() for your case?

Is intel_lpss_prepare() called during S0ix exit?

> I am thinking that it happens because we are not enabling the SSP after resume. 
> It is deferred until we need to send data. By enabling the SSP in resume, I don’t see the issue.
> For S3, I think BIOS re-enables the SSP in resume flow.

-- 
With Best Regards,
Andy Shevchenko



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: "Srivastava, Shobhit" <shobhit.srivastava@intel.com>
Cc: Jarkko Nikula <jarkko.nikula@linux.intel.com>,
	Rajat Jain <rajatja@google.com>, Daniel Mack <daniel@zonque.org>,
	Haojian Zhuang <haojian.zhuang@gmail.com>,
	Robert Jarzmik <robert.jarzmik@free.fr>,
	Mark Brown <broonie@kernel.org>,
	"linux-arm-kernel@lists.infradead.org" 
	<linux-arm-kernel@lists.infradead.org>,
	"linux-spi@vger.kernel.org" <linux-spi@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Evan Green <evgreen@chromium.org>,
	"rajatxjain@gmail.com" <rajatxjain@gmail.com>,
	"evgreen@google.com" <evgreen@google.com>,
	"Muthukrishnan, Porselvan" <porselvan.muthukrishnan@intel.com>
Subject: Re: Re: [PATCH] spi: pxa2xx: Add CS control clock quirk
Date: Thu, 13 Feb 2020 19:18:36 +0200	[thread overview]
Message-ID: <20200213171836.GD10400@smile.fi.intel.com> (raw)
In-Reply-To: <CB4ED07B85D6BB40B8B44F6D5442E4F6572C1523@BGSMSX101.gar.corp.intel.com>

On Thu, Feb 13, 2020 at 04:57:24PM +0000, Srivastava, Shobhit wrote:
> > On 2/12/20 12:34 AM, Rajat Jain wrote:

...

> > I wonder is it enough to have this quick toggling only or is time or actually
> > number of clock cycles dependent? Now there is no delay between but I'm
> > thinking if it needs certain number cycles does this still work when using low
> > ssp_clk rates similar than in commit d0283eb2dbc1 ("spi:
> > pxa2xx: Add output control for multiple Intel LPSS chip selects").
> > 
> > I'm thinking can this be done only once after resume and may other LPSS
> > blocks need the same? I.e. should this be done in drivers/mfd/intel-lpss.c?

> This behavior is seen after S0ix resume, but it is not seen after S3 resume.

I already commented in the other thread about this.

Have you checked what's going on in intel_lpss_suspend() and
intel_lpss_resume() for your case?

Is intel_lpss_prepare() called during S0ix exit?

> I am thinking that it happens because we are not enabling the SSP after resume. 
> It is deferred until we need to send data. By enabling the SSP in resume, I don’t see the issue.
> For S3, I think BIOS re-enables the SSP in resume flow.

-- 
With Best Regards,
Andy Shevchenko



  parent reply	other threads:[~2020-02-13 17:18 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-02-13 16:57 Re: [PATCH] spi: pxa2xx: Add CS control clock quirk Srivastava, Shobhit
2020-02-13 16:57 ` Srivastava, Shobhit
     [not found] ` <CB4ED07B85D6BB40B8B44F6D5442E4F6572C1523-yHIBzpp8AekElmVAvsQTrbfspsVTdybXVpNB7YpNyf8@public.gmane.org>
2020-02-13 17:18   ` Andy Shevchenko [this message]
2020-02-13 17:18     ` Andy Shevchenko
2020-02-13 17:18     ` Andy Shevchenko
2020-02-14  6:26     ` Srivastava, Shobhit
2020-02-14  6:26       ` Srivastava, Shobhit
2020-02-24 21:28 ` Evan Green
2020-02-24 21:28   ` Evan Green

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