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From: Corey Wharton <coreyw7@fb.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: Palmer Dabbelt <palmer@dabbelt.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>,
	Corey Wharton <coreyw7@fb.com>
Subject: [PATCH 1/2] riscv: sifive_e: Support changing CPU type
Date: Thu, 12 Mar 2020 17:55:07 -0700	[thread overview]
Message-ID: <20200313005508.1906-2-coreyw7@fb.com> (raw)
In-Reply-To: <20200313005508.1906-1-coreyw7@fb.com>

Allows the CPU to be changed from the default via the -cpu command
line option.

Signed-off-by: Corey Wharton <coreyw7@fb.com>
---
 hw/riscv/sifive_e.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index a254cad489..b0a611adb9 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
     object_initialize_child(obj, "cpus", &s->cpus,
                             sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
                             &error_abort, NULL);
-    object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
+    object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
                             &error_abort);
@@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
     mc->desc = "RISC-V Board compatible with SiFive E SDK";
     mc->init = riscv_sifive_e_init;
     mc->max_cpus = 1;
+    mc->default_cpu_type = SIFIVE_E_CPU;
 }
 
 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
-- 
2.21.1



WARNING: multiple messages have this Message-ID (diff)
From: Corey Wharton <coreyw7@fb.com>
To: <qemu-devel@nongnu.org>, <qemu-riscv@nongnu.org>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	Corey Wharton <coreyw7@fb.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Sagar Karandikar <sagark@eecs.berkeley.edu>,
	Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Subject: [PATCH 1/2] riscv: sifive_e: Support changing CPU type
Date: Thu, 12 Mar 2020 17:55:07 -0700	[thread overview]
Message-ID: <20200313005508.1906-2-coreyw7@fb.com> (raw)
In-Reply-To: <20200313005508.1906-1-coreyw7@fb.com>

Allows the CPU to be changed from the default via the -cpu command
line option.

Signed-off-by: Corey Wharton <coreyw7@fb.com>
---
 hw/riscv/sifive_e.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index a254cad489..b0a611adb9 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
     object_initialize_child(obj, "cpus", &s->cpus,
                             sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
                             &error_abort, NULL);
-    object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
+    object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
                             &error_abort);
     object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
                             &error_abort);
@@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
     mc->desc = "RISC-V Board compatible with SiFive E SDK";
     mc->init = riscv_sifive_e_init;
     mc->max_cpus = 1;
+    mc->default_cpu_type = SIFIVE_E_CPU;
 }
 
 DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
-- 
2.21.1



  reply	other threads:[~2020-03-13  0:56 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-13  0:55 [PATCH 0/2] Support different CPU types for the sifive_e machine Corey Wharton
2020-03-13  0:55 ` Corey Wharton
2020-03-13  0:55 ` Corey Wharton [this message]
2020-03-13  0:55   ` [PATCH 1/2] riscv: sifive_e: Support changing CPU type Corey Wharton
2020-03-13 14:39   ` Bin Meng
2020-03-13 14:39     ` Bin Meng
2020-03-13 18:32   ` Alistair Francis
2020-03-13 18:32     ` Alistair Francis
2020-03-13  0:55 ` [PATCH 2/2] target/riscv: Add a sifive-e34 cpu type Corey Wharton
2020-03-13  0:55   ` Corey Wharton
2020-03-13 14:42   ` Bin Meng
2020-03-13 14:42     ` Bin Meng
  -- strict thread matches above, loose matches on Subject: below --
2020-03-13  0:29 [PATCH 0/2] Support different CPU types for the sifive_e machine Corey Wharton
2020-03-13  0:29 ` [PATCH 1/2] riscv: sifive_e: Support changing CPU type Corey Wharton
2020-03-13  0:29   ` Corey Wharton

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