* [PATCH 0/2] Support different CPU types for the sifive_e machine
@ 2020-03-13 0:55 ` Corey Wharton
0 siblings, 0 replies; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:55 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Corey Wharton
The purpose of this patch set is to allow the sifive_e machine to run
with different CPU targets to enable different ISA entensions. To that
end it also introduces a new sifive-e34 CPU type which provides the
same ISA as sifive-e31, with the addition of the single precision
floating-point extension (f). The default CPU for the sifive_e machine
is unchanged.
A user can change the default CPU type by specifying it with the '-cpu'
option on the command line.
Corey Wharton (2):
riscv: sifive_e: Support changing CPU type
target/riscv: Add a sifive-e34 cpu type
hw/riscv/sifive_e.c | 3 ++-
target/riscv/cpu.c | 10 ++++++++++
target/riscv/cpu.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
--
2.21.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/2] Support different CPU types for the sifive_e machine
@ 2020-03-13 0:55 ` Corey Wharton
0 siblings, 0 replies; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:55 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair Francis, Corey Wharton, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
The purpose of this patch set is to allow the sifive_e machine to run
with different CPU targets to enable different ISA entensions. To that
end it also introduces a new sifive-e34 CPU type which provides the
same ISA as sifive-e31, with the addition of the single precision
floating-point extension (f). The default CPU for the sifive_e machine
is unchanged.
A user can change the default CPU type by specifying it with the '-cpu'
option on the command line.
Corey Wharton (2):
riscv: sifive_e: Support changing CPU type
target/riscv: Add a sifive-e34 cpu type
hw/riscv/sifive_e.c | 3 ++-
target/riscv/cpu.c | 10 ++++++++++
target/riscv/cpu.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
--
2.21.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/2] riscv: sifive_e: Support changing CPU type
2020-03-13 0:55 ` Corey Wharton
@ 2020-03-13 0:55 ` Corey Wharton
-1 siblings, 0 replies; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:55 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Corey Wharton
Allows the CPU to be changed from the default via the -cpu command
line option.
Signed-off-by: Corey Wharton <coreyw7@fb.com>
---
hw/riscv/sifive_e.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index a254cad489..b0a611adb9 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus,
sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
&error_abort, NULL);
- object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
+ object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
@@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
mc->desc = "RISC-V Board compatible with SiFive E SDK";
mc->init = riscv_sifive_e_init;
mc->max_cpus = 1;
+ mc->default_cpu_type = SIFIVE_E_CPU;
}
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
--
2.21.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 1/2] riscv: sifive_e: Support changing CPU type
@ 2020-03-13 0:55 ` Corey Wharton
0 siblings, 0 replies; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:55 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair Francis, Corey Wharton, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
Allows the CPU to be changed from the default via the -cpu command
line option.
Signed-off-by: Corey Wharton <coreyw7@fb.com>
---
hw/riscv/sifive_e.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index a254cad489..b0a611adb9 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus,
sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
&error_abort, NULL);
- object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
+ object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
@@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
mc->desc = "RISC-V Board compatible with SiFive E SDK";
mc->init = riscv_sifive_e_init;
mc->max_cpus = 1;
+ mc->default_cpu_type = SIFIVE_E_CPU;
}
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
--
2.21.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 1/2] riscv: sifive_e: Support changing CPU type
2020-03-13 0:55 ` Corey Wharton
@ 2020-03-13 14:39 ` Bin Meng
-1 siblings, 0 replies; 14+ messages in thread
From: Bin Meng @ 2020-03-13 14:39 UTC (permalink / raw)
To: Corey Wharton
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
On Fri, Mar 13, 2020 at 8:57 AM Corey Wharton <coreyw7@fb.com> wrote:
>
> Allows the CPU to be changed from the default via the -cpu command
> line option.
>
> Signed-off-by: Corey Wharton <coreyw7@fb.com>
> ---
> hw/riscv/sifive_e.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] riscv: sifive_e: Support changing CPU type
@ 2020-03-13 14:39 ` Bin Meng
0 siblings, 0 replies; 14+ messages in thread
From: Bin Meng @ 2020-03-13 14:39 UTC (permalink / raw)
To: Corey Wharton
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Fri, Mar 13, 2020 at 8:57 AM Corey Wharton <coreyw7@fb.com> wrote:
>
> Allows the CPU to be changed from the default via the -cpu command
> line option.
>
> Signed-off-by: Corey Wharton <coreyw7@fb.com>
> ---
> hw/riscv/sifive_e.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/2] riscv: sifive_e: Support changing CPU type
2020-03-13 0:55 ` Corey Wharton
@ 2020-03-13 18:32 ` Alistair Francis
-1 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-03-13 18:32 UTC (permalink / raw)
To: Corey Wharton
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
On Thu, Mar 12, 2020 at 5:58 PM Corey Wharton <coreyw7@fb.com> wrote:
>
> Allows the CPU to be changed from the default via the -cpu command
> line option.
>
> Signed-off-by: Corey Wharton <coreyw7@fb.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/sifive_e.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index a254cad489..b0a611adb9 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
> object_initialize_child(obj, "cpus", &s->cpus,
> sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
> &error_abort, NULL);
> - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
> + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
> &error_abort);
> object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
> &error_abort);
> @@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
> mc->desc = "RISC-V Board compatible with SiFive E SDK";
> mc->init = riscv_sifive_e_init;
> mc->max_cpus = 1;
> + mc->default_cpu_type = SIFIVE_E_CPU;
> }
>
> DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
> --
> 2.21.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 1/2] riscv: sifive_e: Support changing CPU type
@ 2020-03-13 18:32 ` Alistair Francis
0 siblings, 0 replies; 14+ messages in thread
From: Alistair Francis @ 2020-03-13 18:32 UTC (permalink / raw)
To: Corey Wharton
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Thu, Mar 12, 2020 at 5:58 PM Corey Wharton <coreyw7@fb.com> wrote:
>
> Allows the CPU to be changed from the default via the -cpu command
> line option.
>
> Signed-off-by: Corey Wharton <coreyw7@fb.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> hw/riscv/sifive_e.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index a254cad489..b0a611adb9 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
> object_initialize_child(obj, "cpus", &s->cpus,
> sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
> &error_abort, NULL);
> - object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
> + object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
> &error_abort);
> object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
> &error_abort);
> @@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
> mc->desc = "RISC-V Board compatible with SiFive E SDK";
> mc->init = riscv_sifive_e_init;
> mc->max_cpus = 1;
> + mc->default_cpu_type = SIFIVE_E_CPU;
> }
>
> DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
> --
> 2.21.1
>
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 2/2] target/riscv: Add a sifive-e34 cpu type
2020-03-13 0:55 ` Corey Wharton
@ 2020-03-13 0:55 ` Corey Wharton
-1 siblings, 0 replies; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:55 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Corey Wharton
The sifive-e34 cpu type is the same as the sifive-e31 with the
single precision floating-point extension enabled.
Signed-off-by: Corey Wharton <coreyw7@fb.com>
---
target/riscv/cpu.c | 10 ++++++++++
target/riscv/cpu.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c0b7023100..d415cd06eb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
set_feature(env, RISCV_FEATURE_PMP);
}
+static void rv32imafcu_nommu_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC);
+ set_priv_version(env, PRIV_VERSION_1_10_0);
+ set_resetvec(env, DEFAULT_RSTVEC);
+ set_feature(env, RISCV_FEATURE_PMP);
+}
+
#elif defined(TARGET_RISCV64)
static void riscv_base64_cpu_init(Object *obj)
@@ -609,6 +618,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
/* Depreacted */
DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3dcdf92227..ae5a1d9dce 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -36,6 +36,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
+#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
--
2.21.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 2/2] target/riscv: Add a sifive-e34 cpu type
@ 2020-03-13 0:55 ` Corey Wharton
0 siblings, 0 replies; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:55 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair Francis, Corey Wharton, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
The sifive-e34 cpu type is the same as the sifive-e31 with the
single precision floating-point extension enabled.
Signed-off-by: Corey Wharton <coreyw7@fb.com>
---
target/riscv/cpu.c | 10 ++++++++++
target/riscv/cpu.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c0b7023100..d415cd06eb 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
set_feature(env, RISCV_FEATURE_PMP);
}
+static void rv32imafcu_nommu_cpu_init(Object *obj)
+{
+ CPURISCVState *env = &RISCV_CPU(obj)->env;
+ set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC);
+ set_priv_version(env, PRIV_VERSION_1_10_0);
+ set_resetvec(env, DEFAULT_RSTVEC);
+ set_feature(env, RISCV_FEATURE_PMP);
+}
+
#elif defined(TARGET_RISCV64)
static void riscv_base64_cpu_init(Object *obj)
@@ -609,6 +618,7 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
+ DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E34, rv32imafcu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init),
/* Depreacted */
DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 3dcdf92227..ae5a1d9dce 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -36,6 +36,7 @@
#define TYPE_RISCV_CPU_BASE32 RISCV_CPU_TYPE_NAME("rv32")
#define TYPE_RISCV_CPU_BASE64 RISCV_CPU_TYPE_NAME("rv64")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
+#define TYPE_RISCV_CPU_SIFIVE_E34 RISCV_CPU_TYPE_NAME("sifive-e34")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
#define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54")
--
2.21.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH 2/2] target/riscv: Add a sifive-e34 cpu type
2020-03-13 0:55 ` Corey Wharton
@ 2020-03-13 14:42 ` Bin Meng
-1 siblings, 0 replies; 14+ messages in thread
From: Bin Meng @ 2020-03-13 14:42 UTC (permalink / raw)
To: Corey Wharton
Cc: qemu-devel@nongnu.org Developers, open list:RISC-V,
Alistair Francis, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
On Fri, Mar 13, 2020 at 9:00 AM Corey Wharton <coreyw7@fb.com> wrote:
>
> The sifive-e34 cpu type is the same as the sifive-e31 with the
> single precision floating-point extension enabled.
>
> Signed-off-by: Corey Wharton <coreyw7@fb.com>
> ---
> target/riscv/cpu.c | 10 ++++++++++
> target/riscv/cpu.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c0b7023100..d415cd06eb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
> set_feature(env, RISCV_FEATURE_PMP);
> }
>
> +static void rv32imafcu_nommu_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC);
This is missing RVU.
> + set_priv_version(env, PRIV_VERSION_1_10_0);
> + set_resetvec(env, DEFAULT_RSTVEC);
> + set_feature(env, RISCV_FEATURE_PMP);
> +}
> +
> #elif defined(TARGET_RISCV64)
>
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PATCH 2/2] target/riscv: Add a sifive-e34 cpu type
@ 2020-03-13 14:42 ` Bin Meng
0 siblings, 0 replies; 14+ messages in thread
From: Bin Meng @ 2020-03-13 14:42 UTC (permalink / raw)
To: Corey Wharton
Cc: open list:RISC-V, Sagar Karandikar, Bastian Koppelmann,
qemu-devel@nongnu.org Developers, Alistair Francis,
Palmer Dabbelt
On Fri, Mar 13, 2020 at 9:00 AM Corey Wharton <coreyw7@fb.com> wrote:
>
> The sifive-e34 cpu type is the same as the sifive-e31 with the
> single precision floating-point extension enabled.
>
> Signed-off-by: Corey Wharton <coreyw7@fb.com>
> ---
> target/riscv/cpu.c | 10 ++++++++++
> target/riscv/cpu.h | 1 +
> 2 files changed, 11 insertions(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index c0b7023100..d415cd06eb 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -164,6 +164,15 @@ static void rv32imacu_nommu_cpu_init(Object *obj)
> set_feature(env, RISCV_FEATURE_PMP);
> }
>
> +static void rv32imafcu_nommu_cpu_init(Object *obj)
> +{
> + CPURISCVState *env = &RISCV_CPU(obj)->env;
> + set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVC);
This is missing RVU.
> + set_priv_version(env, PRIV_VERSION_1_10_0);
> + set_resetvec(env, DEFAULT_RSTVEC);
> + set_feature(env, RISCV_FEATURE_PMP);
> +}
> +
> #elif defined(TARGET_RISCV64)
>
[snip]
Regards,
Bin
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 0/2] Support different CPU types for the sifive_e machine
@ 2020-03-13 0:29 Corey Wharton
2020-03-13 0:29 ` Corey Wharton
0 siblings, 1 reply; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:29 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Corey Wharton
The purpose of this patch set is to allow the sifive_e machine to run
with different CPU targets to enable different ISA entensions. To that
end it also introduces a new sifive-e34 CPU type which provides the
same ISA as sifive-e31, with the addition of the single precision
floating-point extension (f). The default CPU for the sifive_e machine
is unchanged.
A user can change the default CPU type by specifying it with the '-cpu'
option on the command line.
Corey Wharton (2):
riscv: sifive_e: Support changing CPU type
target/riscv: Add a sifive-e34 cpu type
hw/riscv/sifive_e.c | 3 ++-
target/riscv/cpu.c | 10 ++++++++++
target/riscv/cpu.h | 1 +
3 files changed, 13 insertions(+), 1 deletion(-)
--
2.21.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/2] riscv: sifive_e: Support changing CPU type
2020-03-13 0:29 [PATCH 0/2] Support different CPU types for the sifive_e machine Corey Wharton
@ 2020-03-13 0:29 ` Corey Wharton
0 siblings, 0 replies; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:29 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Palmer Dabbelt, Alistair Francis, Sagar Karandikar,
Bastian Koppelmann, Corey Wharton
Allows the CPU to be changed from the default via the -cpu command
line option.
Signed-off-by: Corey Wharton <coreyw7@fb.com>
---
hw/riscv/sifive_e.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index a254cad489..b0a611adb9 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus,
sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
&error_abort, NULL);
- object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
+ object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
@@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
mc->desc = "RISC-V Board compatible with SiFive E SDK";
mc->init = riscv_sifive_e_init;
mc->max_cpus = 1;
+ mc->default_cpu_type = SIFIVE_E_CPU;
}
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
--
2.21.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH 1/2] riscv: sifive_e: Support changing CPU type
@ 2020-03-13 0:29 ` Corey Wharton
0 siblings, 0 replies; 14+ messages in thread
From: Corey Wharton @ 2020-03-13 0:29 UTC (permalink / raw)
To: qemu-devel, qemu-riscv
Cc: Alistair Francis, Corey Wharton, Palmer Dabbelt, Sagar Karandikar,
Bastian Koppelmann
Allows the CPU to be changed from the default via the -cpu command
line option.
Signed-off-by: Corey Wharton <coreyw7@fb.com>
---
hw/riscv/sifive_e.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index a254cad489..b0a611adb9 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -123,7 +123,7 @@ static void riscv_sifive_e_soc_init(Object *obj)
object_initialize_child(obj, "cpus", &s->cpus,
sizeof(s->cpus), TYPE_RISCV_HART_ARRAY,
&error_abort, NULL);
- object_property_set_str(OBJECT(&s->cpus), SIFIVE_E_CPU, "cpu-type",
+ object_property_set_str(OBJECT(&s->cpus), ms->cpu_type, "cpu-type",
&error_abort);
object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts",
&error_abort);
@@ -220,6 +220,7 @@ static void riscv_sifive_e_machine_init(MachineClass *mc)
mc->desc = "RISC-V Board compatible with SiFive E SDK";
mc->init = riscv_sifive_e_init;
mc->max_cpus = 1;
+ mc->default_cpu_type = SIFIVE_E_CPU;
}
DEFINE_MACHINE("sifive_e", riscv_sifive_e_machine_init)
--
2.21.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
end of thread, other threads:[~2020-03-13 18:33 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz follow: Atom feed
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2020-03-13 0:55 [PATCH 0/2] Support different CPU types for the sifive_e machine Corey Wharton
2020-03-13 0:55 ` Corey Wharton
2020-03-13 0:55 ` [PATCH 1/2] riscv: sifive_e: Support changing CPU type Corey Wharton
2020-03-13 0:55 ` Corey Wharton
2020-03-13 14:39 ` Bin Meng
2020-03-13 14:39 ` Bin Meng
2020-03-13 18:32 ` Alistair Francis
2020-03-13 18:32 ` Alistair Francis
2020-03-13 0:55 ` [PATCH 2/2] target/riscv: Add a sifive-e34 cpu type Corey Wharton
2020-03-13 0:55 ` Corey Wharton
2020-03-13 14:42 ` Bin Meng
2020-03-13 14:42 ` Bin Meng
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2020-03-13 0:29 [PATCH 0/2] Support different CPU types for the sifive_e machine Corey Wharton
2020-03-13 0:29 ` [PATCH 1/2] riscv: sifive_e: Support changing CPU type Corey Wharton
2020-03-13 0:29 ` Corey Wharton
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