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From: Catalin Marinas <catalin.marinas@arm.com>
To: Will Deacon <will@kernel.org>
Cc: Ard Biesheuvel <ardb@kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	kernel-hardening@lists.openwall.com,
	Mark Rutland <mark.rutland@arm.com>
Subject: Re: [RFC PATCH] arm64: remove CONFIG_DEBUG_ALIGN_RODATA feature
Date: Thu, 7 May 2020 14:43:00 +0100	[thread overview]
Message-ID: <20200507134259.GA3180@gaia> (raw)
In-Reply-To: <20200505104404.GB19710@willie-the-truck>

On Tue, May 05, 2020 at 11:44:06AM +0100, Will Deacon wrote:
> Catalin -- did you get anything back from the architects about the cache
> hit behaviour?

Any read from a non-cacheable alias would be coherent with writes using
the same non-cacheable attributes, irrespective of other cacheable
aliases (of course, subject to the cache lines having been previously
cleaned/invalidated to avoid dirty lines evictions).

So as long as the hardware works as per the ARM ARM (B2.8), we don't
need to unmap the non-cacheable DMA buffers from the linear map.

-- 
Catalin

WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Ard Biesheuvel <ardb@kernel.org>,
	Linux ARM <linux-arm-kernel@lists.infradead.org>,
	kernel-hardening@lists.openwall.com
Subject: Re: [RFC PATCH] arm64: remove CONFIG_DEBUG_ALIGN_RODATA feature
Date: Thu, 7 May 2020 14:43:00 +0100	[thread overview]
Message-ID: <20200507134259.GA3180@gaia> (raw)
In-Reply-To: <20200505104404.GB19710@willie-the-truck>

On Tue, May 05, 2020 at 11:44:06AM +0100, Will Deacon wrote:
> Catalin -- did you get anything back from the architects about the cache
> hit behaviour?

Any read from a non-cacheable alias would be coherent with writes using
the same non-cacheable attributes, irrespective of other cacheable
aliases (of course, subject to the cache lines having been previously
cleaned/invalidated to avoid dirty lines evictions).

So as long as the hardware works as per the ARM ARM (B2.8), we don't
need to unmap the non-cacheable DMA buffers from the linear map.

-- 
Catalin

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  reply	other threads:[~2020-05-07 13:43 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-03-29 14:12 [RFC PATCH] arm64: remove CONFIG_DEBUG_ALIGN_RODATA feature Ard Biesheuvel
2020-03-29 14:12 ` Ard Biesheuvel
2020-03-30 11:29 ` Mark Rutland
2020-03-30 11:29   ` Mark Rutland
2020-03-30 12:36   ` Ard Biesheuvel
2020-03-30 12:36     ` Ard Biesheuvel
2020-03-30 13:51 ` Will Deacon
2020-03-30 13:51   ` Will Deacon
2020-03-30 13:53   ` Ard Biesheuvel
2020-03-30 13:53     ` Ard Biesheuvel
2020-03-30 13:59     ` Robin Murphy
2020-03-30 13:59       ` Robin Murphy
2020-03-30 14:04     ` Will Deacon
2020-03-30 14:04       ` Will Deacon
2020-03-30 14:22       ` Ard Biesheuvel
2020-03-30 14:22         ` Ard Biesheuvel
2020-03-30 14:28         ` Will Deacon
2020-03-30 14:28           ` Will Deacon
2020-03-30 14:32           ` Ard Biesheuvel
2020-03-30 14:32             ` Ard Biesheuvel
2020-04-02 11:30             ` Catalin Marinas
2020-04-02 11:30               ` Catalin Marinas
2020-04-02 12:17               ` Mark Rutland
2020-04-02 12:17                 ` Mark Rutland
2020-04-03  7:07               ` Will Deacon
2020-04-03  7:07                 ` Will Deacon
2020-04-03  8:58               ` Ard Biesheuvel
2020-04-03  8:58                 ` Ard Biesheuvel
2020-05-05 10:44                 ` Will Deacon
2020-05-05 10:44                   ` Will Deacon
2020-05-07 13:43                   ` Catalin Marinas [this message]
2020-05-07 13:43                     ` Catalin Marinas
2020-03-30 13:57 ` Laura Abbott
2020-03-30 13:57   ` Laura Abbott
2020-04-02 11:15 ` Catalin Marinas
2020-04-02 11:15   ` Catalin Marinas
2020-04-02 11:24   ` Ard Biesheuvel
2020-04-02 11:24     ` Ard Biesheuvel

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