All of lore.kernel.org
 help / color / mirror / Atom feed
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Cc: peter.ujfalusi@ti.com, richard@nod.at,
	linux-mtd@lists.infradead.org, vigneshr@ti.com,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 1/2] mtd: rawnand: qcom: remove write to unavailable register
Date: Tue, 9 Jun 2020 16:02:17 +0200	[thread overview]
Message-ID: <20200609160217.0b111883@xps13> (raw)
In-Reply-To: <1591701056-3944-2-git-send-email-sivaprak@codeaurora.org>

Hi Sivaprakash,

Sivaprakash Murugesan <sivaprak@codeaurora.org> wrote on Tue,  9 Jun
2020 16:40:55 +0530:

> SFLASHC_BURST_CFG register is not available on all ipq nand platforms,
> it is available only on ipq8064 devices and the nand controller works
> without configuring these registers in this platform, so register write
> to this can be removed.

Maybe it works because the bootloader is setting the register itself.
What if you use a different bootloader, or the same bootloader without
NAND support?

I don't think this is a proper fix, you should instead have a different
compatible if the IP is not the same and depending on this compatible
do the write, or not.

> 
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
>  drivers/mtd/nand/raw/qcom_nandc.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index 5b11c70..e0afa2c 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -36,7 +36,6 @@
>  #define	NAND_DEV_CMD1			0xa4
>  #define	NAND_DEV_CMD2			0xa8
>  #define	NAND_DEV_CMD_VLD		0xac
> -#define	SFLASHC_BURST_CFG		0xe0
>  #define	NAND_ERASED_CW_DETECT_CFG	0xe8
>  #define	NAND_ERASED_CW_DETECT_STATUS	0xec
>  #define	NAND_EBI2_ECC_BUF_CFG		0xf0
> @@ -2774,7 +2773,6 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>  	u32 nand_ctrl;
>  
>  	/* kill onenand */
> -	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>  	nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
>  		    NAND_DEV_CMD_VLD_VAL);
>  

Thanks,
Miquèl

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Sivaprakash Murugesan <sivaprak@codeaurora.org>
Cc: richard@nod.at, vigneshr@ti.com, peter.ujfalusi@ti.com,
	linux-mtd@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH V2 1/2] mtd: rawnand: qcom: remove write to unavailable register
Date: Tue, 9 Jun 2020 16:02:17 +0200	[thread overview]
Message-ID: <20200609160217.0b111883@xps13> (raw)
In-Reply-To: <1591701056-3944-2-git-send-email-sivaprak@codeaurora.org>

Hi Sivaprakash,

Sivaprakash Murugesan <sivaprak@codeaurora.org> wrote on Tue,  9 Jun
2020 16:40:55 +0530:

> SFLASHC_BURST_CFG register is not available on all ipq nand platforms,
> it is available only on ipq8064 devices and the nand controller works
> without configuring these registers in this platform, so register write
> to this can be removed.

Maybe it works because the bootloader is setting the register itself.
What if you use a different bootloader, or the same bootloader without
NAND support?

I don't think this is a proper fix, you should instead have a different
compatible if the IP is not the same and depending on this compatible
do the write, or not.

> 
> Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org>
> ---
>  drivers/mtd/nand/raw/qcom_nandc.c | 2 --
>  1 file changed, 2 deletions(-)
> 
> diff --git a/drivers/mtd/nand/raw/qcom_nandc.c b/drivers/mtd/nand/raw/qcom_nandc.c
> index 5b11c70..e0afa2c 100644
> --- a/drivers/mtd/nand/raw/qcom_nandc.c
> +++ b/drivers/mtd/nand/raw/qcom_nandc.c
> @@ -36,7 +36,6 @@
>  #define	NAND_DEV_CMD1			0xa4
>  #define	NAND_DEV_CMD2			0xa8
>  #define	NAND_DEV_CMD_VLD		0xac
> -#define	SFLASHC_BURST_CFG		0xe0
>  #define	NAND_ERASED_CW_DETECT_CFG	0xe8
>  #define	NAND_ERASED_CW_DETECT_STATUS	0xec
>  #define	NAND_EBI2_ECC_BUF_CFG		0xf0
> @@ -2774,7 +2773,6 @@ static int qcom_nandc_setup(struct qcom_nand_controller *nandc)
>  	u32 nand_ctrl;
>  
>  	/* kill onenand */
> -	nandc_write(nandc, SFLASHC_BURST_CFG, 0);
>  	nandc_write(nandc, dev_cmd_reg_addr(nandc, NAND_DEV_CMD_VLD),
>  		    NAND_DEV_CMD_VLD_VAL);
>  

Thanks,
Miquèl

  reply	other threads:[~2020-06-09 14:02 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-09 11:10 [PATCH V2 0/2] Fix issues related to register access in IPQ NAND Sivaprakash Murugesan
2020-06-09 11:10 ` Sivaprakash Murugesan
2020-06-09 11:10 ` [PATCH V2 1/2] mtd: rawnand: qcom: remove write to unavailable register Sivaprakash Murugesan
2020-06-09 11:10   ` Sivaprakash Murugesan
2020-06-09 14:02   ` Miquel Raynal [this message]
2020-06-09 14:02     ` Miquel Raynal
2020-06-11  4:30     ` Sivaprakash Murugesan
2020-06-11  4:30       ` Sivaprakash Murugesan
2020-06-09 11:10 ` [PATCH V2 2/2] mtd: rawnand: qcom: set BAM mode only if not set already Sivaprakash Murugesan
2020-06-09 11:10   ` Sivaprakash Murugesan
2020-06-09 14:03   ` Miquel Raynal
2020-06-09 14:03     ` Miquel Raynal
2020-06-11  4:27     ` Sivaprakash Murugesan
2020-06-11  4:27       ` Sivaprakash Murugesan
2020-06-11  7:13       ` Miquel Raynal
2020-06-11  7:13         ` Miquel Raynal

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20200609160217.0b111883@xps13 \
    --to=miquel.raynal@bootlin.com \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-mtd@lists.infradead.org \
    --cc=peter.ujfalusi@ti.com \
    --cc=richard@nod.at \
    --cc=sivaprak@codeaurora.org \
    --cc=vigneshr@ti.com \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.