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From: hhk7734@gmail.com
To: linus.walleij@linaro.org, khilman@baylibre.com
Cc: linux-gpio@vger.kernel.org, Hyeonki Hong <hhk7734@gmail.com>,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org
Subject: [PATCH] pinctrl: meson: fix drive strength register and bit calculation
Date: Wed, 10 Jun 2020 13:13:29 +0900	[thread overview]
Message-ID: <20200610041329.12948-1-hhk7734@gmail.com> (raw)

From: Hyeonki Hong <hhk7734@gmail.com>

If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two
registers. However, when register and bit were calculated, the first
register defined in the bank was used, and the bit was calculated based
on the first pin. This causes problems in setting the driving strength.

Solved the problem by changing the bit using a mask and selecting the
next register when the bit exceeds 15.

Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
---
 drivers/pinctrl/meson/pinctrl-meson.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index bbc919bef2bf..ef66239b7df5 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -98,6 +98,13 @@ static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,

 	*reg = desc->reg * 4;
 	*bit = desc->bit + pin - bank->first;
+
+	if (reg_type == REG_DS) {
+		if (*bit > 15) {
+			*bit &= 0xf;
+			*reg += 4;
+		}
+	}
 }

 static int meson_get_groups_count(struct pinctrl_dev *pcdev)
--
2.17.1

_______________________________________________
linux-amlogic mailing list
linux-amlogic@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-amlogic

WARNING: multiple messages have this Message-ID (diff)
From: hhk7734@gmail.com
To: linus.walleij@linaro.org, khilman@baylibre.com
Cc: linux-gpio@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org, linux-kernel@vger.kernel.org,
	Hyeonki Hong <hhk7734@gmail.com>
Subject: [PATCH] pinctrl: meson: fix drive strength register and bit calculation
Date: Wed, 10 Jun 2020 13:13:29 +0900	[thread overview]
Message-ID: <20200610041329.12948-1-hhk7734@gmail.com> (raw)

From: Hyeonki Hong <hhk7734@gmail.com>

If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two
registers. However, when register and bit were calculated, the first
register defined in the bank was used, and the bit was calculated based
on the first pin. This causes problems in setting the driving strength.

Solved the problem by changing the bit using a mask and selecting the
next register when the bit exceeds 15.

Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
---
 drivers/pinctrl/meson/pinctrl-meson.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index bbc919bef2bf..ef66239b7df5 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -98,6 +98,13 @@ static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,

 	*reg = desc->reg * 4;
 	*bit = desc->bit + pin - bank->first;
+
+	if (reg_type == REG_DS) {
+		if (*bit > 15) {
+			*bit &= 0xf;
+			*reg += 4;
+		}
+	}
 }

 static int meson_get_groups_count(struct pinctrl_dev *pcdev)
--
2.17.1

WARNING: multiple messages have this Message-ID (diff)
From: hhk7734@gmail.com
To: linus.walleij@linaro.org, khilman@baylibre.com
Cc: linux-gpio@vger.kernel.org, Hyeonki Hong <hhk7734@gmail.com>,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org,
	linux-amlogic@lists.infradead.org
Subject: [PATCH] pinctrl: meson: fix drive strength register and bit calculation
Date: Wed, 10 Jun 2020 13:13:29 +0900	[thread overview]
Message-ID: <20200610041329.12948-1-hhk7734@gmail.com> (raw)

From: Hyeonki Hong <hhk7734@gmail.com>

If a GPIO bank has greater than 16 pins, PAD_DS_REG is split into two
registers. However, when register and bit were calculated, the first
register defined in the bank was used, and the bit was calculated based
on the first pin. This causes problems in setting the driving strength.

Solved the problem by changing the bit using a mask and selecting the
next register when the bit exceeds 15.

Signed-off-by: Hyeonki Hong <hhk7734@gmail.com>
---
 drivers/pinctrl/meson/pinctrl-meson.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index bbc919bef2bf..ef66239b7df5 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -98,6 +98,13 @@ static void meson_calc_reg_and_bit(struct meson_bank *bank, unsigned int pin,

 	*reg = desc->reg * 4;
 	*bit = desc->bit + pin - bank->first;
+
+	if (reg_type == REG_DS) {
+		if (*bit > 15) {
+			*bit &= 0xf;
+			*reg += 4;
+		}
+	}
 }

 static int meson_get_groups_count(struct pinctrl_dev *pcdev)
--
2.17.1

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

             reply	other threads:[~2020-06-10  4:14 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-06-10  4:13 hhk7734 [this message]
2020-06-10  4:13 ` [PATCH] pinctrl: meson: fix drive strength register and bit calculation hhk7734
2020-06-10  4:13 ` hhk7734
2020-06-10 13:09 ` Jerome Brunet
2020-06-10 13:09   ` Jerome Brunet
2020-06-10 13:09   ` Jerome Brunet
2020-06-11  5:40   ` Hyeonki Hong
2020-06-11  5:40     ` Hyeonki Hong
2020-06-11  5:40     ` Hyeonki Hong
2020-06-17 13:59     ` Jerome Brunet
2020-06-17 13:59       ` Jerome Brunet
2020-06-17 13:59       ` Jerome Brunet

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